BRUCE SMITH
` UNITED STATES PATENT AND TRADEMARK OFFICE
` BEFORE THE PATENT TRIAL AND APPEAL BOARD
`----------------------------------------
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
` Petitioner,
` - vs -
`GODO KAISHA IP BRIDGE 1,
` Patent Owner.
` Case IPR2016-01376
` Patent 6,197,696
`----------------------------------------
` Examination before trial of BRUCE SMITH,
`taken pursuant to 37 C.F.R. Section 42.53, at the
`Hilton Garden Inn Rochester, 30 Celebration Drive,
`Rochester, New York, on March 23, 2017, commencing
`at 9:05 a.m., before JOAN M. METZGER-HUBBELL, CRR,
`RMR, RPR, Notary Public.
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`TSMC v. IP Bridge
`IPR2016-01379
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` UNITED STATES PATENT AND TRADEMARK OFFICE
` BEFORE THE PATENT TRIAL AND APPEAL BOARD
`----------------------------------------
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
` Petitioner,
` - vs -
`GODO KAISHA IP BRIDGE 1,
` Patent Owner.
` Case IPR2016-01376
` Patent 6,197,696
`----------------------------------------
` Examination before trial of BRUCE SMITH,
`taken pursuant to 37 C.F.R. Section 42.53, at the
`Hilton Garden Inn Rochester, 30 Celebration Drive,
`Rochester, New York, on March 23, 2017, commencing
`at 9:05 a.m., before JOAN M. METZGER-HUBBELL, CRR,
`RMR, RPR, Notary Public.
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`Transcript of Bruce Smith
`Conducted on March 23, 2017
`
`2
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`APPEARANCES: FINNEGAN, HENDERSON, FARABOW,
` GARRETT & DUNNER, LLP,
` By DARREN M. JIRON, ESQ.,
` Two Freedom Square,
` 11955 Freedom Drive,
` Reston, Virginia 20190-5675,
` (571) 203-2729,
` darren.jiron@finnegan.com,
` and
` FINNEGAN, HENDERSON, FARABOW,
` GARRETT & DUNNER, LLP,
` By J. PRESTON (J.P.) LONG, ESQ.,
` 901 New York Avenue, NW,
` Washington, D.C. 20001-4413,
` (202) 408-4000,
` jp.long@finnegan.com,
` Appearing for the Petitioner.
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`3
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` ROPES & GRAY LLP,
` By JORDAN M. ROSSEN, ESQ.,
` 2099 Pennsylvania Avenue, N.W.,
` Washington, D.C. 20006-6807,
` (202) 508-4759,
` jordan.rossen@ropesgray.com,
` Appearing for the Patent Owner.
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`4
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` INDEX TO EXHIBITS
`Exhibit Description Page
` SMITH EXH. 1 Declaration of Dr. Bruce W. 11
` Smith, Ph.D.
` SMITH EXH. 2 United States Patent No. 32
` 6,197,696 B1
` SMITH EXH. 3 Chapter 12 of textbook 49
` titled Microlithography:
` Science and Technology
` SMITH EXH. 4 Declaration of Dr. Bruce W. 71
` Smith, Ph.D.
` SMITH EXH. 5 Declaration of Dr. Bruce W. 72
` Smith, Ph.D.
` SMITH EXH. 6 Declaration of Dr. Bruce W. 77
` Smith, Ph.D.
` SMITH EXH. 7 United States Patent No. 79
` 6,140,226
` SMITH EXH. 8 United States Patent No. 99
` 5,592,024
` SMITH EXH. 9 Chapter 11 from textbook 109
` titled Microlithography:
` Science and Technology
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`5
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`*Original exhibits attached to original transcript.
` Copies of exhibits attached to all other
` transcripts.
`
` INDEX TO WITNESSES
`Witness Examination Page
`BRUCE SMITH BY MR. ROSSEN: 6
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`6
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`B R U C E S M I T H, 22 Mount Eagle Drive,
`Penfield, New York, after being duly called and
`sworn, testified as follows:
`
` EXAMINATION BY MR. ROSSEN:
`
` Q. Dr. Smith, have you been deposed
`before?
` A. Yes, I have.
` Q. How many times have you been deposed?
` A. Somewhere a little more than 20
`probably.
` Q. And have you been deposed in what I'm
`going to call PTAB proceedings, like IPRs, those
`types of proceedings?
` A. No, I have not. This is the first time
`in a PTAB proceeding.
` Q. Did you prepare for this deposition?
` A. Yes, I did.
` Q. For approximately how long did you
`prepare for this deposition?
` A. For the deposition -- deposition
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`7
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`itself?
` Q. Yes, the deposition today.
` A. I'd say probably 30, 40 hours maybe,
`close to 30.
` Q. Okay. And in forming your opinions for
`this -- for your declaration in this IPR, did you
`review any documents from the litigation in the
`Eastern District of Texas?
` A. I don't believe so. I don't think I've
`seen any of that.
` Q. And in preparing and forming your
`opinions, did you receive any documents from
`Broadcom?
` A. Not that I'm aware of, no.
` Q. Okay. And in forming your opinions,
`did you speak to counsel for Broadcom?
` A. No, I did not.
` Q. Are you familiar with the requirements
`for finding a claim obvious?
` A. Yes, I -- I think I am.
` Q. Okay. And for obviousness, are you
`aware of the requirement that you must identify the
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`8
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`differences between the prior art in the claims of
`the patent at issue?
` A. Sure, differences and similarities,
`sure.
` Q. Okay. And did you perform that
`analysis for this case?
` A. Yes, I did.
` Q. Okay. And so talking about the -- the
`main reference in this case, which we'll call it
`Grill --
` A. Okay.
` Q. -- are you familiar with that?
` A. Yes. I've read through Grill several
`times.
` Q. So what would you say are the
`differences between Grill and the '696 patent?
` MR. JIRON: Objection. Form.
` THE WITNESS: Yeah, I guess that's a good
`question. Both deal with multi-level
`metallization, and they do so in a way they use
`what we refer to as dual damascene. The Grill,
`patented Grill reference, is based on work and
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`9
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`inventions filed by a team of IBM workers, and
`during the time period in the 1990s, IBM had worked
`extensively on what we refer to as dual damascene,
`especially dual damascene or including dual
`damascene that uses things like multiple thin
`layer -- thin protection layers, often referred to
`as hard masks, and then corresponding dielectric
`layers for a wiring level in a contact or via
`level. Both the '696 patent and the Grill patent
`deal with that sort of technology.
` BY MR. ROSSEN:
` Q. Okay. And so it's your understanding
`that what you just explained there is -- it's a
`difference between the '696 patent and the Grill
`reference?
` MR. JIRON: Objection. Form.
` THE WITNESS: I think the aspects covered in
`the specification and claims of the '696 patent are
`covered by the dual damascene process that is
`described in the Grill reference, but that Grill
`reference in combination, for instance, with
`another reference that I referred to in my report
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`10
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`is the Aoyama reference that leads to support for
`some possible weaknesses in the Grill patent,
`especially related to the use of some of the layers
`to etch some of the underlying films.
` BY MR. ROSSEN:
` Q. Okay. Okay. So let's talk about the
`Aoyama reference for a second, the one you just
`mentioned.
` A. Right.
` Q. And the one you cited in your
`declaration. I believe in your declaration you
`talked about what the problem that Aoyama was
`attempting to solve?
` A. I did. I discussed a problem that is
`common with dual damascene processes for
`multiple-level metallization, and that is because
`multiple photoresist layers are used, the
`misalignment of one layer to the other can lead to
`problems.
` So both Aoyama and Grill deal with solutions
`or design alternatives to either solve for or
`alleviate some of the problems associated with what
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`11
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`we call misalignment.
` MR. ROSSEN: Okay. I'm going to go ahead
`and give you a copy of your declaration.
` THE WITNESS: Okay.
` MR. ROSSEN: Which we can mark as Deposition
`Exhibit 1.
` The following was marked for Identification:
` SMITH EXH. 1 Declaration of Dr. Bruce W.
` Smith, Ph.D.
` BY MR. ROSSEN:
` Q. Okay. And this is the -- just to
`clarify, this is your declaration from the
`IPR2016-01376 IPR.
` Do you recognize this document?
` A. Yes, I do. This is one of four
`declarations that I -- that I authored and worked
`on.
` Q. Okay. Can I point you to paragraph 155
`of your declaration, and particularly the last
`sentence of that.
` A. I see that.
` Q. Okay. So in this section you're
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`12
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`talking about the problems that Aoyama's attempting
`to solve; is that correct?
` A. Well, as I say, it explains a problem,
`but, sure, it is a problem that Aoyama is working
`to -- to -- working to solve.
` Q. Okay. And one of these problems that
`you mention here is integration density?
` A. Well, not exactly. What this means --
`so you're reading the last few words, problems for
`increasing integration density. The integration
`density isn't the problem, but, instead that's the
`direction that semiconductor technology goes as we
`move along to advance device performance, and a
`fundamental direction of integrated circuit
`technology is to make things smaller and packed
`closer together to make things more dense.
` So what this -- this sentence means is, as
`device generations continue and geometry is made
`smaller and features are packed closer together,
`and in particular this is -- this deals with wiring
`and contact level, as these features are made
`smaller and closer together, there is -- there are
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`13
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`increasingly difficult -- more difficult problems
`with things like contact resistance, degradation,
`and liability.
` So it is increasingly more important for
`advanced generations that misalignment is minimized
`or avoided.
` Q. Okay. So just so that I'm clear on
`this, the problem is not integration density. The
`problem is how to increase integration density?
` A. Right. The target is to increase
`density. That's the goal. As density's increased,
`problems associated with contact misalignment or
`misalignment between two layers becomes
`increasingly important.
` Q. Okay. And integration density, I
`believe you sort of talked about this, but that's
`the -- the number of wires per area?
` A. In a simple sense, that's right. It's
`the density of the circuit pattern features in a
`particular electronic device, and particular to
`what Aoyama and Grill and the '696 deal with, this
`is for wiring levels, inter -- multiple-level
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`14
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`wiring levels and the interconnection of those
`wiring levels with contacts, or sometimes these are
`referred also to -- also as vias.
` Q. Okay. So are you familiar with the
`term dimension control?
` A. Sure. And I think probably what you're
`referring to is critical dimension control. We
`abbreviate that as CD, and critical dimension
`control is the ability to maintain a given, let's
`say, line width or space width to a -- to a
`specified dimension.
` Q. Okay. And does -- does critical
`dimension control, as you're calling it, allow for
`an increased integration density?
` A. Without well-controlled -- without good
`control over things like critical dimension,
`integration -- increasing integration density
`becomes difficult. Without tight control over
`critical dimension sizes, let's say, it's difficult
`to increase integration density.
` Q. Okay. Can I direct you to paragraph 47
`of your declaration now.
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`15
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` A. Sure. I see that.
` Q. So can you read the last sentence here.
` A. Sure. It says -- this is referring to
`the Huang, Zhao, and Yu reference, and that
`paragraph begins talking about dual damascene,
`selective anisotropic dry etching, and it says:
`This preserves the critical dimensions,
`parentheses, i.e., the sizing, closed parentheses,
`of the vias and trenches and ensures that the
`correct layers are etched during each step of the
`process.
` Q. Okay. So this critical dimensions here
`that you're referring to here is what we were just
`talking about with the critical dimension control?
` A. Yes. This is the sizing of -- the word
`critical means -- generally means, and it's a term
`that has been used in semiconductor processing for
`generations, critical means a feature that is of
`interest. It means a small or maybe the smallest
`feature. It means not the biggest features in that
`device. It's the ones that are going to be most
`critical, the ones that you have to control.
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`16
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` So critical dimension, or what we often call
`CD, is the size of that feature of interest or that
`critical feature. So this paragraph says the use
`of a particular type of dry etching, one that leads
`to anisotropy, a directional etch, is necessary to
`preserve the kind of critical dimension control,
`the CD control, that's needed for vias and trenches
`for corresponding layers.
` Q. Okay. So here what we're talking about
`is the critical dimension is the size of the vias
`and the trenches?
` A. In a general sense, that's -- that's
`right, the size, the control of size of vias,
`trenches. Again, via is often referred to as
`contacts or contact holes.
` Q. Okay. And why is the sizing of the via
`important?
` A. Well, the via often refers to the hole
`which is filled with metal which then becomes the
`connection, which becomes the contact. If that
`hole or that via, sometimes also called a contact
`hole, can't be sized correctly, if it isn't, for
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`17
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`instance, etched to the right critical dimension --
`and these are dimensions that are -- need to be
`tightly controlled. There are specifications in
`how tight these dimensions have to be controlled
`for any process. If they're not controlled with
`some -- within some tight critical dimension, then
`that influences things like contact resistance. It
`influences the resistance or conductivity of that
`feature, for instance, that via feature as it
`connects to metal layers and things like that.
`Basically, bottom line, the device that this would
`be applied to won't work.
` Q. Okay. Can I now have you turn to
`paragraph 158 of your declarations.
` A. Okay. I see that.
` Q. Okay. And in particular the last
`sentence of that paragraph, can you -- can you read
`that sentence for me.
` A. Sure. Let me review the paragraph
`first.
` Q. Sure.
` A. So this paragraph addresses what's
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`18
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`referred to -- what's often referred to and can be
`a common problem with semiconductor processing,
`especially processing for multiple-level metal.
` So lithographic rework generally means after
`patterning of one photoresist level, that
`photoresist material may have to be removed, and
`that process has to be done again. That is why we
`call it rework.
` Rework in a dual damascene process like that
`described in the Grill patent, or that like
`described in the Grill patent in the discussion of
`prior art, can be difficult if that lithographic
`rework at stripping of the photoresist damages
`underlying materials like, for instance, organic
`dielectric materials that are made of similar --
`similar composition.
` So the Grill patent, the IBM dual damascene
`process utilizes something that IBM calls dual hard
`mask, and those two hard masks are underneath --
`are coated on the top of a multilayer stack and
`below the photoresist materials to be able to
`transfer those photoresist patterns into the hard
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`19
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`mask layers and allow protection of some of the
`underlying films like, for instance -- for
`instance, organic dielectrics.
` So you asked me to read -- oh, and then the
`sentence after that, so I'm reading the
`second-to-last sentence, I say: This ensures
`alignment of both via and wiring levels is
`completed and transferred into the thin films.
` So this allows, if rework needs to be done
`to ensure this such alignment, it can be done
`without damaging underlying films. And then that
`last sentence you asked me to read, did you want me
`to read it out loud?
` Q. Sure.
` A. It says: Figure 2B and 2C of Grill
`below show how stripping misaligned photoresist 28
`can damage interlayer dielectric 12 and make it
`difficult to control the via dimension.
` Q. And here when we say via dimension, are
`we talking about the via size as we were talking
`about before? Are those synonyms?
` A. Yeah. Via here is used as a noun, so
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`20
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`it's the size or the critical dimension of the via.
`And the via is the eventual hole that's made
`through the entire stack. So if -- if damage is
`made, for instance, to layer 12 of figure 2C, it
`becomes difficult to control the dimension of that
`via as it's transferred through the remainder of
`the stack.
` Q. Okay. And why is controlling the --
`the via dimension important in Grill?
` A. Well, for the same reason I stated. If
`that via dimension, once it's filled with metal and
`becomes the connection between metal layers, if
`that's not controlled correctly, it can lead to
`problems like resistance or conductivity and
`eventually lead to a failed device, a nonworking
`device.
` Q. Okay. And is there a problem if the
`via dimension is too small?
` A. There can be a problem if the via
`dimension is too small or too large.
` Q. Or too large? Okay. And so what
`factors would constrain the target, the via
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`dimension?
` A. I'm not sure I follow.
` Q. So if you have to -- I believe you just
`said that it's important to control the via
`dimension and that there would be problems if it
`was too big or too small, but I guess I'm asking:
`What factors would lead to knowing the correct
`size, the correct via dimension?
` A. So that's a difficult question to
`answer in a general sense, but I think generally
`the best answer I can give you is as any
`semiconductor device is designed from the -- from
`the beginning, from the designing standpoint, that
`design is based on -- that design for that
`particular generation is based on all the learning
`of all the generations that came ahead of it. So
`generally any device generation is a modification
`or an improvement over another.
` So from the design standpoint and the
`requirements of the electrical characteristics and
`the design of that -- of each and every process
`step, engineers would design into that -- these
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`processes or this process what would -- what the
`required contact hole size needs to be and the
`tolerance it would need to have in order to allow
`for that -- a particular device and device
`generation to work.
` Not only does it come down to the electrical
`characteristics which occur from the design
`standpoint, but the process conditions, it would
`allow, for instance, that contact hole to be
`patterned all the way through an entire stack.
` One problem with contact holes or vias
`during patterning and etch is we need to realize
`that it's not just one hole like figures 2B and 2C,
`a Grill or some of the other figures in the
`patents. It's not just a single hole, but it's an
`array of many, many holes, thousands, millions, and
`each of these has to perform identically over a
`large area.
` So all these things take into account to
`insure that that contact hole has the right -- to
`insure that contact hole in the ultimate connection
`has the right electrical performance, but also has
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`23
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`the ability to be able to be processed through the
`entire device process. Those kind of things
`determine the tolerance on what that hole has to
`be.
` Once that's set, once that's known, once
`that's determined and described very completely in
`any process control what the dimensional control
`has to be, if it deviates from what those
`allowances are, the device won't work. We -- we
`call that yield issues, and if the device doesn't
`work, then the entire -- the entire wave would be
`scrapped or need to be scrapped.
` Q. Okay. And is there any -- is there any
`particular relationship between the via dimension
`and the dimension of the wire above the via?
` A. Sure, there would be, but it's nothing
`that -- it's not an answer I could give you in a
`general sense, but there certainly would be a tied
`tolerance on what that via dimension would need to
`be for a particular generation as it makes contact
`with the metal layer above and the metal layer
`below. It's -- that would be -- that would be very
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`24
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`well established for any particular device.
` Q. Okay. But you're saying you wouldn't
`know necessarily whether the via dimension would be
`larger than the dimension of the wire above it or
`the wire below it?
` A. You mean sitting here I wouldn't know?
`I think I would know if I looked at a -- if you put
`a particular process in front of me, I could tell
`you, but there is not a general rule that has to be
`any -- any degree smaller or the same size.
` Q. Okay. Okay. So talking about the
`processes here, like the process in Grill, there --
`would there be advantages to any particular
`relationship between the via dimension and the --
`the wire dimension?
` A. What Grill does -- what the Grill
`process and process flow does is it leads to a -- a
`patterning and a pattern transfer approach that
`would allow for the control of that via or that
`contact hole to meet the required specifications.
` I can't answer any questions related to, you
`know, how much variation there would be and how
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`25
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`much matters and that kind of thing unless we
`looked at a real process. I think if we looked at
`a real process, if we looked at a real IBM dual
`damascene process, we could answer those questions.
`The key of what Grill does, though, is it allows
`those tolerances to be met to size that contact
`hole as it needs to be.
` Q. Okay. And is there any benefit to
`having the -- in these processes to having the via
`hole be smaller than the wire dimension?
` A. Again, it depends on the process. It
`depends on -- there -- there are generalities. If
`that hole is made too small, it will close up and
`may not fill. If that hole is -- again, in a
`general sense, if features are made too large,
`without -- without necessarily regard to via, if a
`feature is made too large, you run into issues as
`your density increases of decreasing the width of
`the dielectric insulating layer between those
`features.
` So it's not just what happens when that via
`or that contact hole is made smaller. It's what
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`26
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`happens to the neighboring features and what
`happens to the dielectric in between them.
` So it's -- there are reasons why that
`hole -- that via or any feature shouldn't be any
`bigger than specified or any smaller than
`specified, and in a general sense one wouldn't say
`that it's advantageous to make something smaller or
`bigger. The best thing to do is -- the way to make
`a manufacturerable process is to make that hole or
`that feature or that via its correct size within
`a -- within a tolerable -- specified tolerable
`limit.
` We often call that specified tolerable limit
`a spec, S-P-E-C, and the spec on that contact hole
`or via or whatever feature we're talking about
`is -- is normally well defined.
` Q. Okay. I guess what I'm -- what I'm
`trying to ask is not so much in a vacuum, the via
`size in a vacuum, but more the via size relative to
`the metal wire below it. Are there instances in
`which you'd want the via hole to be bigger than the
`wire below it?
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`27
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` A. I think I'd have to give you the same
`answer. You would want that via to be the size
`that it should be based on the particular device
`design. If that device is designed for that
`contact hole to be the same dimension as the via,
`that would be the target dimension.
` If that contact hole was designed to be
`smaller than -- I'm sorry, I'm not sure if I said
`that right. If that contact hole was designed to
`be the same size as the underlaying -- underlying
`wiring feature, then the target -- it would be --
`that would be the size that would be targeted. If,
`instead, that contact hole was sized to be smaller
`than the underlying wire, that would be its target.
` One can't say that if you're targeting that
`contact hole or via to be smaller than the
`underlying wiring it's a good idea to make it
`bigger or there are advantages to make it bigger.
`That's -- the goal is to make it the size that it
`should be based on that -- based on the device
`design.
` Q. Okay. And how would this concern --
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`how would these issues about the sizing of the via
`dimension affect the integration density that we
`talked about before?
` A. Okay. So the integration density is --
`is the goal, to increase the integration density,
`and to increase integration density, everything is
`made smaller. Things are packed closer together.
` So for a particular device of a given
`density, the wiring, the wiring level for that
`device as well as the via structures for that
`device are designed to a particular dimension. As
`I said -- as I said before, that particular
`dimension is what is -- what is targeted during
`processing and the goal to meet that specified
`critical dimension.
` Q. Okay. Let me -- let me go ahead and
`give you a copy of Grill.
` A. Before we move on to Grill, you gave me
`one of my declarations, the declaration ending in
`01376. I'm not sure if we're going to look at
`other ones, but I have a correction to make in this
`declaration which carries over to all the rest of
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`them, if I could.
` I've noticed one or two typos along the way,
`which I don't think that impacts the substance of
`the declaration, but there are two that I'd like to
`make that do impact the substance.
` Q. Okay.
` A. Actually, I've got three. Appendix A
`is my CV, but this is a bit dated now, and I've
`provided to the lawyers for TSMC an updated CV
`which includes at least one other case that I
`worked on and some updates to my references. So I
`think that can be provided.
` Another correction is also in an appendix,
`Appendix B-9 -- or, I'm sorry, Appendix B at page
`B-9 and 10. And Appendix B addresses the Grill
`patent and the '628 application, which is the
`disclosure of the provisional application, and on
`B-9, the second full paragraph, I say: Although
`the nonprovisional application for the '696 patent.
`That should read the Grill patent. That's what
`this appendix is about, and that correction should
`carry through. So I'm going to cross that out on
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`my copy, if that's okay. I'm just going to write
`Grill here.
` It only makes sense if that's Grill. This
`isn't the '696 patent.
` Q. Okay.
` A. And the other correction in B-10, I
`talk about in the second full paragraph the
`photoresist layer 62 and the layer 12, and at the
`end of -- at the bottom of the first paragraph in
`that column, I say: A person of ordinary skill in
`the art would have understood that etching layer 12
`under such circumstances concurrently etches layer
`58 because the two layers have similar etch
`properties, but layer 12 and 58 don't have similar
`etch properties. The layer that I'm talking to --
`talking about here is not 58. It's 62. So that
`correction should be, instead of layer 58, it
`should be layer 62.
` Q. Okay. I believe that this has actually
`been an issue in this IPR before, about trying to
`correct this -- this particular --
` MR. ROSSEN: We've been going for about 45
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`minutes. Do you want to take a quick -- a quick
`break?
` THE WITNESS: It's your call. I'm okay.
` MR. ROSSEN: Okay. Let's take like a
`five-minute break.
` MR. JIRON: Okay.
` (A rec
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