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`United States Patent
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`Cochran et a1.
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`[19]
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`4,832,789
`[11] Patent Number:
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`[45] Date of Patent: May 23, 1989
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`Assignee:
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`[54]
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`[75]
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`[73]
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`[5 1]
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`[58]
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`[56]
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`SEMICONDUCTOR DEVICES HAVING
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`MULTI-LEVEL METAL INTERCONNECTS
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`Inventors: William T. Cochran, New Tripoli;
`Agustin M. Garcia; Graham W. Hills,
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`both of Allentown; Jenn L. Yeh,
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`Macungie, all of Pa.
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`American Telephone and Telegraph
`Company, AT&T Bell Laboratories,
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`Murray Hill, NJ.
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`App1.No.: 179,176
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`Apr. 8, 1988
`Filed:
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`Int. Cl.4 ........................ .. B44C 1/22; C23F 1/02;
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`C03C 15/00; C03C 25/06
`US. Cl. .................................. .. 156/644; 156/653;
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`156/656; 156/657; 156/659.1; 357/71; 437/203;
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`437/228
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`Field of Search ............. .. 156/644, 653, 656, 657,
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`156/659.l, 662; 357/65, 71; 437/180, 187, 189,
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`192, 194, 203, 204, 228, 245, 238, 241
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`References Cited
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`U.S. PATENT DOCUMENTS
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`l/ 1983 O’Toole et al.
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`4,370,405
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`................... .. 430/312
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`4,605,470
`........... .. 156/659.1 X
`8/1986 Gwozdz et a1.
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`............ .. 156/659.1 X
`4,631,806 12/1986 Poppert et a1.
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`OTHER PUBLICATIONS
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`A Planar Multi-Level Tungsten Interconnect Technol-
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`ogy, D. C. Thomas and S. S. Wong, IEDM Technical
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`Digest, pp. 811—813, Los Angeles, CA 1986.
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`Prairie—A New Planarization Technique and its Appli-
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`cations in VLSI Multilevel Interconnection, Andy L.
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`Wu, Electrochemical Sooiety Proceedings, 87-4, pp.
`239—249, 1987.
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`Primary Examiner—William A. Powell
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`Attorney, Agent, or Firm—John T. Rehberg
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`[57]
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`ABSTRACT
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`A self-assigned, self-planarized metallization scheme for
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`multilevel interconnections using self-aligned windows
`in integrated circuits is described. Trenches are etched
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`into a dielectric and then, using an etch stop layer on
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`top of the dielectric to prevent unwanted etching of the
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`dielectric, self-aligned windows which expose portions
`of the substrate are etched in the dielectric. Self-aligned
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`windows can also be formed without a mask.
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`6 Claims, 2 Drawing Sheets
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`Page 1 of 5
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`TSMC Exhibit 1040
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`TSMC v. IP Bridge
`IPR2016-01377
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`Page 1 of 5
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`TSMC Exhibit 1040
`TSMC v. IP Bridge
`IPR2016-01377
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`

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`US. Patent
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`May 23, 1989
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`Sheet 1 of 2
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`4,832,789
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`I
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`-—DA
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`Sr
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`FIG. 1
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`1733E2fi21
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`US. Patent May 23,1989
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`Sheet 2 of 2
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`4,832,789
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`///a//_///A
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`1
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`SEMICONDUCI‘OR DEVICES HAVING
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`MULTI-LEVEL METAL INTERCONNECTS
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`4,832,789
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`2
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`cessed metal in the dielectric. The second sequence is
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`conceptually somewhat similar although the unwanted
`metal is removed by a lift-off step.
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`Neither approach teaches how to make windows that
`are self-aligned.
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`SUMMARY OF THE INVENTION
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`We have found that metallizations including self-
`aligned contacts may be obtained by a method that we
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`term “the reverse pillar process.” The method deposits
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`at least first and second dielectric layers and first and
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`second etch stop layers between the first and second
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`dielectric layers and on top of said second dielectric
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`layer, respectively, patterns portions of said first dielec-
`tric layer and said etch stop layers to form trenches for
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`metal runners. Portions of said trenches are now pat-
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`terned, using the second etch layer to prevent unwanted
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`etching of the dielectric, to form self-aligned windows
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`in said first dielectric layer which expose selected por-
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`tions of the underlying substrate. The first etch stop
`layer is typically a dielectric. The openings are now
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`filled with metal.
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`Alternatives are contemplated. One dielectric layer,
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`rather than two and an intermediate etch stop layer,
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`may be used if the depth of the etch used for the first
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`patterning step can be precisely controlled. In the pre-
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`ferred embodiment, however, a plurality of layers is
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`used, typically 4, with the first etch stop layer being
`used to more precisely control the etch depths for win-
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`dows and trenches. The method of the invention avoids
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`patterning of a metal layer as the metal is deposited in
`trenches and windows. Also, the windows and metal
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`trenches are filled simultaneously will metal thereby
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`avoiding any interfaces.
`In another embodiment, a maskless contact is ob-
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`tained by depositing a metal after the first patterning
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`step and etching back to leave metal sidewalls in the
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`nailhead sections of trenches with the normal width
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`portion of the trenches being sealed. The windows are
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`then etched using the sidewalls as a mask, i.e., the metal
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`acts as a mask as the bottom dielectric layer is selec-
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`tively removed for the contact. Of course, the top di-
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`electric is not etched because of the etch stop layer.
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`It will also be appreciated by those skilled in the art
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`that the metal filling process is a self-planarizing pro-
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`cess.
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`BRIEF DESCRIPTION OF THE DRAWING
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`FIG. 1 is a top view of the layout and lithography for
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`metallizations according to this invention;
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`FIGS. 2—5 are sectional views along line A—A’ of
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`FIG. 1 with
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`FIG. 2 showing the initial structure;
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`FIG. 3 showing the structure after etching for the
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`metal pattern;
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`FIG. 4 showing the structure after etching the win-
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`dow pattern;
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`FIG. 5 showing the final structure; and
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`FIG. 6 depicts yet another embodiment which is a
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`maskless contact.
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`DETAILED DESCRIPTION
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`FIG. 1 is a top view showing the layout and lithogra-
`phy for the metallizations according to this invention.
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`The structure depicted comprises a plurality of metal
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`runners indicated as 1 and a plurality of windows indi-
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`cated as 3, opening to the underlying substrate. It will
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`TECHNICAL FIELD
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`This invention relates to semiconductor integrated
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`circuits and to the metallization used in such circuits.
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`BACKGROUND OF THE INVENTION
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`As the complexity of integrated circuits increases,
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`numerous approaches have been taken to solve the
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`problem of expediently making electrical connections
`to and between individual devices. This is an important
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`problem in integrated circuit fabrication because not
`only do electrical contacts and interconnections require
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`space on the integrated circuit chip, but the complexity
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`of the interconnections frequently requires the metalli-
`zations to be on more than one level. The former con-
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`sideration requires minimization of the size of the metal-
`lization, and the latter consideration introduces process-
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`ing complexity.
`In a typical multilevel fabrication sequence, windows
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`or vias are first opened in a dielectric layer to expose
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`selected portions of the underlying substrate and then
`filled with a metal. Substrate is used to mean underlying
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`material and thus may include the Si wafer, source and
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`drain regions, prior interconnections, etc. Metal runners
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`electrically connecting the filled windows are then
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`formed on the dielectric. This is typically done by blan-
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`ket depositing a metal and then patterning it. Of course,
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`care must be taken to insure that the runners are prop-
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`erly aligned so that they contact the windows.
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`Although the processing sequence described is con-
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`ceptually simple, at least three problems are likely to
`arise. (1) Metals are highly reflective and the optical
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`printing and etching of features in metals is difficult and
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`becomes even more so at submicron dimensions. (2)
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`After the metal runners have been formed, a dielectric is
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`deposited betwen the runners. This dielectric should be
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`free of voids, but depositing such a layer becomes more
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`difficult as runners are more closely spaced and the
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`space available for the dielectric decreases. (3) Accu-
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`rate pattern transfer from the mast is most easily ob-
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`tained with a planar surface. As the topography be-
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`45
`comes more complex, dielectric smoothing by means of
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`flow or planarization may be required. However, re-
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`flow is not always an acceptable procedure since the
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`temperature required for reflow may impair the integ—
`rity of lower metal levels. Planarization schemes make
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`the processing more complex.
`Some of these problems can be avoided by a tech-
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`nique such as that discussed by Thomas et al. in IEDM
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`Technical Digest, pp, 811—813, Los Angeles, Calif,
`1986. A composite dielectric layer, Si3N4 over $02, is
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`55
`patterned to form trenches into which metal is selec-
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`tively deposited with the nucleation being initiated by a
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`silicon implant. Thus, the problems of filling the spaces
`between the runners and of obtaining a planar dielectric
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`surface over complex topography are avoided.
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`Another approach, which also deposits a metal in a
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`trench in a dielectric is described by Wu in Electro-
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`chemical Society Proceedings, 87—4, pp. 239—429, 1987.
`Exemplary sequences are shown in Wu’s FIGS. 1 and 3.
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`The first sequence forms the trenches, blanket deposits
`a metal, deposits and etches a photoresist thus leaving
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`portions of the original trenches full of resist, etches
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`back the metal to expose the dielectric surface using the
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`resist as an etch mark, and strips the resist leaving re-
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`25
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`be readily appreciated that in a typical integrated circuit
`many more runners and contacts than those depicted
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`will be present.
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`FIG. 2 depicts a cross section of the structure of FIG.
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`1 along line A—A’. Depicted are substrate 21, three
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`dielectric layers 23, 25, 27, etch stop layer 29 and photo-
`resist layer 31. Also shown is a conductive runner 33.
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`The dielectrics have a total
`thickness d,. Dielectric
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`layer 23 has a thickness c, and layers 25 and 27 have a
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`combined thickness mt. Layer 25 is thin compared to
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`layers 23 and 27. The term “substrate” is used to mean
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`the materials underlying the dielectric layers. Choice of
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`dielectric and etch stop materials will be apparent to
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`those skilled in the art after reading the following de-
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`scription of the etching steps. Methods for depositing
`the dielectric and etch stop materials will be readily
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`apparent to those skilled in the art.
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`The photoresist 31 and etch stop layer 29 and the two
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`top dielectric layers 25 and 27 are now patterned for the
`metal runners. This is done by patterning the photore-
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`sist with the desired metal pattern. It should be noted
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`that the mask used is a mask of the reverse tone pattern.
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`Well known techniques are used to etch the etch stop
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`layer and both of the two top dielectric layers. The
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`third, i.e., bottom, dielectric layer acts as an etch stop
`for the etch of the second, i.e., middle, dielectric layer.
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`The resulting structure is depicted in FIG. 3.
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`The photoresist for the reverse metal patterning is
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`now stripped and a new layer of photoresist 35 is depos-
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`ited and patterned with the window pattern. Standard
`lithographic techniques are now used to define the win-
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`dow pattern. It is noted that the windows, as defined in
`the resist, are oversized along the critical dimensions,
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`and the etch stop layer 29 will provide self alignment
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`during the subsequent window etch, i.e., layer 29 pre-
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`vents etching of the underlying dielectric material
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`thereby forming self-aligned windows. The dielectric
`23 is etched to expose selected portions of the underly~
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`ing substrate. Only portions that were exposed during
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`contacts. The resulting structure is depicted in FIG. 4.
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`It is apparent that the etch stop layer, i.e[layer 29, stops
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`the etching of the oversized portions of the window
`pattern as it is not etched by the process of etching the
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`dielectric. However, as the reverse metal patterning
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`exposed portions of dielectric layer 23,
`this layer is
`etched and portions of the substrate exposed.
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`The contact photoresist is now removed, and conven-
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`tional techniques used to fill the recessed areas with
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`metal 37. The resulting structure is depicted in FIG. 5.
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`Several techniques can be used for depositing the
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`metallizations. For example, sputtering can be used for
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`aluminum metallization. Tungsten or other refractory
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`metals may be deposited by either selective or blanket
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`chemical vapor deposition. Selective deposition will
`result in the metal being present in only the trenches and
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`windows after suitable activation of these areas. For the
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`non-selective depositions, a uniform etchback will be
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`required to remove material from the surface of the
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`dielectric. The etch stop layer can be removed prior to
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`or after the metal filling. If the etch stop is non-conduc-
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`tive, it does not have to be removed and can be used as
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`an etch stop for the next level of metallization.
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`It will be readily appreciated that the process de-
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`scribed may be repeated to obtain additional levels of
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`interconnection.
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`The first and third dielectrics have an etch selectivity
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`65
`against the second dielectric and may be the same mate-
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`rial. Both the etch stop layer 29 and the middle dielec-
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`tric layer 25 have a high etch selectivity against layers
`23 and 29, i.e., the first and second dielectrics. Layer 25
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`10
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`15
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`30
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`35
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`45
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`55
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`6O
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`4,832,789
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`4
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`may thus also be referred to as an etch stop layer. The
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`etch stop layers 25 and 29 are typically very thin with
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`respect to the first and third dielectric layers. In the
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`typical process described, the reverse metal pattern for
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`the trenches is formed by etching the top etch stop layer
`and the top two dielectrics, that is, dielectrics 25 and 27.
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`Typical dielectrics are oxides and nitrides. It will be
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`appreciated that etching conditions will have to be
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`changed for the two layers. Window patterning is per-
`formed, and dielectric 23 is etched to expose portions of
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`the substrate for the windows. The metal is now depos-
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`ited as previously described.
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`It will be appreciated by those skilled in the art that
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`the reverse metal patterning is performed first and the
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`window patterning performed second. This sequence is
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`opposite to the conventional alignment sequences and
`produces a window which is self-aligned to the metal.
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`Variations in the process described are contemplated.
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`For example, to avoid the necessity of using a plurality
`of dielectric layers, the depth of the etches into a single
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`dielectric layer may be carefully controlled.
`A maskless window may be formed by blanket depos-
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`iting a metal conformally after the first patterning step.
`The metal is then etched back so that only metal side-
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`walls 39 remain in the nailheads in the trenches where
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`there are wider openings while the narrower runners 40
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`are sealed, i.e., filled, with metal. This structure is de-
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`picted in FIG. 6. Numerals identical to those used in
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`describing previous figures represent identical elements.
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`Techniques for appropriate deposition and etchback
`will be readily apparent to those skilled in the art. The
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`sidewalls and the etch stop layer then act as a mask as
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`the windows are opened in the bottom dielectric layer.
`Metal is then deposited and, if necessary, etched back to
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`leave a planar surface. Although there is a reduction of
`one mask level per interconnection, self-aligned nail-
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`heads are required in this embodiment.
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`What is claimed is:
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`l. A method of fabricating a semiconductor inte-
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`grated circuit comprising the step of fabricating a metal-
`lization on said circuit, said fabricating step comprises:
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`depositing at least one dielectric layer and an etch
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`stop layer on a substrate, said etch stop layer being
`over said at least one dielectric layer;
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`patterning said etch stop and dielectric layer to form
`trenches for metal;
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`patterning portions of said trenches in said at least one
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`dielectric layer, said etch stop layer preventing
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`etching of the underlying portions of said at least
`one dielectric layer
`thereby forming windows
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`which expose portions of said substrate; and
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`depositing metal to fill said trenches and windows.
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`2. A method as recited in claim 1 in which said second
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`patterning step comprises patterning a resist on said
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`etch stop layer to form oversized windows and etching
`said at least one dielectric layer, said windows in said
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`layer being self-aligned.
`3. A method as recited in claim 1 in which said second
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`patterning step comprises depositing in metal in said
`trenches, etching back to form metal sidewalls in over-
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`sized trenches and etching said dielectric layer to form
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`self~aligned windows.
`4. A method as recited in claim 1 in which said at least
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`one dielectric layer comprises first, second and third
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`dielectric layers, said first and third layers having an
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`etch selectivity against said second layer.
`5. A method as recited in claim 4 in which said first
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`and third layers comprise oxides.
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`6. A method as recited in claim 5 in which said second
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`layer comprises a nitride.
`*
`*
`*
`*
`*
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`Page 5 0f 5
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`Page 5 of 5
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