`
`IP Bridge Exhibit 2020
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`TSMC v. IP Bridge
`IPR2016-01377
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`Page 0001
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`IP Bridge Exhibit 2020
`TSMC v. IP Bridge
`IPR2016-01377
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`

`FOR
`
`THE VLSI ERA
`
`VOLUME 1:
`
`SILICON PROCESSING
`
`PROCESS TECHNOLOGY
`
`IPR2016-01377 Page 0002
`
`

`

`SILICON PROCESSING
`
`FOR
`
`THE VLSI ERA
`
`VOLUME 1:
`
`PROCESS TECHNOLOGY
`
`STANLEY WOLF Ph.D.
`
`Sunset Beach, California
`
`Professor, Department of Electrical Engineering
`California State University, Long Beach—
`Long Beach, California
`and
`
`Instructor, Engineering Extension, University of California, Irvine
`
`RICHARD N. TAUBER PhD.
`
`Manager of VLSI Fabrication
`TRW - Microelectronics Center
`
`Redondo Beach, California
`and
`
`Insn'uctor;Engineering Extension, University of California, Irvine
`
`LATTICE
`PRESS
`
`IPR2016-01377 Page 0003
`
`

`

`ENGINEERING; “are.
`
`DIS CLAIMER
`
`This publication is based on sources and information believed to be reliable, but the authors and
`Lattice Press
`disclaim any warranty or liability based on or relating to the contents of this
`publication.
`
`Copyright © 1986 by Lattice Press
`All rights reserved. No part of this book may be reproduced or transmitted in any form or by any
`means, electronic or mechanical, including photocopying, recording or by any information storage
`and retrieval system without written permission from the publisher, except for the inclusion of
`brief quotations in a review.
`
`PRINTED IN TIHE UNITED STATES OF AMERICA
`
`Published by:
`
`Lattice Press
`Post Office Box 340
`
`Sunset Beach, California 90742, U.S.A.
`
`Cover design by Roy Montibon and Donald Strout, Visionary Art Resources, Inc., Santa Ana, CA.
`
`Library of Congress Cataloging in Publication Data
`Wolf, Stanley
`and Tauber, Richard N.
`
`Silicon Processing for the VLSI Era
`
`Volume 1
`
`: Process Technology
`
`Includes Index
`
`1. Integrated circuits-Very large scale
`integration.
`2. Silicon.
`I. Title
`
`86—081923
`
`ISBN 0-961672-3—7
`
`987654
`
`IPR2016-01377 Page 0004
`
`

`

`f-z'!
`
`"“T\
`
`To my wife, Carrol Ann,
`and my children, Jennifer Laura and Stanley Charles Ross
`
`Richard N. Tauber
`
`Stanley Wolf
`
`To my Wife, Barbara
`
`IPR2016-01377 Page 0005
`
`

`

`PREFACE
`
`Vll
`
`SILICON PROCESSING FOR THE VLSI ERA is a text designed to provide a
`comprehensive and up-to-date treatment of this important and rapidly changing field. The text
`will consist of two volumes of which this book is the first, subtitled, Process Technology.
`Volume 2, subtitled, Manufacturing Technology is scheduled for publication in 1988.
`In this
`first volume, the individual processes utilized in the fabrication of silicon VLSI circuits are
`covered in depth (e.g. epitaxial growth, chemical vapor and physical vapor deposition of
`amorphous and polycrystalline films, thermal oxidation of silicon, diffusion, ion implantation,
`microlithography, and etching processes).
`In addition, chapters are also provided on technical
`subjects that are common to many of the individual processes, such as vacuum technology,
`properties of thin films, material characterization for VLSI, and the structured design of
`experiments ’for process optimization. The topics covered in the book are listed in more detail in
`the Table of Contents.
`In Volume 2, Manufacturing Technology, other issues related to VLSI
`fabrication such as process integration, process simulation, manufacturing yield, VLSI
`manufacturing facilities, assembly, packaging, and testing will be covered.
`The purpose of writing this text was to provide professionals involved in the
`microelectronics industry with a single source that offers a complete overview of the technology
`associated with the manufacture of silicon integrated circuits. Other texts on the subject are
`available only in the form of specialized books (i.e. that treat just a small subset of all of the
`processes), or in the form of edited volumes (i.e. books in which a group of authors each
`contributes a small portion of the contents). Such edited volumes typically suffer from a lack of
`unity in the presented material from chapter-to-chapter, as well as an unevenness in writing style
`and level of presentation.
`In addition, in multi-disciplinary fields, such as microelectronic
`fabrication, it is difficult for most readers to follow technical arguments in such books, especially
`if the information is presented without defining each technical "buzzword" as it is first introduced.
`In our book we hope to overcome such drawbacks by treating the subject of VLSI fabrication
`from a unified and more pedagogical viewpoint, and by being careful to define technical terms
`when they are first used. The result is intended to be a userfriendly book for workers who have
`come to the semiconductor industry after having been trained in but one of the many traditional
`technical disciplines.
`,
`An important technical breakthrough has occurred in publishing, that the authors also felt
`could be exploited in creating a unique book on silicon processing. That is, revolutionary
`electronic publishing techniques have recently become available, which can cut the time required
`to produce a published book from a finished manuscript. This task traditionally took 15—18
`months, but can be now reduced to less than 4 months.
`If traditional techniques are used to
`produce books in such fast-breaking fields as VLSI fabrication, these books automatically
`possess a built-in obsolescence, even upon being first published.
`The authors took advantage
`of the rapid production techniques, and were able to successfully meet the reduced production-
`time schedule. As a result, they were able to include information contained in technical journals
`
`IPR2016-01377 Page 0006
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`

`

`viii
`
`PREFACE
`
`and conferences which was available within four months of the book's publication date. Earlier
`books written on silicon processing, unfortunately, suffer from having had to undergo an 15-18
`month production cycle. This is the first book on the subject in which such time—delay effects
`have been eliminatedfrom the production process!
`Written for the professional, the book belongs on the bookshelf of workers in several
`microelectronic disciplines. Microelectronicfabrication engineers who seek to develop a more
`complete perspective of the subject, or who are new to the field, will find it inValuable.
`Integrated circuit designers, test engineers, and integrated circuit equipment designers, who must
`understand VLSI processing issues to effectively interface with the fabrication environment, will
`also find it a uniquely useful reference. The book should also be very suitable as a text for
`graduate—level courses on silicon processing techniques, offered to students of electrical engin-
`eering, applied physics, and materials science.
`It is assumed that such students already possess a
`basic familiarity with semiconductor device physics. Problems are included at the end of each
`chapter to assist readers in gauging how well they have assimilated the material in the text.
`The book is an outgrowth of an intensive seminar conducted by the authors through the
`Engineering Extension of the University of California, Irvine.
`In the first three years that it
`was offered, over three hundred engineers and managers from more than 75 companies and
`government agencies, enrolled in the course.
`Its fine reputation is attested to by the fact that
`many firms have sent participants each time the course has been offered, presumably based on the
`recommendations of earlier enrollees.
`
`considered as being the technical underpining of Chapters 1, 2, 8, and 9. Extra thanks are also
`
`the authors each
`In setting out to create a comprehensive text on VLSI fabrication,
`Professor Wolf's
`contributed a set of unique and complementary skills to the project.
`proficiency as a teacher and writer were utilized to produce a clearly written and logically
`organized book. Some of this expertise was gained in authoring an earlier best-selling text
`Electronic Measurements and Laboratory Practice, Prentice—Hall, 1983. Dr. Tauber brought a
`technical expertise vauired from his long involvement in the semiconductor industry. He used
`this background to insure that the most important topics of VLSI fabrication were addressed, and
`that the information was up-to—date and presented in a technically correct fashion. Note that for
`over twenty years, Dr. Tauber has held positions at Bell Telephone Laboratories, Xerox, And
`Hughes Aircraft Company. Currently he directs advanced VLSI Fabrication efforts at the
`Microelectronics Center of TRW. The labor of the writing effort was divided between the
`authors in the following manner: Professor Wolf was responsible for writing Chapters 1, 2, 3,
`9, 10, 12, 13, 15, 16, 17, and 18, and Dr. Tauber undertoOk the writing of Chapters 4, 5, 7, 8,
`11, and 14. Material for Chap. 6 was jointly contributed by Andrew R. Coulson and Dr. Tauber.
`A book Of this length and diversity would not have been possible without the indirect and
`direct assistance of many other workers. To begin with, virtually all of the information presented
`in this text is based on the research efforts of a countless number of scientists and engineers.
`Their contributions are recognized to a small degree by citing some of their articles in the
`references given at the end of each chapter. The direct help came in a variety of forms, and was
`generously provided by many people. The text is a much better work as a result of this aid, and
`the authors express heartfelt thanks to those who gave of their time, energy, and intellect.
`Each of the chapters was reviewed after the writing was cempleted. The engineers and
`scientists who participated in this review were numerous. Special thanks are given to Leonard
`Braun and Ethelyn Motley, who provided extensive and incisive editing services. We also thank
`Warren Flack, Stephen Franz, Kenneth Tokunaga, Dean Denison, Simon Prussin, and Vitus
`Matare for their critical reviews. Simon Prussin also provided clarification of many concepts
`during the course of numerous technical discussions with the authors, and can be rightly
`
`IPR2016-01377 Page 0007
`
`

`

`ix
`
`Stanley Wolf and Richard N. Tauber
`
`P.S. Additional copies of the book can be obtained from:
`
`extended to Mark Miscione for bringing valuable technical input on the subject of the physics of
`microlithography, to Susan Curry for donating SEM photographs, and to Andrew Coulson for
`creating some of the drawings. Ada Mae Hardeman, of the Engineering Extension of the
`University of California, Irvine is OWed special thanks for helping to make a success of the
`seminar from which this book grew. Otto Gruneberg, of QBI, Inc. was also a benefactor of the
`project. He graciously agreed to share his exhibition space with Lattice Press at Semicon—West,
`1986, where the book made its debut.
`Superlative computer support and access to computer resources was generously made
`available by Donald E. Carlile, Harry T. Hayes, and Dale Lambertson of the Personal Computer
`Support Section of the Electronic Systems Group of TRW. Henry Nicholas was a computer
`expert and friend who lit the fire of inspiration that led to the undertaking of the project. The
`management of the Electronics Systems Group and the Microelectronics Center of TRW,
`including most notably Dr. Barry Dunbridge and Phillip Reid, are warmly thanked for providing a
`supportive environment, conducive to producing such an intensive technical project. They made
`available technical literature and other resources to the authors, especially S. Wolf, who was able
`to avail himself of this generosity while writing during a Sabbatical leave from his teaching
`duties at California State'\University, Long Beach. Roy Montibon and Donald Strout of
`Visionary Art Resources, Inc., Santa Ana, CA designed the cover. Finally, we wish to thank
`Shirley Rome, Carrol Ann Wolf, and Barbara Tauber for typing the manuscript.
`
`An order form, for your convenience, is provided on the final leaf of the book.
`
`Lattice Press,
`PO. Box 340-V
`
`Sunset Beach, CA, 90742
`
`IPR2016-01377 Page 0008
`
`

`

`PREFACE
`
`PROLOGUE
`
`CONTENTS
`
`xxi
`
`1. SILICON: SINGLE-CRYSTAL GROWTH AND WAFERING 1
`
`- TERMINOLOGY OF CRYSTAL STRUCTURE, 1
`- MANUFACTURE OF SINGLE-CRYSTAL SILICON, 5
`From Raw Material to Electronic Grade Polysilicon
`- CZOCHRALSKI (CZ) CRYSTAL GROWTH, s
`Czochralski Crystal Growth Sequence
`Incorporation of Impurities into the Crystal (Normal Freezing)
`Modifications Encountered to Normal Freezing in CZ Growth
`Czochralski Silicon Growing Equipment
`Analysis of Czochralski Silicon in Ingot Form
`Measuring Oxygen and Carbon in Silicon Using Infrared Absorbance Spectroscopy
`- FLOAT-ZONE SINGLE-CRYSTAL SILICON, 21
`- FROM INGOT TO FINISHED WAFER: SLICING; ETCHING; POLISHING, 23
`- SPECIFICATIONS OF SILICON WAFERS FOR VLSI, 26
`- TRENDS IN SILICON CRYSTAL GROWTH AND VLSI WAFERS, 30
`
`Wafer Resistance to Warpage
`
`2. CRYSTALLINE DEFECTS, THERMAL PROCESSING,
`AND GETTERING
`
`- CRYSTALLINE DEFECTS IN SILICON, 37
`Point Defects
`One-Dimensional Defects (Dislocations)
`
`Area Defects (Stacking Faults)
`Bulk Defects and Precipitation
`— INFLUENCE OF DEFECTS ON DEVICE PROPERTIES, 51
`Leakage Currents in pn Junctions
`Collector-Emitter Leakage in Bipolar Transistors
`
`Minority Carrier Lifetimes
`Gate Oxide Quality
`Threshold Voltage Control
`
`IPR2016-01377 Page 0009
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`

`

`CONTENTS -
`
`CHARACTERIZATION OF CRYSTAL DEFECTS, 55
`THERMAL PROCESSING, 56
`Rapid Thermal Processing (RTP)
`OXYGEN IN SILICON, 59
`GETTERING, 61
`Basic Gettering Pinciples
`Extrinsic Gettering
`Intrinsic Gettering
`
`3. VACUUM TECHNOLOGY FOR VLSI APPLICATIONS
`
`FUNDAMENTAL CONCEPTS OF GASES AND VACUUMS, 73
`Pressure Units
`
`Pressure Ranges
`Mean Free Path and Gas Flow Regimes
`LANGUAGE OF GAS ISOLID INTERACTIONS, 77
`TERMINOLOGY OF VACUUM PRODUCTION AND PUMPS, 78
`ROUGHING PUIVIPS, 85
`Oil-Sealed Rotary Mechanical Pumps
`Pump Oils
`Roots Pumps
`HIGH VACUUM PUMPS I: DIFFUSION PUNIPS, 89
`HIGH VACUUM PUNIPS II: CRYOGENIC PUNIPS, 92
`HIGH VACUUM PUNIPS III: TURBOMOLECULAR PUNIPS, 95
`SPECIFICATION OF VACUUM PUNIPS FOR VLSI, 97
`TOTAL PRESSURE NIEASUREMENT, 97
`
`Electrical Transport in Thin Films
`
`NIEASUREMENTS OF PARTIAL PRESSURE: Residual Gas Analyzers, 101
`Operation of Residual Gas Analyzers (RGA)
`RGAs and Non-High Vacuum Applications: Diflerential Pumping
`Interpretation of RGA Spectra
`RGA Specification List
`- HIGH GAS FLOW VACUUM ENVIRONMENTS IN VLSI PROCESSING, 104
`Medium and Low~Vacuum Systems
`Throttled High-Vacuum Systems
`
`4. BASICS OF THIN FILMS
`
`- THIN FILM GROWTH, 110
`- STRUCTURE OF THIN FILMS, 111
`- MECHANICAL PROPERTIES OF THIN FILMS, 113
`Adhesion
`
`Stress in Thin Films
`
`Other Mechanical Properties
`- ELECTRICAL PROPERTIES OF IVIETALLIC THIN FILMS, 118
`
`IPR2016-01377 Page 0010
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`

`

`CONTENTS
`
`5. SILICON EPITAXIAL FILM GROWTH
`
`— FUNDAMENTALS OF EPITAXIAL DEPOSITION, 125
`
`The Grove Epitaxial Model
`Gas Phase Mass Transfer
`
`Atomistic Model Of Epitaxial Growth
`- CHEMICAL REACTIONS USED IN SILICON EPITAXY, 133
`
`- DOPING OF EPITAXIAL FILMS, 136
`
`Intentional Doping
`
`Autodoping and Solid-State Diffusion
`- DEFECTS IN EPITAXIAL FILMS, 139
`
`Optical Inspection of Epitaxial Films
`Electrical Characterization
`
`Epitaxial Film Thickness Measurements
`Infrared Reflectance Measurement Techniques
`- SILICON ON INSULATORS, 151
`
`Silicon on Sapphire
`Silicon on Other Insulators
`
`- MOLECULAR BEAM EPITAXY OF SILICON, 156
`
`Defects Induced During Epitaxial Deposition and their Nucleation Mechanisms
`Techniques for Reducing Defects in Epitaxial Films
`- PROCESS CONSIDERATIONS FOR EPITAXIAL DEPOSITION, 142
`Pattern Shift, Distortion, and Washout
`— EPITAXIAL DEPOSITION EQUIPIVIENT, 145
`- CHARACTERIZATION OF EPITAXIAL FILMS, 147
`
`Undoped CVD Si02
`
`6. CHEMICAL VAPOR DEPOSITION OF AMORPHOUS
`AND POLYCRYSTALLINE FILMS
`
`- BASIC ASPECTS OF CHEMICAL VAPOR DEPOSITION, 162
`- CHEMICAL VAPOR DEPOSITION SYSTEMS, 164
`
`Components of Generic CVD Systems
`Terminology of CVD Reactor Design
`Atmospheric Pressure CVD Reactors
`Low-Pressure CVD Reactors
`
`Plasma-Enhanced CVD: Physics; Chemistry; and Reactor Configurations
`Photon-Induced CVD Reactors
`- POLYCRYSTALLINE SILICON: PROPERTIES AND CVD DEPOSITION, 175
`
`Properties of Polysilicon Films
`CVD of Polysilicon
`Doping Techniques for Polysilicon
`Oxidation of Polysilicon
`- PROPERTIES AND DEPOSITION OF CVD SiOz FILMS, 182
`Chemical Reactions for CVD Formation
`
`Step Coverage of CVD Si02
`
`IPR2016-01377 Page 0011
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`

`

`CONTENTS
`
`Phosphosilicate Glass
`Borophosphosilicate Glass
`- PROPERTIES AND CVD OF SILICON NITRIDE FILMS, ’191
`
`- OTHER FILMS DEPOSITED BY CVD (OXYNITRIDES and SIPOS), 195
`
`7. THERMAL OXIDATION OF SINGLE-CRYSTAL SILICON 198
`
`- PROPERTIES OF SILICA GLASS, 199
`- OXIDATION KINETICS, 200
`The Linear-Parabolic Model
`
`- THE INITIAL OXIDATION STAGE, 207
`Growth of Thin Oxides
`- THERMAL NITRIDATION OF SILICON AND SiOz, 210
`- FACTORS WHICH AFFECT THE OXIDATION RATE, 211
`
`Oxidation Growth Rates: Crystal Orientation Dependence
`Oxidation Growth Rates: Dopant Effects
`
`Oxidation Growth Rates: Water (H20) Dependence
`Oxidation Growth Rates: Chlorine Dependence
`Oxidation growth Rates: Pressure Efi’ects
`Oxidation Growth Rates: Plasma and Photon Efiects
`— MASKING PROPERTIES OF THERMAILY GROWN SiOz, 219
`- PROPERTIES OF THE Si /Si02 INTERFACE AND OXIDE TRAPS, 220
`Interface Trap Charge
`Fized Oxide Charge
`Mobile Ionic Charge
`Oxide Trapped Charge
`
`Arsenic Difi'usion
`
`Nature of the Si ISi02 Interface
`- STRESS IN SiOZ, 228
`- DOPANT IMPURITY REDISTRIBUTION DURING OXIDATION, 228
`
`- OMDATION SYSTEMS, 230
`Horizontal Furnaces
`
`Suspended Loading Systems
`Vertical Furnaces
`
`— MEASUREMENT OF OXIDE THICKNESS, 234
`
`8. DIFFUSION IN SILICON
`
`- MATHEMATICS OF DIFFUSION, 242
`Ficks First Law
`Ficks Second Law
`Solutions to Ficks Second Law
`
`Concentration Dependence of the Diffusion Coefficient
`- TEMPERATURE DEPENDENCE OF THE DIFFUSION COEFFICIENT, 250
`- DIFFUSION CONSTANTS OF THE SUBSTITUTIONAL
`
`IMPURITIES: B; As; and P, 251
`
`IPR2016-01377 Page 0012
`
`

`

`CONTENTS
`
`Boron Diffusion
`Phosphorus Diffusion
`- ATOIVIISTIC MODELS OF DIFFUSION IN SILICON, 256
`
`The Vacancy Model
`The Vacancy-Interstitial Model
`- DIFFUSION IN POLYCRYSTALLINE SILICON, 261
`
`- DIFFUSION IN SiOz, 262
`- ANOMALOUS DIFFUSION EFFECTS IN SILICON, 262
`Emitter Push Effect
`
`Lateral Diffusion Under Oxide Windows
`Diffusion in an Oxidizing Ambient
`— DIFFUSION SYSTEMS AND DIFFUSION SOURCES, 264
`Gaseous Sources
`
`Liquid Sources
`Solid Sources
`
`— NIEASUREMENT TECHNIQUES FOR DIFFUSED LAYERS, 267
`Sheet Resistivity Measurements
`Junction Depth Measurements
`Doping Profile Measurements
`
`Multiple Implantations
`
`Definitions Associated with Ion Implantation Profiles
`Theory of Ion Stopping
`Models for Predicting Implantation Profiles in Amorphous Solids
`Implanting into Single—Crystal Materials: Channeling
`Boltzmann Transport Equation and Monte-Carlo Approaches to Calculating Profiles
`- ION IMPLANTATION DAMAGE AND DAMAGE ANNEALING IN SILICON, 295
`Implantation Damage in Silicon
`Electrical Activation and Implantation Damage Annealing
`- ION INH’LANTATION EQUIPMENT, 309
`
`9. ION IMPLANTATION FOR VLSI
`
`- ADVANTAGES (AND PROBLEMS) OF ION-INIPLANTATION, 282
`— IMPURITY PROFILES OF INIPLANTED IONS, 283
`
`Components of an Ion Implantation System
`Ion Implanter Types
`Ion Implantation Equipment Limitations
`Ion Implantation Safety Considerations
`- CHARACTERIZATION OF ION IMPLANTATIONS, 318
`Measurement of Implantation Dose and Dose Uniformity
`Measurement of Implantation Depth Profiles
`Measurement of Implantation Damage and Damage Annealing Efficacy
`— ION IIVIPLAN TATION PROCESS CONSIDERATIONS, 321
`
`Selecting Masking Layer Material and Thickness
`Implanting Through Surface Layers
`Shallow Junction Formation by Ion-Implantation
`
`IPR2016-01377 Page 0013
`
`

`

`CONTENTS
`
`10. ALUMINUM THIN FILMS AND
`PHYSICAL VAPOR DEPOSITION IN VLSI
`
`- ALUMINUM THIN FILMS IN VLSI, 332
`- SPUTI'ER DEPOSITION OF THIN FEMS FOR VLSI, 335
`Properties of Glow-Discharges
`Physics of Sputtering
`Sputter Deposited Film Growth
`Radio-frequency (RF) Sputtering
`Magnetron Sputtering
`Bias Sputtering
`Sputter Deposition Equipment
`Commercial Sputtering System Configurations
`Process Considerations in Sputter Deposition
`Reactive Sputtering
`Future Trends in Sputter Deposition
`- PHYSICAL VAPOR DEPOSITION BY EVAPORATION, 374
`Evaporation Basics
`Evaporation Methods
`
`- BASIC PHOTORESIST TERMINOLOGY, 407
`
`Evaporation Process Considerations
`— METAL FILM THICKNESS NIEASUREMENT, 380
`
`11. REFRACTORY METALS and THEIR SILICIDES in VLSI
`
`384
`
`CANDIDATE SILICIDES FOR VLSI APPLICATIONS, 386
`Silicide Resistivities
`
`SILICIDE FORMATION, 388
`Direct Metallurgical Reaction
`Co—Evaporation
`Sputter Deposition: Co-Sputtering and Sputtering from Composite Targets
`Chemical Vapor Deposition
`STRESS IN SILICIDES, 394
`OXIDATION OF SILICIDES, 395
`PROCESS INTERACTION, 397
`SELF-ALIGNED SILICIDE (SALICIDE) TECHNOLOGY, 397
`REFRACTORY NIETAL INTERCONNECTIONS FOR VLSI; 399
`Deposition of CVD Tungsten
`Selective Deposition of Tungsten
`Properties of CVD Tungsten for VLSI Contacts
`Future Trends
`
`12. LITHOGRAPHY I: OPTICAL PHOTORESISTS -
`MATERIAL PROPERTIES AND PROCESS TECHNOLOGY 407
`
`IPR2016-01377 Page 0014
`
`

`

`CONTENTS
`
`- PHOTORESIST MATERIAL PARANIETERS, 409
`Resolution
`
`Sensitivity
`Etch Resistance and Thermal Stability
`Adhesion
`
`Solids Content and Viscosity
`Particulates and Metals Content
`
`Flash Point and TLV Rating
`Process Latitude, Consistency, and Shelf-Life
`- OPTICAL PHOTORESIST MATERIAL TYPES, 418
`Postive Optical Photoresists
`
`Negative Optical Photoresists
`Image Reversal of Positive Resist
`Multilayer Resist Processes
`Contrast Enhancement Layers
`Inorganic Resists
`Dry-Developabie Resists
`Mid-UV and Deep—UV Resists
`Photosensitive Polyimides
`- PHOTORESIST PROCESSING, 429
`Resist Processing: Dehydration Baking and Priming
`Resist Processing: Coating
`Resist Processing: Soft-Bake
`Resist Processing: Exposure
`Resist Processing: Development
`Resist Processing: After Develop Inspection and Linewidth Measurement
`Resist Processing: Post Bake and Deep UV Hardening
`- PHOTORESIST SELECTION, 454
`
`Glass Coating (Chrome)
`
`13. LITHOGRAPHY II:
`OPTICAL ALIGNERS AND PHOTOMASKS
`
`OPTICS OF MCROLITHOGRAPHY, 460
`
`Diffraction, Coherence, Numerical Aperture, and Resolution
`Modulation Transfer Function
`OPTICAL METHODS OF TRANSFERRING PATTERNS
`
`TO A WAFER: OPTICAL ALIGNERS, 468
`
`Light Sources and Light Meters for Optical Aligners
`Contact Printing
`Proximity Printing
`Projection Printing: Scanning Aligners and Steppers
`PATTERN REGISTRATION, 473
`Automatic Alignment
`- MASK AND RETICLE FABRICATION, 476
`Glass Quality and Preparation
`
`IPR2016-01377 Page 0015
`
`

`

`CONTENTS
`
`Mask Imaging (Resist Application and Processing)
`Pattern Generation (Optical and Electron-Beam)
`Mask and Reticle Defects and their Repair
`Pellicles
`
`Critical Dimension and Registration Inspection of Masks and Reticles
`
`14. ADVANCED LITHOGRAPHY
`
`- ELECTRON BEAM LITHOGRAPHY, 493
`Electron Beam Systems
`Writing Strategies
`Electron Scattering in Resists
`Resist Development
`Proximity Effects
`- X-RAY LITHOGRAPHY, 504
`X-Ray Sources
`X—Ray Masks
`X-Ray Resists
`- ION BEAM LITHOGRAPHY, 510
`
`Electrical Aspects of Glow Discharges
`
`15. WET PROCESSING: CLEANING; ETCHING; LIFT-OFF 514
`
`— WAFER CLEANING, 516
`
`Sources of Contamination
`Wafer Cleaning Procedures
`TERNIINOLOGY OF ETCHING, 520
`
`Bias, Tolerance, Etch Rate, and Anisotropy
`
`Selectivity, Overetch, and Feature—size Control
`Determining Required Selectivity with Respect to Substrate, st
`Determining Required Selectivity with Respect to Mask, Sfm
`Loading Effects
`WET ETCHING TECHNOLOGY, 529
`
`Wet Etching Silicon
`Wet Etching Silicon Dioxide
`Wet Etching Silicon Nitride
`Wet Etching Aluminum
`LIFT-OFF TECHNOLOGY FOR PATTERNING, 535
`
`16. DRY ETCHING FOR VLSI
`
`— BASIC PHYSICS AND CHEMISTRY OF PLASMA ETCHING, 542
`The Reactive Gas Glow Discharge
`
`IPR2016-01377 Page 0016
`
`

`

`CONTENTS
`
`Heterogeneous (Surface) Reaction Considerations
`Parameter Control in Plasma Processes
`
`ETCHING SILICON AND SiO2 in CF4 /02 m2, 547
`FIuorine-to-Carbon Ratio Model
`
`ANISOTROPIC ETCHING AND CONTROL OF EDGE PROFILE, 552
`DRY ETCHING VARIOUS TYPES OF THIN FILMS, 555
`Silicon Dioxide (SiOz)
`Silicon Nitride
`
`Polysilicon
`
`Refractory Metal Silicides and Polycides
`Aluminum and Aluminum Alloys
`Organic Films
`
`PROCESS MONITORING AND END POINT DETECTION, 565
`Laser Reflectometry and Laser Reflectance
`Optical Emission Spectroscopy
`Mass Spectroscopy
`DRY ETCIIWG EQUIPBJENT CONFIGURATIONS, 568
`Commercial Dry Etch System Configurations
`Comparison of Single Wafer and Batch Dry Etchers
`PROCESSING ISSUES RELATED TO DRY ETCHING, 574
`Plasma Etching Safety Considerations
`Uniformity and Reproducibility Considerations
`Contamination and Damage of Etched Surfaces
`Process Gases for Dry Etching
`
`17. MATERIAL CHARACTERIZATION TECHNIQUES
`FOR VLSI FABRICATION
`
`Rutherford Backseattering Spectroscopy (RBS)
`
`WHAT ARE WE TRYING TO DETECT, AND HOW IS IT DONE], 586
`Energy Regimes and Energy Levels in Material Characterization
`Definitions of Material Characterization Terminology
`Vacuum Requirements of Compositional Analysis
`NIICROSCOPY FOR VLSI MORPHOLOGY, 589
`Optical Microscopes
`Scanning Electron Microscopes (SEM)
`Transmission Electron Microscopy
`ELECTRON IX-RAY COMPOSITIONAL ANALYSIS TECHNIQUES, 599
`Auger Emission Spectroscopy
`X-Ray Emission Spectrocopy
`X—Ray Photoelectron Spectroscopy (XPS, ESCA)
`X—Ray Fluorescence
`ION BEAM EXCITED COMPOSITIONAL ANALYSIS, 606
`Secondary-Ion Mass Spectroscopy (SIMS)
`Laser [on Mass Spectroscopy (LIMS)
`
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`

`

`18. STRUCTURED APPROACH to DESIGN of EXPERIMENTS
`FOR PROCESS OPTIMIZATION
`
`618
`
`FUNDAMENTALS OF STATISTICS, 619
`
`Samples. Populations, Means, Variance, and Standard Deviation
`Pooled Variance and Degrees of Freedom
`Normal Distributions
`
`Distributions of Averages, t—Distributions, and Confidence Levels
`DESIGN OF EXPERINIENTS: BASIC DEFINITIONS, 625
`
`CHARACTERISTICS OF FACTORIAL EXPERIIVIENTS, 627
`STRATEGY OF DESIGNING EXPERINIENTS, 632
`DESIGNING and ANALYZING 2—LEVEL FULL-FACTORIAL EXPERIMENTS, 634
`
`Method for Designing 2-Level Fall-Factorial Experiments
`Analysis of the Measured Data
`- SCREENING EXPERIMENTS, 641
`- RESPONSE SURFACES, 643
`
`APPENDICES
`
`1. MATERIAL PROPERTIES OF SILICON at 300°K
`2. PHYSICAL CONSTANTS
`3. ARRHENIUS RELATIONSHIP
`
`CONTENTS
`
`- CRYSTALLOGRAPHIC STRUCTURE ANALYSIS, 610
`
`X-Ray Diffraction
`X—Ray Lang Topography
`Neutron Activation Analysis (NAA)
`- SUMMARY OF CHARACTERIZATION TECHNIQUE CAPABILITIES, 612
`- SUGGESTIONS FOR HOW TO ACCOMPLISH AN EFFECTIVE ANALYSIS, 614
`
`INDEX
`
`IPR2016-01377 Page 0018
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`

`

`DRY ETCHING for VLSI
`
`FABRICATION
`
`16
`
`539
`
`In Chapter 15 the procedure of transferring patterns onto regions of Silicon wafers by wet
`etching was described. Wet etching was the standard pattern transfer technique in the process
`sequences used to fabricate early generations of integrated circuits. Its widespread use stemmed
`from the facts that the technology of wet etching was well established, and that liquid etchant
`systems are available with very high selectivity to both substrate and the masking layer (defined
`in Chap. 15). As noted in Chap. 15, however, wet etching processes are typically isotropic.
`Therefore, if the thickness of the film being etched is comparable to the minimum pattern di-
`mension, undercutting due to isotropic etching, becomes intolerable (Fig. la & b). Since many
`films used in VLSI fabrication are 0.5-1.0 pm thick, reproducible and controllable transfer of
`patterns in the 1-2 pm range becomes difficult if not impossible with wet etching. Alternative
`pattern transfer processes must therefore be employed to fabricate devices with such dimensions.
`One alternative pattern transfer method that offers the capability of non-isotropic (or
`anisotropic) etching is "dry" etching. As a result, considerable effort has been expended to
`develop dry etch processes as replacements for wet etch processes. Dry etching also offers the
`important manufacturing advantage of eliminating the handling, consumption, and disposal of the
`relatively large quantities of dangerous acids and solvents used in wet etching and resist stripping
`processes. Dry etching and resist stripping operations utilize comparatively small amounts of
`chemicals (although, as will be discussed later, some of these may ‘still be quite toxic or cor-
`rosive). This chapter deals with the technology of dry etch processes for VLSI fabrication,
`although many of the terms generic to both wet and dry etching are defined in Chap. 15.
`Before launching into a description of the details of dry etching, it is worthwhile to identify
`the characteristics that a useful etching process should exhibit. This approach helps to define the
`problems that must be overcome when developing adequate dry etch processes, and shows why
`some types of dry etch processes may not be suitable for all VLSI applications.
`The overall goal of an etch process for VLSI fabrication is to be able to reproduce the
`features on the mask with fidelity.
`This should be achievable together with control of the
`following aspects of etched features: a) the slope of the feature sidewalls (e.g. the slope of the
`sidewalls of the etched feature should have the desired specific angle, in some cases vertical,
`Fig. 1c - f); and b) the degree of undercutting (i.e. usually the less undercutting the better).
`In
`addition to this capability, a useful etch process should have the following characteristics:
`1) It should be highly selective against etching the mask layer material;
`2) It should be highly selective against etching the material under the film being etched;
`3) The etch rate should be rapid, or the throughput of a machine performing the etch
`should be suitably high;
`
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`

`540
`
`SILICON PROCESSING FOR THE VLSI ERA
`
`/Desired Pattern
`
`Substrate a)
`
`Mask
`
`b)
`
`Substrate
`
`that the mechanism of etching in each type of process can have a physical basis (e.g.
`
`(a) and (b) Isotropic etching of narrow and deep grooves. (a) shows the desired pattern and
`Fig. 1
`(b) shows how the mask must be dimensioned in order to obtain a pattern which resembles the
`desired pattern. (c) -
`(1') SEM micrographs show the results of highly anisotropic etching for
`several materials.
`(c) Anisotropically etched contact hole in an SiO2 layer over Si.
`((1)
`Anisotropically etched poly-Si film over SiOz. (e) l rim-wide features in 3si3ngle-crystal Si.
`(1)
`Anisotropically etched 1.5 pm thick Al-0.7% Cu film, with an SiO2 substrate
`. Copyright 1983,
`Bell Telephone Laboratories, reprinted with permission.
`
`f)
`
`4) The etching should be uniform across the entire wafer, from wafer-to—wafer, and from
`run-to-run;
`
`S) The process should be safe;
`6) The etch process should cause minimal damage to substrates;
`7) The etch mask material should be easily removable after the etching is completed;
`8) The process should be clean (i.e. low incidence of particulate and film contamination);
`9) The process should be conducive to full automation.
`
`As shown in Fig. 2 there is a variety of dry etch process types. This figure also indicates
`
`IPR2016-01377 Page 0020
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`

`

`glow—discharge sputtering [Chap. 10], or ion milling), a chemical basis (e.g. plasma etching), or
`a combination of the two (e.g. reactive ion etching, RIE, and reactive ion beam etching, RIBE).
`In processes that rely predominantly on the physical mechanism of sputtering (including
`RIBE), the strongly directional nature of the incident energetic ions allows substrate material to
`be removed in a highly anisotropic manner (i.e. essentially vertical etch profiles are produced).
`Unfortunately, such material removal mechanisms are also quite non-selective against both
`masking material and materials underlying the layers being etched. ThaLiS, thew
`depend-s largeiyjonsputter‘ yfldijerences between materials. Since the sputter yields for most
`materials are within a factor of three of each other, selectivities are typically not adequate. Fur-
`thermore, since the ejected species are not inherently volatile, redewsition and trenching (see
`Chap. 10) can occur. Another major problem of pattern transfer by physical sputtering involves
`the redeposition of nonvolatile species on the sidewalls of the etched feature]. Mresult of
`these drawbagk’s, dry etch processes for pattern transfer based on physical removal mechanisms
`have not found wide use in VLSI fabrication applications.”
`On the omerhand, dry profisses relying strictly on chemical mechanisms for etching can
`exhibit very high selectivities against both mask and underlying substrate layers. Such purely
`I
`chemical etching mechanisms, however, typically etch in an isotropic fashion. Although some
`applications in VLSI fabrication (eg. pWisLsgippw oxygen plasmas) utilize 311011 PT? "I/
`'
`.Ili“-".-t‘t'
`w, the problem of undercutting associated with isotropic etching is not solveg_by_ them.
`|,
`By adding a physical component to a purely chemical etching mechanism, however, the
`shortcomings of both sputter-based and purely-chemical dry etching processes can be surmount