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`United States Patent
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`5,756,216
`[11] Patent Number:
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`Becker et a1.
`[45] Date of Patent: *May 26, 1998
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`{19]
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`USOOS756216A
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`[54] HIGHLY SELECTIVE NITRIDE SPACER
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`ETCH
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`[75]
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`Inventors: David S. Becker; David J. Keller. both
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`of Boise. Id.
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`[73] Assignee: Micron Technology, Inc.. Boise. Id.
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`[*1 Notice:
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`The term of this patent shall not extend
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`beyond the expiration date of Pat. No.
`5.700.580.
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`[21] Appl. No.: 799,575
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`[22] Filed:
`Feb. 12, 1997
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`Related US. Application Data
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`[63] Continuation of Ser. No. 301,928, Sep. 7, 1994, Pat. No.
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`5,700,580. which is a continuation-in-part of Ser. No.
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`89,205, Jul. 9. 1993, Pat. No. 5,387,312.
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`Int. CL" ................................................... H01L 21/306
`[51]
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`[52] us. Cl.
`428/446; 156/6431; 156/6461;
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`156/650.1; 156/651.1; 156/6531; 156/6621;
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`156/625.1; 428/698; 428/938
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`[58] Field of Search ................................... .. 156/643. 650.
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`156/651. 652. 653. 662.1. 650.1. 651.1.
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`653.1. 643.1. 646.1; 428/446. 698. 938
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`[56]
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`4,568,410
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`4,793,897
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`5,338,395
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`5,374,585
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`References Cited
`
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`U.S. PATENT DOCUMENTS
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`2/1986 Thomquist .............................. 156/643
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`12/1988 Dunfield et a1
`.. 156/643
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`8/1994 Keller et a1.
`..
`156/643
`
`
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`12/1994 Smith et a1.
`.............................. 437/69
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`
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`0283306
`0414372
`235134
`54-125979
`60—246636
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`FOREIGN PATENT DOCUMENTS
`
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`9/ 1988
`European Pat. OE. .
`
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`2/ 1991
`European Pat. Off.
`.
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`4/1986
`Germany .
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`9/1979
`Japan .
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`12/1985
`Japan .
`
`
`OTHER PUBLICATIONS
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`“Thin Film Investigations and Sputter Etchng”—Emmoth et
`211; Annual Report—Res. Inst. Phys. (Swed) 1979; abstract
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`only.
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`“Highly Selective Etching of Silicon Nitride (Si3N4) to
`Silicon Dioxide Employing Fluorine and Chlorine Atoms
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`
`
`Generated by Microwave Discharge”—J. Electrochem. Soc;
`vol. 136. No. 7; 7—89: pp. 2032—2034 Suto et a1.
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`
`
`“Selective Etching of Silicon Nitride Using Remote Plasmas
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`of CF4 and SF ” J. Vac. Sci. A. vol. 7 No. 3. pt. 1;
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`Loewenstein 5—89: abstract only.
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`Primary Examiner—Fred Zitomer
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`ABSTRACT
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`[57]
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`A method is provided for fomiing a nitride spacer. in which
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`a layer of oxide is grown superjacent a substrate and the
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`semiconductor features disposed thin-eon. A layer of nitride
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`is deposited superjacent the oxide layer. and a major hori-
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`zontal portion of the nitride layer anisotropically etched with
`an ionized fluorocarbon compound. The remainder of the
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`horizontal portion of the nitride layer is removed with NF3
`ions in combination with ionized halogen-containing
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`compound,
`thereby creating nitride spacers adjacent the
`features.
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`9 Claims, 2 Drawing Sheets
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`Page 1 of 6
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`TSMC Exhibit 1042
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`TSMC v. IP Bridge
`IPR2016-01376
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`Page 1 of 6
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`TSMC Exhibit 1042
`TSMC v. IP Bridge
`IPR2016-01376
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`

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`US. Patent
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`May 26, 1998
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`US. Patent
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`May 26, 1998
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`5,756,216
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`compared to typical nitride spacer etches. All that is required
`to insure the nitride has been removed. in the process of the
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`present invention. is a measurement of the thin oxide layer
`after the etch process is complete. in order to determine if the
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`etch has partially penetrated into the source/drain reoxida-
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`tion layer.
`A further advantage of the process of the present
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`invention.
`is the ability to adjust
`the spacer thickness.
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`Control of the dimensions of the spacers enables the engi-
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`neer to control the dimensions of the underlying implant
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`regions. The ability to space the implant area away from the
`transistor allows the voltage threshold (VT) to be adjusted to
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`optimize the electrical performance of the transistor.
`
`I
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`HIGHLY SELECTIVE NITRIDE SPACER
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`ETCH
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`This application is a continuation of US. patent appli-
`cation Ser. No. 08/301928. now US. Pat. No. 5.700.580.
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`filed Sept. 7. 1994. which was a continuation-in—part of U. S.
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`patent application Ser. No. 08/089205 filed Jul. 9. 1993.
`now US. Pat. No. 5.387.312 issued Feb. 7. 1995.
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`Field of the Invention
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`This invention relates to semiconductor manufacturing.
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`and more particularly to a process for the formation of
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`nitride spacers employing a selective nitride to oxide etch.
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`BACKGROUND OF THE INVENTION
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`“Spacers” are frequently used in semiconductor manufac-
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`turing as protective structures against subsequent processing
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`steps. In particular. spacers are used to protect underlying
`source/drain areas during doping or implanting steps. The
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`dopant material is unable to penetrate the spacer. and thus.
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`the underlying layer remains relatively unafi’ected by the
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`implanted material.
`transistors) become
`As semiconductor devices (e.g..
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`smaller. the spacers disposed along side them must also
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`become smaller. Spacer formation typically involves
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`etching. and research continues for ever better and cleaner
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`etching processes.
`In transistor formation. a nitride spacer is commonly
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`disposed over the source/drain regions during implant steps.
`Some of the current processes are limited to spacer thick-
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`nesses which are only twice the thickness of the underlying
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`oxide. See. for example. Japanese patent 5-299394 which
`proposes an etch process having a 2:1 nitride to oxide
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`selectivity. This limitation with respect to nitride to oxide
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`selectivity also limits the possible size and thickness of the
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`nitride spacer.
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`SUMMARY OF THE INVENTION
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`The present invention relates to use of a thin oxide layer
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`(i.e.. the source/drain reoxidation layer) under a deposited
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`nitride layer to act as an etch stop during the formation of the
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`spacer. The use of a highly selective nitride to oxide etch
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`prevents the nitride etch from removing the thin oxide layer.
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`and consuming the underlying silicon in the sensitive
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`source/drain areas of the transistor.
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`The process of the present invention therefore. provides a
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`unique nitride etch that is suitable for etching subrnicron
`features. while stopping on a thin oxide layer without pitting
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`the underlying silicon.
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`The present invention provides a process for forming
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`the
`nitride spacers by forming features on a substrate.
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`features having horizontal and vertical surfaces. and grow—
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`ing an oxide layer superjacent the features. The oxide layer
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`is conformal. A nitride layer is deposited superjacent the
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`oxide layer. The nitride layer is conformal. Spacers are
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`formed from the nitride layer. The spacers are disposed
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`adjacent the features. and have a thickness which is greater
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`than twice the thickness of the oxide layer.
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`One advantage of the process of the present invention is
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`that it enables a wide range of oxide thicknesses. The present
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`invention provides the ability to adjust the thickness of the
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`thin oxide (source/drain reoxidation) layer with minimal
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`adjustment to the thickness of the nitride layer. and the
`subsequent nitride spacer.
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`Another advantage of the selective nitride spacer etch of
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`the present invention is the ease of process measurements as
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`Page 4 of 6
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`Brief Description of the Drawings The present
`invention will be better understood from reading
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`the following description of nonlimitative
`embodiments. with reference to the attached
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`drawings. wherein below:
`FIG. 1 is a schematic cross-section of a semiconductor
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`gate device having oxide and nitride layers disposed
`thereon. according to the process of the present invention;
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`FIG. 2 is a schematic cross-section of the semiconductor
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`gate device of FIG. 1. after a low selective nitride to oxide
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`etch. according to the process of the present invention;
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`FIG. 3 is a schematic cross-section of the semiconductor
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`gate device of FIG. 2. after a highly selective nitride to oxide
`etch. according to the process of the present invention; and
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`FIG. 4 is a schematic cross—section of a semiconductor
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`gate device in which the substrate has been damaged due to
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`overetching.
`DETAILED DESCRIPTION OF THE
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`INVENTION
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`The process of the present invention is described and
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`illustrated with respect to a DRAM transistor structure.
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`However. one having ordinary skill in the art. upon being
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`apprised of the invention. in hindsight would be able to
`apply it to other semiconductor devices. such as. but not
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`limited to EPROMS. EEPROMS. and etc. The process of the
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`present invention is not limited to the formation of spacers
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`along gate structures. but is also adaptable to the formation
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`of nitride spacers adjacent other semiconductor features.
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`The formation of a nitride spacer using the selective
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`nitride to oxide etch process of the present invention is as
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`follows:
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`FIG.
`1 illustrates a reoxidation 2 layer formed over
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`transistor gate structures 4. The reoxidation layer 2 is a
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`thin oxide layer which is preferably grown over the
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`surface of the wafer 1. The source/drain reoxidation
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`areas 5 are the locations of the future source/drain
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`regions for their associated gate structures 4. The
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`oxidation layer 2 has a thickness of less than approxi—
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`mater 150 A. of which 70 A is gate oxidation. and the
`additional amount is grown. Both values are adjustable
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`to achieve the desired oxide 2 thickness.
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`Alayer of silicon nitride 3 is disposed superjacent the thin
`reoxidation layer 2. The silicon nitride layer 3 has a thick-
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`ness of approximately 1.6 KA. The oxide 2 and nitride 3
`layers are preferably conformal in nature.
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`In this particular etch. layer 3 acts as a protective or
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`resistant area to cover the future source/drain areas 5 during
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`the subsequent implant or doping process. The nitride layer
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`3 is preferably conformally deposited. There are several
`methods commonly known in the art to accomplish such
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`deposition.
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`The structure of FIG. 1 is then etched according to the
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`process of the present invention to result in the structure
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`depicted in FIG. 2. The etch of the present invention has a
`basis in the physical nature of the reaction. and more
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`specifically. in ion bombardment.
`Hence.
`invention is most
`the process of the present
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`effective when performed in a chamber in which ions can be
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`accelerated. Such chambers are known in the art. and
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`include. but are not limited to. reactive ion etchers. prefer-
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`ably magnetically enhanced reactive ion etchers. and high
`density source etchers.
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`The present invention involves the physical impact of the
`ions which enables the reaction to proceed. as compared to
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`a simple chemical reaction. While the invention anticipates
`chemical reaction. it uses the physical impact of the etchant
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`chemical ions to enhance the uniformity of the etch process.
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`The process of the present invention comprises two etch
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`steps. preferably performed in situ. i.e.. in the same reaction
`chamber. The first step. is a low selective nitride to oxide
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`etch which is used to remove a major portion of the nitride
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`layer 3. Approximately 75% the thiclmess of the nitride is
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`removed. In the preferred embodiment. approximately 1.4
`KA of silicon nitride 3 is etched.
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`The preferred chemistry is approximately 50 sccm CF4
`and approximately 10 sccm CHF3. The etch parameters are
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`approximately 200 mtorr. at 600 Watts. and 100 Gauss.
`Of course. one having ordinary skill in the art will realize
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`that the above values will vary depending on the make and
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`model of the etcher used in the process. The etch processes
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`of the present invention were carried out in an Applied 5000
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`Magnetically Enhanced Reactive Ion Etcher. sold by
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`Applied Materials Corporation of Santa Clara. Calif.
`The low selective etch is an anisotropic etch. and there-
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`fore removes material
`in one direction.
`i.e.. vertically.
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`Hence. the nitride material 3 on the top of the gate structures
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`4 and along the surface of the substrate 1 is removed more
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`quickly than the nitride material 3 on the sides of the gate
`structures 4. In this manner. “spacers” 3 are formed on either
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`side of the semiconductor gate structures 4.
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`The process of the present invention. then employs a
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`highly selective nitride to oxide etch to remove the remain-
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`ing nitride 3 which is on the top portion of the gate structures
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`4 and also covering the thin oxide layer 2. The highly
`selective etch has an etch selectivity in the approximate
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`range of 49:1. This means that the nitride 3 is removed at a
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`rate 49 times faster than the oxide 2 is removed The
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`remaining nitride 3 in the preferred embodiment is approxi-
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`mately 200 A. which is about 25% of the thickness of the
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`deposited nitride layer 3.
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`The process is halted upon reaching the 150 .5. of oxide
`layer 2 of the source/drain reoxidation The parameters for
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`highly selective nitride to oxide etch phase of the present
`process are 500 mtorr. at 200 Watts. and 50 Gauss. Once
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`again. these parameters will vary with the make and model
`of etcher employed in the process.
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`The nitride to oxide selective etch is accomplished by
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`using an NF3/IIBr chemistry. as described more fully in US.
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`Pat. No. 5.338.395 entitled. “Method for Enhancing Etch
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`Uniformity Useful in Etching Submicron Nitride Features.”
`having a common inventor with the present application. and
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`assigned to Micron Semiconductor. Inc.
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`The etch chemistry comprises approximately 49 sccm
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`N173. along with a hydrogen halide. such as. for example.
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`HCl. HI. and I-IBr. The preferred embodiment employs
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`approximately 21 sccm HBr.
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`The fluorine from the NF3 gives a very fast nitride etch
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`rate. while the bromine from the HBr gives a very slow
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`oxide etch rate.
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`The process of the present invention results in a spacer
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`which is substantially anisotropic. There is essentially no
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`undercutting apparent in the nitride spacers 3. Thus. submi-
`cron features can be etched with considerable reliability.
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`Experiments have shown that the individual steps which
`make up the present invention yield faulty devices if they are
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`performed alone. If a high selective nitride to oxide etch
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`alone is used to remove all of the nitride 3. undercutting of
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`the gate structures 4 tends to result. thereby causing faulty
`transistors 4. If. on the other hand. a low selective nitride to
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`oxide etch alone is used to remove all of the nitride 3. most
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`of the reoxidation layer 2 is also removed. and the substrate
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`1 below is consequently etched. and therefore damaged by
`the process. as shown in FIG. 4.
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`Poor nitride to oxide etches have resulted in low refresh
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`times in DRAM semiconductor transistors because the sub-
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`strate damage lessens the ability of the transistor to hold a
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`charge. Since charge on the cell leaks more rapidly. more
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`frequent refreshing of the cell is necessitated.
`The process of the present
`invention overcomes the
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`abovementioned drawbacks. Hence.
`the process of the
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`present invention results in improved semiconductor device
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`functionality.
`All of the US. Patents cited herein are hereby incorpo-
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`rated by reference herein as if set forth in their entirety.
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`While the particular process as herein shown and dis-
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`closed in detail is fully capable of obtaining the objects and
`advantages herein before stated. it is to be understood that it
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`is merely illustrative of the presently preferred embodiments
`of the invention and that no limitations are intended to the
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`details of construction or design herein shown other than as
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`described in the appended claims. For example. one having
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`ordinary skill in the art will realize that the present invention
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`is adaptable to the forming of spacers for other semicon—
`ductor devices.
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`What is claimed is:
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`l. A method of etching a substrate. said method compris-
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`ing the following steps of:
`providing a substrate having at least one layer of oxide
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`and at least one corresponding layer of nitride disposed
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`over said at least one layer of oxide; exposing said
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`substrate to a first atmosphere to remove a first portion
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`of nitride. said first atmosphere comprising a fluoro-
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`carbon that provides a source of polymerizable ele-
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`ments during the removal of said first portion of nitride;
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`and
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`after said step of exposing said substrate to a first
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`aunosphere. exposing said layered substrate to a second
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`atmosphere different from said first atmosphere and
`having hydrogen halide. to selectively remove a second
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`portion of nitride selectively with respect to said oxide.
`to expose a portion of said oxide layer.
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`2. The method of etching according to claim 1. wherein
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`said hydrogen halide comprises at least one of HBr. HCl.
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`and HI.
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`3. The method of etching according to claim 2. wherein
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`said fluorocarbon comprises at least one of CHF3 and CF...
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`4. The method of etching according to claim 3. wherein
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`said second atmosphere further comprises NF3.
`5. The method of etching according to claim 4.
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`wherein said substrate comprises features with horizontal
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`surfaces; and
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`wherein said first atmosphere and said second atmosphere
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`provide primarily anisotropic etching to directionally
`remove portions of nitride material. said portions over
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`horizontal surfaces of the features of said substrate.
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`6. The method of etching according to claim 4. wherein
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`said first atmosphere anisotropically etches said layered
`substrate.
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`50
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`65
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`Page 5 0f 6
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`Page 5 of 6
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`

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`5.756.216
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`6
`second portion of nitride material of said nitride layer
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`to expose a portion of said oxide layer at regions
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`corresponding to the horizontal surfaces of said fea-
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`tures of said base substrate while leaving nitride mate-
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`rial adjacent the vertical surface of said features.
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`8. A method according to claim 7. wherein said first
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`atmosphere comprises at least one fluorocarbon compound
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`from the group of CHF3 and CF4. and provides primarily an
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`anisotropic etch to remove said first portion of nitride
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`material.
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`9. A method according to claim 8. wherein said second
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`annosphere further comprises NF3. and provides primarily
`an anisotropic etch during the removal of said second
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`portion of nitride material.
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`*
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`*
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`7. A method of etching a layered substrate. said method
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`comprising steps of:
`providing a substrate having features with horizontal and
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`vertical surfaces;
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`forming an oxide layer conformally over said substrate
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`including said features;
`providing a generally conformal nitride layer over said
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`oxide layer:
`exposing said layered substrate to a first atmosphere 10
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`comprising fluorocarbons. to remove a first portion of
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`nitride material of said nitride layer: and
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`after said exposure to said first atmosphere. exposing the
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`layered substrate to a second atmosphere difierent from
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`said first atmosphere and having ionized hydrogen 15
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`halide. to remove. selectively with respect to oxide. 21
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`5
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`5
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`Page 6 of 6
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`Page 6 of 6
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