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`[19]
`United States Patent
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`6,091,081
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`[11] Patent Number:
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`[45] Date of Patent: Jul. 18, 2000
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`Matsubara et al.
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`US006091081A
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`[54]
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`[75]
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`INSULATING FILM COMPRISING
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`AMORPHOUS CARBON FLUORIDE, A
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`SEMICONDUCTOR DEVICE COMPRISING
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`SUCH AN INSULATING FILM
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`Inventors: Yoshihisa Matsubara; K0 N0guchi;
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`Shinya Ito; Noriaki Oda; Akira
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`Matsumoto; Takashi Ishigami;
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`Masahiko Nakamae; Tadahiko
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`Horiuchi; Kazuhiko Endo; T0ru
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`Tatsumi; Yoshishige Matsum0t0, all of
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`Tokyo, Japan
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`[73] Assignee: NEC Corporation, Tokyo, Japan
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`] Appl. No.: 08/982,585
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`Filed:
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`Dec. 2, 1997
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`r—‘r—‘r—iWNNONH
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`Dec. 2, 1996
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`Jun. 5, 1997
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`Foreign Application Priority Data
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`Japan .................................. .. 8—321694
`[JP]
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`Japan .................................. .. 9—148017
`[JP]
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`Int. C1.7 ............................................... .. H01L 31/0312
`[51]
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`[52] US. Cl.
`............................... .. 257/52; 257/55; 257/76;
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`257/77; 438/482; 438/483
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`[58] Field of Search ................................ .. 257/77, 76, 55,
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`257/52; 438/482, 483
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`[56]
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`References Cited
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`FOREIGN PATENT DOCUMENTS
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`2/1996 European Pat. Off.
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`0696819
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`0701283
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`5—74962
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`8—83842
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`8—222557
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`8—2365 17
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`9—246242
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`3/1996
`3/1993
`3/1996
`8/1996
`9/1996
`9/1997
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`European Pat. Off.
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`Japan .
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`Japan .
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`Japan .
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`Japan .
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`Japan .
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`Primary Examiner—William Mintel
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`Attorney, Agent, or Firm—Sughrue, Mion, Zinn, Macpeak
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`& Seas, PLLC
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`[57]
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`ABSTRACT
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`A structure and manufacturing process of a low dielectric
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`constant
`interlayer insulating film used between wiring
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`layers and semiconductor devices using such film are dis-
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`closed. The insulating film which can withstand in an actual
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`process comprises an amorphous carbon fluoride film. A
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`diamond like carbon film and a silicon excess layer are
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`disposed on both sides of the amorphous carbon fluoride
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`film to be inserted between the wiring layers, whereby
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`adhesion to wiring and another insulating film contacting it
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`is significantly enhanced. In addition, a silicon based insu-
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`lating film is disposed and flattened on a multilayer film
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`containing an amorphous carbon fluoride film buried with a
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`wiring layer, and is used as a hard mask for anisotropically
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`etching the diamond like carbon film and the amorphous
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`carbon fluoride film with oxygen plasma to form a Via hole.
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`13 Claims, 23 Drawing Sheets
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`TSMC Exhibit 1036
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`TSMC v. IP Bridge
`IPR2016-01376
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`Page 1 of 34
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`TSMC Exhibit 1036
`TSMC v. IP Bridge
`IPR2016-01376
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`US. Patent
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`US. Patent
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`Sheet 2 0f 23
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`6,091,081
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`mm 3
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`US. Patent
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`Sheet 3 0f 23
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`US. Patent
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`US. Patent
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`US. Patent
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`Sheet 6 0f 23
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`US. Patent
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`Sheet 7 0f 23
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`6,091,081
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`US. Patent
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`Sheet 8 0f 23
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`Sheet 12 0f 23
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`FIG.12
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`FIG.13
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`FIG. 1 4
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`Sheet 15 0f 23
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`FIG.16
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`FIG.17
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`Sheet 19 0f 23
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`6,091,081
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`FIG.21(e)
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`451
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`43451
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`W---—----.l
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`y--------------
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`FIG.21 (f)
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`451
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`42
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`451
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`FIG.21(g)
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`6,091,081
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`FIG.22
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`Sheet 21 0f 23
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`6,091,081
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`FlG.23(a)
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`451
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`7///////////////////////////////
`i\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\.\\\\\\\\\\\\\\‘
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`-----......-.
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`FIG 23(b)
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`'I/A
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`43'
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`n\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\V
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`L\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\V FIG.23(C)
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`m’
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`FIG.23(d)
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`6,091,081
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`451
`4:
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`41 —
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`33.:2..¥‘._.__.\3333‘3332
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`FIG.24(e)
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`FIG.24(f)
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`f;
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`16
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`Sheet 23 0f 23
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`6,091,081
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`FIG.25
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`SILICON NITRIDE
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`AMORPHOUS CARBON FLUORIDE
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`SILICON OXIDE
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`Cu(AES)INTENSITY
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`(a.u.)
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`Page 24 of 34
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`6,091,081
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`1
`INSULATING FILM COMPRISING
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`AMORPHOUS CARBON FLUORIDE, A
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`SEMICONDUCTOR DEVICE COMPRISING
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`SUCH AN INSULATING FILM
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`The present invention relates to a semiconductor device
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`having a plurality of laminated wiring layers, or multilayer
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`wiring layers separated by insulating layers, and such an
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`insulating film, as well as a manufacturing process for such
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`a semiconductor device.
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`2. Description of the Related Art
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`As integration becomes more and more dense for a
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`semiconductor large-scale integrated circuit (LSI),
`indi-
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`vidual devices with dimensional accuracy of 14 pm or less
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`are now integrated near the surface of a Si substrate. An LSI
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`exhibits its function only after its individual devices are
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`connected by wiring. However, if wiring is detoured to avoid
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`intersections in interconnections between the individual
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`devices, interconnecting delay may be caused because area
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`occupied by wiring or wiring length is increased. A tech-
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`nique has been commonly used for providing wiring on
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`multiple layers by inserting insulating layers between wiring
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`to prevent intersections and/or overlapping of wiring.
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`This concept of multilayer wiring is shown in FIG. 16. An
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`insulating film 1631 is formed in a silicon substrate 161, and
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`is formed with a contact hole 164 therein. Acontact plug 164
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`is buried in the contact hole 164 to connect a device forming
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`region 162 to a first wiring layer 1651. In addition, the first
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`wiring layer 1651 is connected to a second wiring layer 1652
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`through a via plug 1661 filled in a via hole 1661 opened in
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`the insulating film 1632. The second wiring layer 1652 is
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`connected to a third wiring layer 1653 through a via plug
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`1662 filled in a via hole 1662 opened in the insulating film
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`1633. Further multilayer wiring can be attained by sequen-
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`tially repeating the process described above. The process is
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`completed by covering the last wiring layer with a sealing
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`film 167.
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`This technique for multilayer wiring with thin insulating
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`layers therebetween has a large stray capacity causing inter-
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`connecting delay. When a signal containing high frequency
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`components is transmitted through two vertically adjacent
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`wiring layers having an inter-layer insulating film
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`therebetween, crosstalk is generated, thereby causing erro-
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`neous operation. To prevent
`interconnecting delay or
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`crosstalk, it is sufficient to increase the distance between the
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`upper and lower wiring, or to thicken the inter-layer insu-
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`lating film. However, thickening the inter-layer insulating
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`film makes it necessary to form a deep contact hole or via
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`hole. Formation of a deep contact hole or via hole makes it
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`further difficult to perform the dry etching technology for
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`forming these holes. Thus, it is desirable to have the thinnest
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`inter-layer insulating film as possible. The semiconductor
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`integrated circuit
`technology for 256 megabit DRAM
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`(Dynamic Random Access Memory) or thereafter requires a
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`smaller contact hole diameter of 14 pm or less. However, if
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`it is desired to hold a ratio of the depth of a contact hole to
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`its diameter, or an aspect ratio, up to five from the viewpoint
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`of the dry etching technology, the thickness of the inter-layer
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`insulating film is necessarily required to be 1 pm or less.
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`While the problem on the stray capacity between the upper
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`and lower wiring layers is addressed in the above, an
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`increase of stray capacity is also serious between wiring
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`formed on a same plane. It is because, as the semiconductor
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`integrated circuit is miniaturized, thickness of wiring and
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`Page 25 0f 34
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`2
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`distance between wiring are also miniaturized, necessarily
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`leading to the same problem as in the wiring thickness of 14
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`pm. Since the wiring spacing cannot be widened in view of
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`the requirement for a high degree of integration, the problem
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`on interconnecting delay or crosstalk is more serious
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`between wiring disposed on the same layer than between the
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`upper and lower wiring for which the inter-layer insulating
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`film may potentially be thickened.
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`To accurately determine interconnecting delay and
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`crosstalk accompanying an increase of inter-wiring capacity
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`determined by the thickness of the upper and lower inter-
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`layer insulating film or the interlayer insulating film in the
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`same plane,
`is necessary to handle it as a distributed
`it
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`constant circuit. FIG. 14 shows the capacity per unit wiring
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`length between a wiring layer insulated by a silicon oxide
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`film with a thickness H (dielectric constant: 3.9) and wiring
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`on a silicon substrate, which is described by L. M. Dang, et
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`al. in “IEEE Electron Device Letters,” Vol. EDL-2, 1981, p.
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`196. It shows that, as wiring width W decreases, capacity C
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`significantly increases by a so-called fringe effect when
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`compared with the so-called plane parallel plate approxi-
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`mated capacity. It is also known that the higher wiring height
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`T is, the larger capacity C is. Although the insulating film
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`between the silicon substrate and the lowermost wiring as
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`shown in FIG. 14 is not usually called an inter-layer insu-
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`lating film, it is common in the problems of interconnecting
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`delay and crosstalk. Thus,
`the inter-layer insulating film
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`referred to in this specification includes an insulating film
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`contacting the silicon substrate and performing electric
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`insulation with the wiring as well. In addition, FIG. 15
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`described in the above-referenced paper shows that, as
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`wiring spacing is miniaturized, the total capacity Cf with the
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`silicon substrate per unit length increases as further minia-
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`turization is attained and when W/H is more than 1. This
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`results because, although the capacity C11 between the
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`wiring and the silicon substrate decreases, the capacity C12
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`between adjacent wiring separated by wiring spacing S
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`contrarily increases. That is, although operating speed can
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`be increased for individual elements of a semiconductor
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`integrated circuit through miniaturization, wiring resistance
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`and stray capacity increases in the wiring interconnecting
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`these elements by miniaturization. Consequently, the oper-
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`ating speed for the entire LSI is not improved at all. Both of
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`FIGS. 14 and 15 show results of analysis on the stray
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`capacity between the silicon substrate and the wiring dis-
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`posed through an insulating film, however,
`they do not
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`address the stray capacity between the wiring layers, even
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`though the situation is the same for the stray capacity
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`between the wiring layers.
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`Thus, it is an urgent necessity, in light of the foregoing
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`discussion, to develop an inter-layer insulating film with a
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`low dielectric constant er in place of Si3N4 (er: 7 or less) and
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`silicon oxide (er: 3.9 or less) which are insulating films
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`commonly used in the LSI
`technology. An amorphous
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`carbon fluoride film with a dielectric constant er<3 is dis-
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`closed in Japanese Patent Application Laid-Open Nos.
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`08-83842, 08-222557, 08-236517 and the like is expected as
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`a suitable material with a low dielectric constant er.
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`BRIEF SUMMARY OF THE INVENTION
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`As described above, since the amorphous carbon fluoride
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`film has a low dielectric constant er, it is expected to be
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`suitable as an interlayer insulating film in multilayer wiring.
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`However,
`there are still problems in the technology of
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`forming a contact hole contacting a semiconductor diffusion
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`layer or a via hole for connecting wiring layers, which
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`prevent it from being put in practical use. The inventors tried
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`10
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`15
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`20
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`25
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`35
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`60
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`65
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`Page 25 of 34
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`6,091,081
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`3
`to open a hole in an amorphous carbon fluoride by referring
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`to the description in Japanese Patent Application Laid-Open
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`No. 5-74962 which is directed to an inter-layer insulating
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`film which is believed to be a film similar to the amorphous
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`carbon fluoride disclosed in Japanese Patent Application
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`Laid-Open Nos. 08-83842, 08-222557, 08-236517. Japanese
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`Patent Application Laid-Open No. 5-74962 shows that con-
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`ventional photolithography technology can be used, thus the
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`process is to use conventional resist which is a mixture of
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`phenol resin and photosensitive agent or a resin such as
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`cyclized rubber and photosensitive resin, to apply it on an
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`amorphous carbon fluoride film in a thickness of 1—1.5 um,
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`and to open a hole with a diameter of 0.2 pm by assuming
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`a highly integrated LSI of 64 megabit or higher DRAM. The
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`film disclosed in Japanese Patent Application Laid-Open
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`No. 5-74962 has a problem because it contains a large
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`amount of hydrogen, and is poor in thermal resistance which
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`is a requirement for the interlayer film.
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`It is desired to realize the structure as shown in FIG. 16
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`utilizing an amorphous carbon fluoride as an inter-layer
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`insulating film. A technique is described for opening a
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`contact hole 164, or a via hole 1661 or 1662 in the amor-
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`phous carbon fluoride inter-layer insulating films. First, the
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`conventional resist described above is applied on the amor-
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`phous carbon fluoride, followed by exposure and develop-
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`ment to form a selection mask for etching. Subsequently, a
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`hole is opened in the amorphous carbon fluoride by an ion
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`milling process with this resist film as a mask. A hole
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`opening by the ion milling is adopted because the amor-
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`phous carbon fluoride film is strong against ordinary acid or
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`alkali, and cannot be strongly etched. However, since the
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`hole is opened by ion milling, which is a substantially pure
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`physical process, the resist as the mask itself, is ground in
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`the course of hole opening in the amorphous carbon fluoride.
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`Thus,
`the hole can be hardly opened in the amorphous
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`carbon fluoride with a film thickness less than 0.4 pm by
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`forming the resist in a thickness of 1 pm or more. However,
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`it is very difficult to open a hole in a film with a thickness
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`of 0.4 pm or more by the ion milling process.
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`After opening the hole with the ion milling process, the
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`resist is removed. It is found that film reduction is caused in
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`the amorphous carbon fluoride by wet treatment using resist
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`remover heated to about 100° C. It was further tried to
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`remove the resist with an ashing process in oxygen plasma.
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`However, it is found that even this process rapidly removes
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`the amorphous carbon fluoride together with the resist. That
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`it is very difficult to selectively work the amorphous
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`carbon fluoride film with the conventional photolithography
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`technology.
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`Japanese Patent Application Laid-Open No. 09-246242
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`discloses a technology to break such a situation, and shows
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`that it is sufficient to use a silicone type resist as a mask for
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`selective etching of the inter-layer insulating film containing
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`the amorphous carbon fluoride film. This is because the
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`silicone type resist
`is not etched by oxygen plasma. In
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`addition, an arrangement is adopted, in which a silicon oxide
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`film, silicon nitride film, or silicon oxi-nitride film, which is
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`a mixed film of both, is disposed on at least one principle
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`plane of the amorphous carbon fluoride film. It is shown to
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`be effective in improving adhesion near the inter-layer
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`insulating film particularly when the stoichiometric ratio of
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`the interface contacting at
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`the amorphous carbon
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`fluoride of the silicon oxide film, silicon nitride film, or
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`silicon oxi-nitride film is made silicon excess. In addition, it
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`is shown that, if the silicon oxide film, silicon nitride film,
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`or silicon oxi-nitride film is disposed on the sectional region
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`of the amorphous carbon fluoride film exposed to the side
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`10
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`Page 26 0f 34
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`4
`wall of a hole formed to pass through the insulating film
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`containing the amorphous carbon fluoride film,
`then the
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`degree of freedom can be significantly increased for the
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`conditions in forming a conductive plug. The conductive
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`plug is subsequently buried in the hole, whereby a semi-
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`conductor device having a conductive plug with low specific
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`resistance can be obtained. It is also shown that adhesion of
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`the conductive plug is also improved if the silicon oxide
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`film, silicon nitride film, or silicon oxi-nitride film is silicon
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`excess in the composition of the film adjacent to the amor-
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`phous carbon fluoride film.
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`It is also described that, if an oxide film, nitride film, or
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`oxi-nitride film providing improvement of adhesion to the
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`top surface of the amorphous carbon fluoride film is dis-
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`posed on an insulating layer containing the amorphous
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`carbon fluoride film, the surface of amorphous carbon fluo-
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`ride film which has been unevened due to burying of a
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`wiring layer or the like can be flattened in good reproduc-
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`ibility with chemical mechanical polishing by detecting the
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`oxide film, nitride film or oxi-nitride film existing in the
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`recessed portion for completion of polishing.
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`As described above, Japanese Patent Application No.
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`09-246242 shows that processing of the amorphous carbon
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`fluoride film becomes possible by silicone resist. However,
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`since the silicone resist is not common, and is negative
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`resist, there is a problem that it is not a good compatible with
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`the current LSI process technology mainly using positive
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`resist. The reason why the positive resist is mainly used in
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`the LSI process lies in that, as well known, it provides higher
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`processing accuracy than the negative resist. Although suf-
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`ficient processing accuracy has been obtained on the labo-
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`ratory level even with the silicone type resist, to introduce
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`the amorphous carbon fluoride film in an actual LSI manu-
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`facturing line, it is necessary to build a process constituted
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`by positive resist which is a mixture of phenol resin and
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`photosensitive resin or a resin such as cyclized rubber and
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`photosensitive resin.
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`Furthermore,
`in the flattening process by the chemical
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`mechanical polishing, although there is no problem in the
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`it
`laboratory level,
`is found to be difficult
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`process as stable as in polishing a conventional film such as
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`silicon oxide film.
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`Here, the object of the present invention is to provide a
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`technology for selectively forming a contact hole or via hole
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`when an amorphous carbon fluoride film is applied on an
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`inter-layer insulating film with low dielectric constant er.
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`Such a technology is effective for solving the problems of
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`interconnecting delay or crosstalk, burying wiring, and a
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`practical LSI process using conventional positive resist
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`similar to that described mainly on the technology for
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`flattening the inter-layer insulating film in Japanese Patent
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`Application Laid-Open No. 5-74962. However, the present
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`invention also applies to not only an LSI chip having a
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`multilayer wiring structure, but also a device in which a
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`number of LSI chips are mounted on a substrate, such as a
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`multi-chip module.
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`The present invention improves adhesion with another
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`material by making one principle plane an amorphous
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`carbon fluoride film coated with a DLC (diamond like
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`carbon) film containing hydrogen to prevent fluorine in the
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`amorphous carbon fluoride film from being emitted outside,
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`and by removing fluorine in a surface contacting another
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`material. The addition of hydrogen provides the following
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`effects:
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`When the amorphous carbon fluoride film is applied to an
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`LSI, it is effective to use a DLC film containing hydrogen in
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`Page 26 of 34
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`6,091,081
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`5
`at least one of its primary planes, and an amorphous carbon
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`fluoride film coated with at least one layer of film selected
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`from a silicon excess silicon oxide film, silicon nitride film,
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`or silicon oxi-nitride film. In this case, adhesion with another
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`material is significantly improved by adjusting the supply of
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`gas of the chemical vapor deposition (CVD) process to
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`deposit a silicon excess silicon oxide film, silicon nitride
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`film, or silicon oxi-nitride film, which is a mixed film of both
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`(hereinafter comprehensively called “silicon excess film”).
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`The CVD process for
`the silicon excess film uses an
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`approach to mix gas containing silicon, such as silane
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`(SiH4), and gas containing oxygen or nitrogen, such as 02,
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`nitrogen monoxide (NO) or ammonia (NH3). In an adhesion
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`layer consisting of the DLC film containing hydrogen and
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`the silicon excess film, carbons, a DLC component element,
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`are terminated by rich silicon and hydrogen in the silicon
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`excess film, and are bound to provide enhancement of
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`adhesion.
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`In particular, adhesion with another material is signifi-
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`cantly high for an amorphous carbon fluoride film which has
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`an adhesion layer with a transition layer in which at least
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`carbon and silicon mix in the interface between a DLC film
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`containing hydrogen, and at least one layer of silicon excess
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`film.
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`to
`Formation of such adhesion layer first enables it
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`implement, on a practical level, a semiconductor device in
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`which at least part of insulating material is constituted by an
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`amorphous carbon fluoride.
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`In particular, if an amorphous carbon fluoride film with an
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`adhesion layer as described above is applied to at least a part
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`of the inter-layer insulating film in a multilayer wiring
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`structure, it is possible to implement a semiconductor device
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`with sufficiently high process reliability