SILICON PROCESSING
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`THE VLSI ERA
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`FOR
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`VOLUME 1:
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`PROCESS TECHNOLOGY
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`STANLEY WOLF Ph.D.
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`Professor, Department of Electrical Engineering
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`California State University, Long Beach
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`Long Beach, California
`and
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`Instructor, Engineering Extension, University of California, Irvine
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`I
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`RICHARD N. TAUBER PhD.
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`Manager of VLSI Fabrication
`TRW - Microelectronics Center
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`Redondo Beach, California
`and
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`Instructor, Engineering Extension, University of California, Irvine
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`LATTICE
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`PRESS
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`Sunset Beach, California
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`Page 1 0f 25
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`TSMC Exhibit 1032
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`TSMC v. IP Bridge
`IPR2016-01376
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`TSMC Exhibit 1032
`TSMC v. IP Bridge
`IPR2016-01376
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`Library of Congress Cataloging in. Publication Data
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`Wolf, Stanley
`and Tauber, Richard N.
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`Silicon Processing for the VLSI Era
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`Volume 1
`: Process Technology
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`
`
`Includes Index
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`
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`1. Integrated circuits-Very large scale
`
`
`
`
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`integration.
`I. Title
`2. Silicon.
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`86-081923
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`ISBN 0—961672-3-7
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`987654
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`PRINTED IN THE UNITED STATES OF ANIERICA
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`Page 2 of 25
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`Page 2 of 25
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`

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`PREFACE
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`
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`CONTENTS
`
`
`
`
`
`vii
`
`PROLOGUE
`
`
`
`xxi
`
`
`
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`1. SILICON: SINGLE-CRYSTAL GROWTH AND WAFERING 1
`
`
`
`
`
`
`
`
`
`
`
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`
`
`
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`— TERIVIINOLOGY OF CRYSTAL STRUCTURE, 1
`
`
`
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`- MANUFACTURE OF SINGLE—CRYSTAL SILICON, 5
`
`
`
`
`
`
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`From Raw Material to Electronic Grade Polysilicon
`
`
`
`
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`- CZOCHRALSKI (CZ) CRYSTAL GROWTH, 8
`
`
`
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`Czochralski Crystal Growth Sequence
`
`
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`
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`Incorporation of Impurities into the Crystal (Normal Freezing)
`
`
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`Modifications Encountered to Normal Freezing in CZ Growth
`
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`Czochralski Silicon Growing Equipment
`
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`
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`Analysis of Czochralski Silicon in Ingot Form
`
`
`
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`
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`Measuring Oxygen and Carbon in Silicon Using Infrared Absorbance Spectroscopy
`
`
`
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`- FLOAT-ZONE SINGLE-CRYSTAL SILICON, 21
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`- FROM INGOT TO FINISHED WAFER: SLICING; ETCHING; POLISHING, 23
`
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`
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`— SPECIFICATIONS OF SILICON WAFERS FOR VLSI, 26
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`- TRENDS IN SILICON CRYSTAL GROWTH AND VLSI WAFERS, 30
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`2. CRYSTALLINE DEFECTS, THERMAL PROCESSING,
`
`
`
`
`AND GETTERING
`
`
`
`
`
`36
`
`
`
`
`
`
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`- CRYSTALLINE DEFECTS IN SILICON, 37
`
`
`Point Defects
`
`
`
`One—Dimensional Defects (Dislocations)
`
`
`
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`Area Defects (Stacking Faults)
`
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`Bulk Defects and Precipitation
`
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`- INFLUENCE OF DEFECTS ON DEVICE PROPERTIES, 51
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`Leakage Currents in pn Junctions
`
`
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`Collector-Emitter Leakage in Bipolar Transistors
`
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`Minority Carrier Lifetimes
`
`
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`Gate Oxide Quality
`
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`Threshold Voltage Control
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`Wafer Resistance to Warpage
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`Page 3 of 25
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`Page 3 of 25
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`

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`xii
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`
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`CONTENTS
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`
`
`~ CHARACTERIZATION OF CRYSTAL DEFECTS, 55
`
`
`
`- THERMAL PROCESSING, 56
`
`
`
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`Rapid Thermal Processing (RTP)
`
`
`
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`- OXYGEN IN SILICON, 59
`
`
`- GETTERING, 61
`
`
`Basic Gettering Pinciples
`
`
`Extrinsic Gettering
`
`
`Intrinsic Gettering
`
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`3. VACUUM TECHNOLOGY FOR VLSI APPLICATIONS
`
`
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`73
`
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`
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`
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`- FUNDAMENTAL CONCEPTS OF GASES AND VACUUMS, 73
`Pressure Units
`
`
`
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`Pressure Ranges
`
`
`
`
`
`
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`Mean Free Path and Gas Flow Regimes
`
`
`
`
`
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`- LANGUAGE OF GAS /SOLID INTERACTIONS, 77
`
`
`
`
`
`
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`- TERMINOLOGY OF VACUUM PRODUCTION AND PUMPS, 78
`
`
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`— ROUGHING PUMPS, 85
`
`
`
`Oil-Sealed Rotary Mechanical Pumps
`
`
`Pump Oils
`
`
`Roots Pumps
`
`
`
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`
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`- HIGH VACUUM PUMPS I: DIFFUSION PUD/IFS, 89
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`- HIGH VACUUM PUMPS II: CRYOGENIC PUMPS, 92
`
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`- HIGH VACUUM PUNIPS III: TURBOMOLECULAR PUMPS, 95
`
`
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`
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`— SPECIFICATION OF VACUUM PUIVIPS FOR VLSI, 97
`
`
`
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`-r TOTAL PRESSURE MEASUREMENT, 97
`
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`- MEASUREMENTS OF PARTIAL PRESSURE: Residual Gas Analyzers, 101
`
`
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`Operation of Residual Gas Analyzers (RGA)
`
`
`
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`RGAs and Non-High Vacuum Applications: Differential Pumping
`
`
`
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`Interpretation of RGA Spectra
`
`
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`RGA Specification List
`
`
`
`
`
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`
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`~ HIGH GAS FLOW VACUUM ENVIRONMENTS IN VLSI PROCESSING, 104
`
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`Medium and Low—Vacuum Systems
`
`
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`Throttled High-Vacuum Systems
`
`
`
`,
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`109 .
`
`
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`
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`4. BASICS OF THIN FILMS
`
`
`
`I
`
`
`
`
`
`- THIN FILM GROWTH, 110
`
`
`
`
`
`— STRUCTURE OF THIN FILMS, 111
`
`
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`
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`- MECHANICAL PROPERTIES OF THIN FILMS, 113
`Adhesion
`
`Stress in Thin Films
`
`
`
`
`
`
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`Other Mechanical Properties
`- ELECTRICAL PROPERTIES OF METALLIC THIN FILMS, 118 V
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`Electrical Transport in Thin Films
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`Page 4 of 25
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`Page 4 of 25
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`

`

`CONTENTS
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`
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`
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`5. SILICON EPITAXIAL FILM GROWTH
`
`
`
`Xiii
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`
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`124
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`- FUNDAIVIENTALS OF EPITAXIAL DEPOSITION, 125
`
`
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`The Grove Epitaxial Model
`I
`
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`
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`Gas Phase Mass Transfer
`
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`Atomistic Model Of Epitaxial Growth
`
`
`
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`- CHEIVIICAL REACTIONS USED IN SILICON EPITAXY, 133
`
`
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`- DOPING OF EPITAXIAL FILMS, 136
`
`
`Intentional Doping
`
`
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`Autodoping and Solid~State Diffusion
`
`
`
`
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`— DEFECTS IN EPITAXIAL FILMS, 139
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`Defects Induced During Epitaxial Deposition and their Nucleation Mechanisms
`
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`Techniques for Reducing Defects in Epitaxial Films
`
`
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`
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`- PROCESS CONSIDERATIONS FOR EPITAXIAL DEPOSITION, 142
`
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`Pattern Shift, Distortion, and Washout
`
`
`
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`— EPITAXIAL DEPOSITION EQUIPMENT, 145
`
`
`
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`- CHARACTERIZATION OF EPITAXIAL FILMS, 147
`
`
`
`
`
`Optical Inspection of Epitaxial Films
`Electrical Characterization
`
`
`
`
`
`
`Epitaxial Film Thickness Measurements
`
`
`
`Infrared Reflectance Measurement Techniques
`
`
`
`
`- SILICON ON'INSULATORS, 151
`
`
`
`Silicon on Sapphire
`Silicon on Other Insulators
`
`
`
`
`
`
`
`
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`- MOLECULAR BEAM EPITAXY OF SILICON, 156
`
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`6. CHEMICAL VAPOR DEPOSITION OF AMORPHOUS
`
`
`
`AND POLYCRYSTALLINE FILMS
`
`
`
`161
`
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`
`
`- BASIC ASPECTS OF CHEMICAL VAPOR DEPOSITION, 162
`
`
`
`
`
`— CHEMICAL VAPOR DEPOSITION SYSTEMS, 164
`
`
`
`
`
`Components of Generic CVD Systems
`
`
`
`
`
`Terminology of CVD Reactor Design
`
`
`
`
`Atmospheric Pressure CVD Reactors
`Low-Pressure CVD Reactors
`
`
`
`
`
`
`
`
`
`Plasma—Enhanced C VD: Physics; Chemistry; and Reactor Configurations
`Photon—Induced CVD Reactors
`
`
`
`
`
`
`
`
`
`~ POLYCRYSTALLINE SILICON: PROPERTIES AND CVD DEPOSITION, 175
`
`
`
`
`Properties of Polysilicon Films
`
`
`
`CVD of Polysilicon
`
`
`
`Doping Techniques for Polysilicon
`
`
`
`Oxidation of Polysilicon
`
`
`
`
`
`
`— PROPERTIES AND DEPOSITION OF CVD 5102 FILMS, 182
`
`
`
`
`
`
`Chemical Reactions for CVD Formation
`
`
`
`
`Step Coverage of CVD Si02
`
`
`
`Undoped CVD S102
`
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`Page 5 of 25
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`Page 5 of 25
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`

`

`xiv
`
`
`
`CONTENTS
`
`
`
`
`
`Phosphosilicate Glass
`
`
`Borophosphosilicate Glass
`
`
`
`
`
`
`
`
`- PROPERTIES AND CVD OF SILICON NITRIDE FILMS, 191
`
`
`
`
`
`
`
`
`— OTHER FILMS DEPOSITED BY CVD (OXYNITRIDES and SIPOS), 195
`
`
`
`
`
`
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`
`
`7. THERMAL OXIDATION OF SINGLE-CRYSTAL SILICON 198
`
`
`
`
`
`
`
`
`- PROPERTIES OF SILICA GLASS, 199
`
`
`
`— OXIDATION KINETICS, 200
`The Linear-Parabolic Model
`
`
`
`
`
`
`
`- THE INITIAL OXIDATION STAGE, 207
`
`
`
`
`Growth of Thin Oxides
`
`
`
`
`
`
`
`- THERMAL NITRIDATION OF SILICON AND SiOZ, 210
`
`
`
`
`
`
`
`- FACTORS WHICH AFFECT THE OXIDATION RATE, 211
`
`
`
`
`
`
`Oxidation Growth Rates: Crystal Orientation Dependence
`
`
`
`
`
`Oxidation Growth Rates: Dopant Efiects
`
`
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`
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`Oxidation Growth Rates: Water (H20) Dependence
`
`
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`Oxidation Growth Rates: Chlorine Dependence
`
`
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`
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`Oxidation growth Rates: Pressure Effects
`
`
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`Oxidation Growth Rates: Plasma and Photon Effects
`
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`
`
`
`- MASKING PROPERTIES OF THERMALLY GROWN SiOZ, 219
`
`
`
`
`
`
`
`
`— PROPERTIES OF THE Si /Si02 INTERFACE AND OXIDE TRAPS, 220
`
`
`
`
`Interface Trap Charge
`
`
`
`Fixed Oxide Charge
`
`
`
`Mobile Ionic Charge
`
`
`
`Oxide Trapped Charge
`
`
`
`
`Nature of the Si ISiOZ Interface
`
`
`
`
`
`- STRESS IN SiOZ, 228
`
`
`
`
`
`- DOPANT IMPURITY REDISTRIBUTION DURING OXIDATION, 228
`
`
`
`- OXIDATION SYSTEMS, 230
`Horizontal Furnaces
`
`
`
`
`Suspended Loading Systems
`Vertical Furnaces
`
`
`
`
`
`
`- MEASUREMENT OF OXIDE THICKNESS, 234
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`8. DIFFUSION IN SILICON ;
`
`242
`
`
`
`
`
`
`
`
`- MATHEMATICS OF DIFFUSION, 242
`Ficks First Law
`
`
`
`Ficks Second Law
`
`
`
`Solutions to Ficks Second Law
`
`
`
`
`
`
`
`
`
`
`
`Concentration Dependence of the Diffusion Coefi'icient
`
`
`
`
`
`
`- TEIVIPERATURE DEPENDENCE OF THE DIFFUSION COEFFICIENT, 250
`- DIFFUSION CONSTANTS OF THE SUBSTITUTIONAL
`
`
`
`
`
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`
`
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`
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`IMPURII‘IES: B; As; and P, 251
`
`
`Arsenic Difi’usion
`
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`Page 6 of 25
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`Page 6 of 25
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`

`

`CONTENTS
`
`
`
`
`
`xv
`
`
`
`Boron Diffusion
`
`
`Phosphorus Diffusion
`
`
`
`
`
`
`- ATOMISTIC MODELS OF DIFFUSION IN SILICON, 256
`
`
`
`The Vacancy Model
`
`
`
`The Vacancy-Interstitial Model
`
`
`
`
`- DIFFUSION IN POLYCRYSTALLINE SILICON, 261
`
`
`
`
`— DIFFUSION IN SiOz, 262
`
`
`
`
`
`— ANOMALOUS DIFFUSION EFFECTS IN SILICON, 262
`
`
`
`Emitter Push Effect
`
`
`
`
`
`Lateral Diffusion Under Oxide Windows
`
`
`
`
`
`Difi'usion in an Oxidizing Ambient
`
`
`
`
`
`- DIFFUSION SYSTEMS AND DIFFUSION SOURCES, 264
`Gaseous Sources
`
`
`
`Liquid Sources
`Solid Sources
`
`
`
`
`
`
`
`— IVIEASUREIVIENT TECHNIQUES FOR DIFFUSED LAYERS, 267
`
`
`
`Sheet Resistivity Measurements
`
`
`Junction Depth Measurements
`
`
`
`
`Doping Profile Measurements
`
`
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`
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`
`
`9. ION IMPLANTATION FOR VLSI
`
`
`
`280
`
`
`
`
`
`
`
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`
`
`
`
`- ADVANTAGES (AND PROBLEMS) OF ION-MLANTATION, 282
`
`
`
`
`
`
`- IMPURITY PROFILES OF IMPLANTED IONS, 283
`
`
`
`
`
`
`Definitions Associated with Ion Implantation Profiles
`
`
`
`
`\
`Theory of Ion Stopping
`
`
`
`
`
`
`
`Models for Predicting Implantation Profiles in Amorphous Solids
`
`
`
`
`
`V
`Implanting into Single-Crystal Materials: Channeling
`
`
`
`
`
`
`
`
`
`Boltzmann Transport Equation and Monte-Carlo Approaches to Calculating Profiles
`
`
`
`
`
`
`
`- ION INIPLANTATION DAMAGE AND DAMAGE ANNEALING IN SILICON, 295
`
`
`
`
`
`Implantation Damage in Silicon
`
`
`
`
`
`Electrical Activation and Implantation Damage Annealing
`
`
`
`
`— ION IMPLANTATION EQUIPMENT, 309
`
`
`
`
`
`
`Components of an Ion Implantation System
`
`
`
`Ion Implanter Types
`
`
`
`Ion Implantation Equipment Limitations
`
`
`
`
`Ion Implantation Safety Considerations
`
`
`
`
`- CHARACTERIZATION OF ION IMPLANTATIONS, 318
`
`
`
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`Measurement of Implantation Dose and Dose Uniformity
`
`
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`
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`Measurement of Implantation Depth Profiles
`
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`Measurement of Implantation Damage and Damage Annealing Efficacy
`
`
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`
`
`- ION IMPLAN‘TATION PROCESS CONSIDERATIONS, 321
`
`
`
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`
`
`Selecting Masking Layer Material and Thickness
`
`Implanting Through Surface Layers
`A
`
`
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`Shallow Junction Formation by Ion—Implantation
`
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`Multiple Implantations
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`Page 7 of 25
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`Page 7 of 25
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`

`
`
`xvi
`
`CONTENTS
`
`
`
`
`
`
`
`
`10. ALUMINUM THIN FILMS AND
`
`
`
`
`PHYSICAL VAPOR DEPOSITION IN VLSI
`
`
`
`331
`
`
`
`
`
`
`
`
`
`- ALUIVflNUM THIN FILMS IN VLSI, 332
`
`
`
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`
`
`
`- SPUTTER DEPOSITION OF THIN FILMS FOR VLSI, 335
`
`
`
`Properties of Glow-Discharges
`
`
`
`Physics of Sputtering
`
`
`
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`Sputter Deposited Film Growth
`
`
`Radiofrequency (RF) Sputtering
`
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`Magnetron Sputtering
`
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`Bias Sputtering
`
`
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`Sputter Deposition Equipment
`
`
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`Commercial Sputtering System Configurations
`
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`
`
`Process Considerations in Sputter Deposition
`
`
`Reactive Sputtering
`
`
`
`
`
`Future Trends in Sputter Deposition
`
`
`
`
`
`— PHYSICAL VAPOR DEPOSITION BY EVAPORATION, 374
`
`
`Evaporation Basics
`
`
`Evaporation Methods
`
`
`Evaporation Process Considerations
`
`
`
`
`
`- METAL FILM THICKNESS NIEASUREMENT, 380
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`11. REFRACTORY METALS and THEIR SILICIDES in VLSI
`
`
`
`384
`
`
`
`
`
`
`
`
`- CANDIDATE SILICIDES FOR VLSI APPLICATIONS, 386
`Silicide Resistivities
`
`
`
`
`- SILICIDE FORMATION, 388
`
`
`
`Direct Metallurgical Reaction
`
`Co-Evaporation
`
`
`
`
`
`
`
`Sputter Deposition: Co-Sputtering and Sputtering from Composite Targets
`
`
`
`Chemical Vapor Deposition
`
`
`
`
`— STRESS IN SILICIDES, 394
`
`
`
`- OXIDATION OF SILICIDES, 395
`
`
`
`~ PROCESS INTERACTION, 397
`
`
`
`
`
`- SELF-ALIGNED SILICIDE (SALICIDE) TECHNOLOGY, .‘397_
`
`
`
`
`
`- REFRACTORY NH'ETAL INTERCONNECTIONS FOR VLSI, 399
`
`
`
`
`Deposition of CVD Tungsten
`r
`
`
`
`
`Selective Deposition. of Tungsten
`
`
`
`
`
`
`Properties of CVD Tungsten for VLSI Contacts
`Future Trends
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`12. LITHOGRAPHY I: OPTICAL PHOTORESISTS -
`
`
`
`
`
`MATERIAL PROPERTIES AND PROCESS TECHNOLOGY 407
`
`
`
`- BASIC PHOTORESIST TERMINOLOGY, 407
`
`
`
`
`
`
`Page 8 of 25
`
`Page 8 of 25
`
`

`

`CONTENTS
`
`
`
`xvii
`
`
`
`
`
`
`
`
`
`
`
`
`- PHOTORESIST MATERIAL PARAMETERS, 409
`Resolution
`
`
`Sensitivity
`
`
`
`
`Etch Resistance and Thermal Stability
`Adhesion
`
`
`
`
`
`Solids Content and Viscosity.
`Particulates and Metals Content
`
`
`
`
`
`
`
`
`Flash Point and TLV Rating
`
`
`
`
`
`Process Latitude, Consistency, and Shelf-Life
`
`
`
`
`- OPTICAL PHOTORESIST MATERIAL TYPES, 418
`
`
`
`Postive Optical Photoresists
`
`
`
`Negative Optical Photoresists
`
`
`
`
`Image Reversal of Positive Resist
`
`
`
`Multilayer Resist Processes
`
`
`Contrast Enhancement Layers
`
`
`Inorganic Resists
`
`
`Dry-Developable Resists
`
`
`
`Mid—UV and Deep-UV Resists
`
`
`Photosensitive Polyimides
`
`
`
`— PHOTORESIST PROCESSING, 429
`
`
`
`
`
`Resist Processing: Dehydration Baking and Priming
`
`
`
`Resist Processing: Coating
`
`
`Resist Processing: Soft—Bake
`
`
`
`Resist Processing: Exposure
`
`
`
`,
`Resist Processing: Development
`
`
`
`
`
`
`
`Resist Processing: After Develop Inspection and Linewidth' Measurement
`
`
`
`
`
`
`
`
`Resist Processing: Post Bake and Deep UV Hardening
`
`
`
`- PHOTORESIST SELECTION, 454
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`.
`-
`13. LITHOGRA’PHY II:
`
`
`
`OPTICAL ALIGNERS AND PHOTOMASKS
`
`
`
`
`
`
`
`
`
`
`
`- OPTICS OF MICROLITHOGRAPHY, 460
`
`
`
`
`
`Difi’raction, Coherence, Numerical Aperture, and Resolution
`
`
`
`Modulation Transfer Function
`— OPTICAL NIETHODS OF TRANSFERRING PATTERNS
`
`
`
`
`
`
`
`
`
`
`TO A WAFER: OPTICAL ALIGNERS, 468
`
`
`
`
`
`
`
`Light Sources and Light Meters for Optical Aligners
`
`
`Contact Printing
`:
`-
`
`
`Proximity Printing
`
`
`
`
`
`Projection Printing: Scanning Aligners and Steppers
`
`
`
`‘ - PATTERN REGISTRATION, 473
`
`
`I
`'
`Automatic Alignment
`
`
`
`
`
`- MASK AND RETICLE FABRICATION, 476 '
`
`
`
`
`Glass Quality and Preparation
`
`
`
`Glass Coating (Chrome)
`
`
`
`
`
`Page 9 of 25
`
`:
`
`
`
`-
`
`~
`
`459
`
`
`
`Page 9 of 25
`
`

`

`xviii
`
`
`
`CONTENTS
`
`
`
`
`
`
`
`
`Mask Imaging (Resist Application and Processing)
`
`
`
`
`
`Pattern Generation (Optical and Electron-Beam)
`
`
`
`
`
`
`
`Mask and Reticle Defects and their Repair
`Pellicles
`
`
`
`
`
`
`
`
`
`Critical Dimension and Registration Inspection of Masks and Reticles
`
`
`
`
`
`
`
`14. ADVANCED LITHOGRAPHY
`
`
`
`493
`
`
`
`
`
`
`
`- ELECTRON BEAM LITHOGRAPHY, 493
`
`
`
`Electron Beam Systems
`
`
`Writing Strategies
`
`
`
`Electron Scattering in Resists
`
`
`Resist Development
`
`
`Proximity Effects
`
`
`- X—RAY LITHOGRAPHY, 504
`
`
`X—Ray Sources
`
`
`X—Ray Masks
`
`
`X—Ray Resists
`
`
`
`- ION BEAM LITHOGRAPHY, 510
`
`
`
`
`
`
`
`
`
`
`
`
`
`15. WET PROCESSING: CLEANING; ETCHING; LIFT-OFF 514
`
`
`
`'
`
`
`
`— WAFER CLEANING, 516
`
`
`
`Sources of Contamination
`
`
`
`
`Wafer Cleaning Procedures
`
`
`
`
`- TERD/IINOLOGY OF ETCHING, 520
`
`
`
`
`
`
`Bias, Tolerance, Etch Rate, and Anisotropy
`
`
`
`
`
`Selectivity, Overetch, and Feature-size Control
`
`
`
`
`
`
`
`Determining Required Selectivity with Respect to Substrate, S
`Determining Required Selectivity with Respect to Mask, Sfm fS
`
`
`
`
`
`
`
`
`
`
`Loading Effects
`
`
`
`- WET ETCHING TECHNOLOGY, 529
`
`
`
`Wet Etching Silicon
`
`
`
`Wet Etching Silicon Dioxide
`
`
`
`
`Wet Etching Silicon Nitride
`
`
`
`Wet Etching Aluminum
`
`
`
`
`« LIFT-OFF TECHNOLOGY FOR PATTERNING, 535
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`16. DRY ETCHING FOR VLSI
`
`
`
`'
`
`539
`
`
`
`
`
`
`
`
`
`
`- BASIC PHYSICS AND CHEMISTRY OF PLASMA ETCHING, 542
`
`
`
`
`
`The Reactive Gas Glow Discharge
`
`
`
`
`Electrical Aspects of Glow Discharges
`
`
`
`
`
`Page 10 of 25
`
`Page 10 of 25
`
`

`

`CONTENTS
`
`
`
`Xix
`
`
`
`
`
`
`
`
`
`
`Heterogeneous (Surface) Reaction Considerations
`Parameter Control in Plasma Processes
`
`
`
`
`
`
`
`
`
`
`
`— ETCHING SILICON AND Si02 in CF4 IOZ IHZ, 547
`
`
`Fluorine-to-Carbon Ratio Model
`
`
`
`
`
`
`
`
`
`
`- ANISOTROPIC ETCHING AND CONTROL OF EDGE PROFILE, 552
`
`
`
`
`
`
`
`
`— DRY ETCHING VARIOUS TYPES OF THIN FILMS, 555
`
`
`
`Silicon Dioxide (Si02)
`Silicon Nitride
`
`
`
`Polysilicon
`
`
`
`
`Refractory Metal Silicides and Polycides
`
`
`
`
`Aluminum and Aluminum Alloys
`
`
`Organic Films
`
`
`
`
`
`
`- PROCESS MONITORING AND END POINT DETECTION, 565
`
`
`
`
`
`Laser Reflectometry and Laser Reflectance
`
`
`
`Optical Emission Spectroscopy
`
`
`Mass Spectroscopy
`
`
`
`
`- DRY ETCHING EQUIPNIENT CONFIGURATIONS, 568
`
`
`
`
`
`Commercial Dry Etch System Configurations
`
`
`
`
`
`
`
`
`Comparison of Single Wafer and Batch Dry Etchers
`
`
`
`
`
`
`-_ PROCESSING ISSUES RELATED TO DRY ETCHING, 574
`
`
`
`
`Plasma Etching Safety Considerations
`
`
`
`Uniformity and Reproducibility Considerations
`
`
`
`
`
`
`Contamination and Damage of Etched Surfaces
`
`
`
`
`
`Process Gases for Dry Etching
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`17. MATERIAL CHARACTERIZATION TECHNIQUES
`
`
`
`FOR VLSI FABRICATION
`
`
`
`586
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`— WHAT ARE WE TRYING TO DETECT, AND HOW IS IT DONE?, ‘58
`
`
`
`
`
`
`
`
`Energy Regimes and Energy Levels in Material Characterization
`-
`
`
`
`
`
`Definitions of Material Characterization Terminology
`
`
`
`
`
`Vacuum Requirements of Compositional Analysis
`
`
`
`
`- MCROSCOPY FOR VLSI MORPHOLOGY, 589
`
`
`Optical Microscopes
`
`
`
`
`Scanning Electron Microscopes (SEM)
`
`
`
`Transmission Electron Microscopy
`
`
`
`
`- ELECTRON /X-RAY COMPOSITIONAL ANALYSIS TECI‘INIQUES, 599
`
`
`
`Auger Emission Spectroscopy
`
`
`
`X—Ray Emission Spectrocopy
`
`
`
`
`X-Ray Photoelectron Spectroscopy (XPS, ESCA)
`
`
`X-Ray Fluorescence
`
`
`
`
`
`- ION BEAM EXCITED COMPOSITIONAL ANALYSIS, 606
`
`
`
`
`Secondary-Ion Mass Spectroscopy (SIMS)
`
`
`
`
`
`Laser Ion Mass Spectroscopy (LIMS)
`
`
`
`
`Rutherford Backseattering Spectroscopy (RBS)
`
`
`
`
`
`
`
`
`
`Page 11 of 25
`
`Page 11 of 25
`
`

`

`xx
`
`
`CONTENTS
`
`
`
`
`
`
`— CRYSTALLOGRAPHIC STRUCTURE ANALYSIS, 610
`
`
`X—Ray Diffraction
`
`
`
`X-Ray Lang Topography
`
`
`
`
`Neutron Activation Analysis (NAA)
`
`
`
`
`
`
`- SUMIVIARY OF CHARACTERIZATION TECHNIQUE CAPABILITIES, 612
`
`
`
`
`
`
`
`
`- SUGGESTIONS FOR HOW TO ACCOMPLISH AN EFFECTIVE ANALYSIS, 614
`
`
`
`
`
`
`
`
`
`
`
`18. STRUCTURED APPROACH to DESIGN of EXPERIMENTS
`
`
`
`FOR PROCESS OPTIMIZATION
`
`
`
`618
`
`
`
`
`
`
`
`
`
`- FUNDAMENTALS OF STATISTICS, 619
`
`
`
`
`
`
`Samples, Populations, Means, Variance, and Standard Deviation
`
`
`
`
`
`
`Pooled Variance and Degrees of Freedom
`Normal Distributions ‘
`
`
`
`
`
`
`
`
`Distributions of Averages, t-Distributions, and Confidence Levels
`
`
`
`
`
`
`— DESIGN OF EXPERIMENTS: BASIC DEFINITIONS, 625
`
`
`
`
`— CHARACTERISTICS OF FACTORIAL EXPERIIVIENTS, 627
`
`
`
`
`
`- STRATEGY OF DESIGNING EXPERIMENTS, 632
`
`
`
`
`
`
`— DESIGNING and ANALYZING 2—LEVEL FULL-FACTORIAL EXPERIIVIENTS, 634
`
`
`
`
`
`
`Method for Designing 2—Level Full~Fact0rial Experiments
`
`
`
`
`
`Analysis of the Measured Data
`
`
`
`- SCREENlNG EXPERIIVIENTS, 641
`
`
`
`
`- RESPONSE SURFACES, 643
`
`
`
`
`
`
`
`
`
`,
`
`647
`64 8
`649
`
`6 5 1
`
`
`
`
`
`
`
`APPENDICES
`
`
`
`
`
`
`
`
`1. MATERIAL PROPERTIES OF SILICON at 300°K
`
`
`
`
`2. PHYSICAL CONSTANTS
`
`
`3. ARRHENIUS RELATIONSHIP
`
`
`
`'
`
`IND E X
`
`
`
`Page 12 of 25
`
`Page 12 of 25
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`

`

`LITHOGRAPIIYI: OPTICAL RESIST MATERIALS AND PROCESS TECHNOLOGY 423
`
`images, gives good critical dimension control, good contrast, and adequate depth of focus.
`It also has the potential for allowing the slope of the resultant images to be controlled without
`the film thickness loss normally present in conventional positive resist processing. Wall angles
`in excess of 90" (Le. inverted wall angles) may even be produced, a feature that could be useful in
`metal lift-off processing.
`
`Multilayer Resist Processos
`
`As resist films cross over steps their local thickness is altered. This arises because the resist
`that crosses the top of the steps is much thinner than the resist that covers wafer regions which
`are low—lying. Thus, during exposure either the thin resist becomes overexposed, or the thicker
`resist underexposed. Upon development, a resist pattern crossing a step will therefore possess a
`linewidth variation (Le. narrower on the top of the step). For lines in which step heights
`approach the size of the linewidth (eg. for linewidths or spaces of 1 pm or less), such variations
`in dimension become intolerable.
`In addition, standing wave effects in thick resist layers reduces
`their minimum resolution. Finally, reflective substrates also degrade resolution in thick resist
`films (see section Lirtewr’dth Variation Over Steps).
`The use of thin resist films could relieve the problems from standing waves and reflective
`substrates, but would not overcome the step coverage limitation. A thick planarizing layer
`under a thin-imaging layer would, however, reduce the impact of all of the problems listed above.
`Approaches using such underlying planarizing layers are known as muiri-Jevei resist (MLR)
`processes, since two or more layers are required to implement them”.
`In MLR processes, an Organic layer is therefore first spun onto the wafer, thicker than the
`underlying steps, to provide a surface which is smooth and significantly more planar than the
`original wafer topography.
`After pre—baking this bottom layer, a thin imaging layer is
`deposited. In some cases a third thin transfer layer, such as SiOZ, is deposited on the thick layer
`prior to depositing the imaging layer. High resolution patterns are then created in the thin top
`layer. These are next precisely transferred into the bottom layer using the delineated imaging
`layer as a blanket exposme mask, or as an etching mask to pattern the planarizing layer. Patterns
`With resolutions less than 0.5 pm have been delineated with MLR processes.
`The advantages gained by MLR processes, however, are obtained at the expense of added
`complexity. This can result in diminished throughput, possible increase in defects, and increased
`costs. The degree of additional complexity that can be tolerated, and the expected increase in
`defect density depend on the maturity of the alignment tools and the overall device process.
`Three multilayer resist processes will be desoribed in this section: a) a portable conformable
`mask process, or PCM; b) an organic tri-layer process; and c) a bilayer process utilizing an
`inorganic resist (AgZSe/Gex8e1_x) as the imaging layer.
`The PCM is the simplest MLR scheme, and is the only one that has reportedly been used
`by 1985 in a VLSl production mode”.
`In this process, a thick underlying layer of resist (cg.
`PMMA, which is sensitive to deep UV), is used to planarize the surface. A thin resist that is
`sensitive to the near UV, but opaque to deep UV, is then deposited over the PMMA.
`The upper layer is conventionally patterned, and subsequently used as a conformal deep UV
`mask for PMMA. The PMMA is then flood exposed (using deep UV) and developed. The
`rfi‘rsolution of the PCM process, and that of the tri—layer processes are equal, since they utilize the
`3lime. imaging resist layer. The resolution of Cit=.xSe1_x layer process is higher because of its
`edge sharpening effect. The instability of the PMMA under dry etch, however, is a limitation of
`[he PCM process. To improve the durability during dry-etching, the imaging resist is often
`r{Blamed on top of the PMMA. This is often referred to as a capped structure. Another attraction
`
`Page 13 of 25
`
`Page 13 of 25
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`

`

`424
`
`SILICON PROCESSING FOR THE VLSI ERA
`
`of the PCM process is that it can be done on conventional lithographic equipment, together with
`a source of deep—UV for the flood exposure of the PMMA. 0n the other hand, film interfaCe
`layers at the PMMA {Optical resist interface can cause exposure and develop problems.
`in the Ifi-i'ayer resist process (Fig. 11), a thick organic layer is again used to partially
`planarize the surface”. Materials investigated for this layer have included conventiOnal positive
`optical photoresist, polyimide, and polysulfone. A thin layer of SiO2 (spin—on or PECVD} is
`then deposited to act as an etch mask for the bottom layer. An imaging resist layer is finally
`applied, and patterned in a conventional manner (e.g. near—UV exposure and wet development),
`To minimize effects from standing waves and reflections from the substrate, the lower layer is
`treated to increase its optical density (see the section on Resist Processing: Exposure). The Sit)
`and lower layer are dry etched anisotropically to precisely transfer the pattern from the 1111?1
`imaging layer into the thick lower layer. The main disadvantage of the tri-layer process is the
`added complexity that it requires.
`In GeeSe based bilayer processes, the high contrast and resolution advantages of Ge—Se
`chalcogenide glasses are exploited [see section on Inorganic Resists). These materials are used
`for the imaging layer of a bilayer structure. The bottom layer is again a thick polymer, such as
`A22400 resist. This process exhibits the highest resolution limit of the three MLR processes
`discussed, but is also the most complicated to develop. Since its resolution capability is
`potentially so small, however, it has been identified as a process that might compete favorably
`with x-ray or electron beam lithographyfl.
`
`Contrast Enhancement Layers
`
`An alternative technique to the multilayer resist processes for increasing the maximum
`resolution obtainable with projection aligners, uses a photobleachable top layer called a contrast
`enhancement layer (CEL) 4. The penalties incurred for obtaining the improved resolution are
`
`i— Chrome Mask
`Imaging Layer
`sro
`E eh Mzask
`
`'
`.................. ..
`
`FllE (oz) of Polymer
`+
`* *
`
`ayer u g u g . s n g g a n n n n u u u o o o .-
`
`- - . - u a a - n n s - n n a n o o .-
`
`Trl-Layer Structure
`
`
`
`.d)
`
`Schematic of the tri-layer processgl. Reprinted with permission of Solid State
`Fig. 11
`Technology, published by Technical Publishing, a company of Dun S: Bradstreet.
`
`Page 14 of 25
`
`Page 14 of 25
`
`

`

`LITHOGRAPHY I: OPTICAL RESIST MATERIALS AND PROCESS TECHNOLOGY 425
`
`i
`
`i
`it i iv
`
`
`
`
`
`
`V
`
`SPIN COAT
`
`PHOTORESIST
`
`SPIN cosr CEL
`
`EXPOSE PATTERN
`
`REMOVE CEL
`
`
`
`
`
`
`
`
`m DEVELOP RESIST
`Contrast-Enhancement Process
`a ,
`Fig. 12 (a) Photoresist process incorporating the CEL concept. Added CEL steps are outlined in
`boxes.
`(1)) SEMS (8000K) of identical microcircuits produced with and without a CEL. Courtesy of
`the General Electric Research and Development Center.
`
`increased process complexity, longer exposure times, and longer development times. Note,
`however, that use of a CEL increases exposure time by ~3x, but stepper time by only ~15%.
`The CEL layer consists of a material that is spun onto a resist-coated wafer to a thickness of
`1000-30003 after soft-bake. This layer is normally opaque, but becomes transparent (bleached),
`when exposed to the light of the aligning tool. When the mask image from a projection printer
`is focused onto the wafer, regions of the opaque CEL layer that are struck by high-intensity light
`become transparent. This creates windows in the CEL through which light can shine and expose
`the resist. The unbleached CEL regions continue to absorb the relatively weak diffracted light.
`Since the CEL is in direct contact with the resist, it acts much like a thin mask used in contact
`printing. As discussed in Chap. 13, contact printers have higher resolution capabilities than
`Projection printers.
`In addition, because the CEL is applied as a relatively thin film, it has an
`inherently high resolution capability. As such, use of a CEL layer allows the advantages of
`projection printing to be exploited, together with the benefits, but without the limitations of
`Contact printing.
`In addition, unlike the PCM process, no interface layer problems are reported
`With CEL processes. The name is derived from the fact that the presence of the CEL layer
`increases the contrast of illumination that effectively reaches the resist.
`Following exposure,
`the CEL layer is completely stripped prior to developing. This
`requires that an extra dispense head in a spray developer (see section on Resist Processing:
`Development) be used to spray on the stripping solution. A spin dry step is then performed
`before the normal development cycle is begun. The CEL stripping operation adds about 30
`Seconds to the development process.
`Linewidths of ~05 tun using commercially available optical photoresists and stepper
`projection systems have been achieved with the aid of a CEL compared to the 1 pin resolution
`limit without CEL. Figure 12 shows SEM photographs of 2 ttm wide lines in photoresist
`
`Page 15 of 25
`
`Page 15 of 25
`
`

`

`426
`
`SILICON PROCESSING FOR THE VLSI ERA
`
`patterned with and without use of a CEL layer, and demonstrates the improvement that use of a
`CEL may provide.
`
`Inorganic Photoresists
`
`The finite contrast, 7, of organic-based resists limits their resolution capability. In order to
`increase the resolution capabilty of a photoresist process, without having to increase the
`numerical aperture NA of the system, or decrease the wavelength, A, of the system source, a
`technique must be used to increase the resist contrast.
`It has been demonstrated that inorganic
`resist materials exhibit extremely high contrasts, and therefore high resolution capability
`(eg. 7 = 6.8 for inorganic resists, versus YE 2 for organic resists). Delineation of 0.4 tint lines
`and spaces using conventional optical
`lithography has been demonstrated by utilizing
`R. = 405 nm, a lens of NA = 0.35, and such an inorganic resist”.
`The first such materials were based on the Ge-Se, that We introduced in the tri-layer MLR
`process discussion“.
`In such resists, GexSeLx glasses are deposited as thin films by rf
`sputtering or evaporation. Next, a 1000}. layer of silver (Ag) is deposited by plating from an
`AgN03 solution onto the GexSeLx surface, by a dip into an aqueous solution of AgNO3,
`When this composite film is exposed to UV light (or electron radiation), the Ag diffuses into and
`dopes the Ge—Se matrix (Fig. 13). This renders the Ag-doped Ge-Se almost insoluble to alkaline
`solutions that would normally dissolve an amorphous Ge-Se film. Thus this process exhibits a
`negative resist type behavior. Note that although this mechanism implies that wet developing
`is used to create patterns in Ge-Se films, dry development in CF4 is also feasible.
`The resist also demonstrates a unique edge-sharpening behavior. That is, rapid lateral
`diffusion of the Ag during exposure (photodoping) takes place across the boundary between
`exposed and unexposed regions. The resulting Ag profile compensates for diffraction at the
`image edges, which leads to the sharp edges.
`Inorganic resist materials also exhibit other attractive features for VLSI lithographic
`applications, including the following: a) there is no swelling during development and the edges
`have anisotropic profiles; b) the material is resistant to oxygen plasmas and hence is compatible
`with dry etched bilayer MLR processes; 0) the materials possess a broad-band spectral response to
`all regions of the UV spectrum, while appearing opaque to light of all wavelengths up to 450 um
`(thereby eliminating standing waves on reflective substrates) and is transparent to visible light.
`2.25
`
`l
`
`l
`
`l
`
`l
`
`l
`
`l
`
`l
`
`l
`
`l
`
`2.00
`
`1.75
`
`1.50
`
`1.25"
`
`PHOTODOPED
`no cone.
`
`
`
`NORMALIZEDCONCENTRATION
`
`POSlTION
`
`mo
`
`c IN Agase
`
`0.25
`
`204.0
`170.0
`136.0