`ULSI Technology
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`EDITED BY
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`C. Y. Chang
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`Chair Professor: College of Electrical Engineering and Computer Science
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`National Chico Tang University
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`Director: National Nam; Device Laboratories
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`Hxinchu, flszan, ROC
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`S. M. Sze
`UMC Chair Professor
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`Department of Eiccrmnics Engineering
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`Director; Microelectronics and Information Systems Research Center
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`National Chiao Tung Uraiversily
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`Hsinchn, Taiwan, ROC
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`THE McGRAW-HILL COMPANIES, INC.
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`TSMC Exhibit 1031
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`Page 1 of 71
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`TSMC Exhibit 1031
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`2‘22
`McGraw-Ht'll
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`A Division of'f‘heMeGmw-Hill Companies
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`ULSI TECHNOLOGY
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`Copyright ©1996 by The McGraw—Hill Companies, Inc. All rights reserved. Printed in the United
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`Slates of America. Except as permitted under the United States Copyright Act of 1976. no part of
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`this publication may be reproduced or distributed in any form or by any means, or stored in a data
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`base or relrievel system. without the prior written permission of the publisher.
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`Acknowledgments begin on page 724 and appear on this page by reference.
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`This book is printed on acid-free paper.
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`234567890DOCDOC909876
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`iSBN 0-07-063062—3
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`'I'his book Was set in flutes Roman by Pnbiication. Services. Inc.
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`The editors were Lynn Cox and John M. Morrirs.‘
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`the production supervisor was Denise L. Pnryear:
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`The cover was designed by Farengn Design Gmr-tp.
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`Project supervision was done by Publication Services, inc.
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`R. R. Donneliey 0‘}. Sons Company was printer and binder:
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`Cover photo: Electron micrograph of contact holes filled with CVD tungsten plugs (see Chapter 8).
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`The diameter is 0.25 micron. Courtesy of the National Nam) Device Laboratories, Natiorm! Science
`Cmmcii. RC3. C.
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`Library of Congress CataIOg Card Number: 95-81366
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`Page 2 of 71
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`CONTENTS
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`__—-:——=-_‘_EF.r—§'—' mm
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`List of Contributors
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`Preface
`Introduction
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`Cleanroom Technology
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`H. P. Tseng and R. Jansen
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`1.1
`Introduction
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`1.2 Cleanroom Classification
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`1.3 Cleanroom Design Concept
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`1.4 Cleanroom Installation
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`1.5 Cleanroom Operations
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`1.6 Automation
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`1.7 Rel atcd Facility Systems
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`1.8 Summary and Future Trends
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`References
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`Problems
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`Wafer-Cleaning Technology
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`C. Y. Chang and T. S. Char)
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`2.1
`Introduction
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`2.2 Basic Concepts of Wafer Cleaning
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`2.3 Wet-Cleaning Technology
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`2.4 Dry-Cleaning Technology
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`2.5 Summary and Future Trends
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`References
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`Problems
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`xiii
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`105
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`Epitaxy
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`P. Wang
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`3.1
`Introduction
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`3.2 Fundamental Aspects of Epitaxy
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`3.3 Convantional Si Epitaxy
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`3.4 Low-Temperature Epitaxy of Si
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`3.5 Selective Epitaxial Growth of Si
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`3.6
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`3.7
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`Characterization of Epitaxial Films
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`Summary and Future Trends
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`References
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`Problems
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`Conventional and Rapid Thermal Processes
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`R. B. Fair
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`Introduction
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`4.4
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`Requirements for Thermal Processes
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`Rapid Thermal Processing
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`Summary and Future Trends
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`References
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`Problems
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`Deposition Processes
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`Dielectric and Polysilicon Film Deposition
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`5.1
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`5.2
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`Atmosplieric-Pressure Chemical—Vapor-Deposited
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`(APCVD) and Low-Pressure Chemical-Vapor-Deposited
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`(LPCVD) Silicon Oxides
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`LPCVD Silicon Nitride—S
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`LPCVD Polysilicon Films
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`Plasma—Assisted Depositiona
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`Other Deposition Methods
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`Applications of Deposited Polysilicon, Silicon Oxide,
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`and Silicon Nitride Films
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`5.3
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`Summary and Future Trends
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`References
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`Prob lems
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`Lithography
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`K. Nakamura
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`6.1
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`Optical Lithography
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`Electron Lithography
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`XnRay Lithography
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`Ion Lithography
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`6.6 Summary and Future Trends
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`References
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`7 Etching
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`7.]
`Introduction
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`7.2 Low-Pressure Gas Discharge
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`7.3 Etch Mechanisms. Selectivity, and Profile Control
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`7.4 Reactive Plasma Etching Techniques and Equipment
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`7.5 Plasma Processing Processes
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`7.6 Diagnostics, End Point Control, and Damage
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`7.7 Wet Chemical Etching
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`7.8 Summary and Future Trends
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`References
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`Contents
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`ix
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`Problems
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`8 Metallization
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`Introduction
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`R. Lin
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`8.2 Metal Deposition Techniques
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`8.3 Silicide Process
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`8.4 CVD Tungsten Plug and Other Plug Processes
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`8.5 Multilevel Metallization
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`8.6 Metallizalion Reliability
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`8.7 Summary and Future Trends
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`References
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`Problems
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`9 Process Integration
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`C. Y. Lu. and W. K Lee
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`9.1
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`9.2 Basic Process Modules and Device Considerations for
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`9.3 CMOS Technology
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`9.4 Bipolar Technology
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`9.5 BiCMOS Technology
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`9.6 MOS Memory Technology
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`37]
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`x Contents
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`9.7 Process Integration Considerations in ULSI Fabrication
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`'l'eehnology
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`9.8 Summary and Future Trends
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`References
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`Problems
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`Assembly and Packaging
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`TI ’fitchikmm
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`10.1
`Introduction
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`111.2 Package '1‘ypcs
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`111.3 ULSI Assembly Technologies
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`111.4 Package Fabrication Technologies
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`10.5 Package Design Considerations
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`10.6 Special Package Considerations
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`111.“? Other ULSI Packages
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`10.3 Summary and Future Trends
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`References
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`Problems
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`10
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`11
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`Wafer Fab Manufacturing ’l‘cehnology
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`T: F. Show and I“: C. Wang
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`11.1 What Is Manufacturing?
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`11.2 Wafer Fab Manufacturing Considerations
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`11.3 Manufucmring Start—Up Technology
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`11.4 Volume Ramp Up Considerations
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`11.5 Continuous Improvement
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`11.1- Summary’ and l1‘uture 'I‘ronds
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`References
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`5 I!)
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`S3}
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`56‘)
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`Problems
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`[2. Reliability
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`J. '1: Yup
`12.1
`introduction
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`12.2 lint Carrier injection
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`12.3 Electroniigration
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`12.4 Stress Migration
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`12.5 Oxide Breakdown
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`12.6 Effect of Scaling on Device Reliability
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`Page 6 0f 71
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`Page 6 of 71
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`Contents
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`xi
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`12.7 Relations between DC and AC Lifetimes
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`12.8 Some Recent ULSI Reliability Concerns
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`12.9 Mathematics of Failure Distribution
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`12.10 Summary and Future Trends
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`References
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`Problems
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`Appendixes
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`A. Properties of Si at 300 K
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`B. List of Symbols
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`C.
`International System of Units
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`D. Physical Constants
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`Index
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`Page 7 0f 71
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`Page 7 of 71
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`INTRODUCTION
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`GROWTH OF THE INDUSTRY
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`The'United States has the largest electronics industry in the world, with a global
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`market Shade of over 40%. Since 1958, the beginning of the integratedseircuit [1(3)
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`era, the factory sales of electronic products have increased by about thirty times [see
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`Fig. Leurve (o)"2]. Electronics sales. which were $303 billion in 1993, are projected
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`to increase at an average annual rate of 8.5% and reach a half-trillion-dollar level by
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`the year 2000. In the same period, the [C market itself has increased at an even
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`higher rate [see Fig. 1, curve (mule 'IC sales in the United States were $28 billion
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`in 1993 and are expected to grow by 13% annually. reaching $65 billion by the
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`year 9.000. The main irnpetuses for such phenomenal market growth are the intrinsic
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`pcrvasiveness of electronic products and the continued technological breakthroughs
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`in integrated Circuits.
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`The world markets of electronics and semiconductor industries will grow at
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`comparable rates. Figure 2 shows the 1993 world electronics industry with a global
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`sales volume of $679.7 billion. Also shown are the market shares of the six major
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`electronics applications: computer and peripherals equipment at 32.3%, consumer
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`electronics at 2] 2%, telecommunication equipment. at 16.5%, industrial electronics
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`at 14.3%. defense and space at 11.5%, and transportation at 4.2%. By the year 2000,
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`the world electronics industry is projected to reach $1200 billion. which will surpass
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`the automobile. chemical, and steel industries in sales volume.
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`Figure 3 shows the 1993 world semiconductor industry, with total sales of $85.6
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`billion. Only 14% is related to optoelectronics and discrete semiconductor devices.
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`[C sales constitute 86% of the total volume, with the largest segment being memory
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`[C3, followed by microprocessor and microcontroller units, logic ICs, and analog le.
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`in 2000, the semiconductor industry is projected to reach $200 billion, with over
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`$170 billion in integrated circuits.
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`Figure 4 shows the market shares of the three major 1C groups: MOS FE’I', bipo-
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`lar transistor, and IQ; made from III—V compound semiconductors.-1 At the begin-
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`ning of the 1C era, the 1C market was broadly based on bipolar transistors. However,
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`because of the advantages in device miniaturization, low power consumption. and
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`high yield, sales volume of MOS-based [Cs has increased steadily and in 1993
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`amounted to 75% of the total 10 market. By the year 2000, MOS le will capture. the
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`largest n-rarket share (88%) of all ICs sold. This book, therefore, emphasizes MOS—
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`l‘eiated ULSl technology.
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`""Therc were only two years in which [he growths were negative: in 1074. due to the Middle Fast oil
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`embargo. and in 1085. due to overproduction ol' personal computers.
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`xvii
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`(a) Factory sales
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`of electronics
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`(1)) Integrated
`circuits
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`xviii
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`Introduction
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`l 0000
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`[00 10
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`Invention
`of
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`transistor
`i
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`0.0l
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`1930
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`1950
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`1960
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`1980
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`] 990
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`2000
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`1970
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`Year
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`FIGURE 1
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`(a) Factory sales of electronics in the United States for the 64 years between
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`1930 and 1993 and projected to 2000. (b) Integrated circuit market in the
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`United States for 32 years between 1962 and 1993 and projected to 2000.
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`(After Refs. 1' and 2.)
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`DEVICE MINIATURIZATION
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`Figure 5, curve (a), shows the rapid growth in the number of components per MOS
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`inemory chip.“-S Note that the MOS 1C complexity has advanced from small-scale
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`integration (881),
`to medium-scale integration (M31), to large-scale integration
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`(LSI), to very-large-scale integration (VLSI), and finally to ultralarge-seale integra-
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`tion (ULSI), which has 107 or more components per chip. We note that since 1975
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`the growth has been maintained at a rate of about 40% annually: in other words, the
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`Page 9 of 71
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`Transportation
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`Introduction
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`xix
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`l 5%
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`Computers s, peripherals
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`equipment 32.3%
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`industrial electronics
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`I4.3%
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`Telecommunication
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`equipment 16.5%
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` Defense, space I
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`Consumer electronics 2 | 2%
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`FIGURE 2
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`l993 world electronics industry. (After Dnmqnesr. 1994.)
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`number of components has doubled every two years. At this rate, over 100 million
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`components per chip will be available before the year 2000; in the earl y 2] st century
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`We will move into the gigabit range, with IC chips having more than one billion
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`componentsfi'7 Also shown in Fig. 5 is the growth of the number of components for
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`bipolar, MHSFET, and MODFET ICs. They are about two orders of magnitude lower
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`in complexity compared with MOS-based ICs.
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`The most important factor in achieving the ULSI complexity is the continued
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`l‘eduction of the minimum device-feature length [see Fig. 6, curve (0)]. Since 1960,
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`the annual rate of reduction has been 13%, which corresponds to a reduction by a
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`factor of two every six years. At this rate, the minimum feature length will shrink
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`from its present length ot'0.5 pm to 0.2 not in the year 2000. The junction depth of
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`the source and drain junctions, and the gate oxide thickness are also being reduced
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`at a similar rate as shown in curves (b) and (c) of Fig. 6, respectively.
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`The reduction of the device feature length and related dimensions has resulted
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`in reduced overall device size and unit price per function. Figure 7 shows the relative
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`price and size reductions.8 In the past fifty years, prices have gone down by 100
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`Million times, and the size has been reduced by a factor of one billion. By 2000 the
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`Price per hit is expected to be less than 0.1 millicent fora 64-megabit memory chip.
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`Similar price reductions are expected for logic ICs. Additional benefits from device
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`Page 10 of 71
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`xx
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`Introduction
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`Opluclcctronics
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`Memory [C
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`28 5%
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`[8.796-
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`Logic 1C
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`MPU, CPU
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`24.5%
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`FIGURE 3
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`1993 world semiconductor industry. (Afler Dataquesu 994.)
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`III—V
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`World IC market (1980—2000). (After Zdebef, R43.)
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`Introduction
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`and
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`UL51
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`7
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`mm
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`10“
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`10“
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`3g
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`1070
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`t9so
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`Year
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`1990
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`2000
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`-
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`2010
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`FIGURE 5
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`(H!) Exponential growth of the number of components per MOS 1C chip. (After
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`ii’i'oomr Ref. 4. and Myers. Ref. 5. ) (b). (c). and (1:!) Components per chip versus
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`year for bipolar. MESFET. and MODFET ICs. respectively.
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`miniaturization include improvement of device speed (which varies inversely with
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`lhe device feature length) and reduction of power consumption (which varies ap-
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`Droximutely with the square of the feature length). Higher speeds lead to expanded
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`1C functional throughput rates, so that future ICs can perform data processing. nu-
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`merical computation. and signal conditioning at 100 and higher gigabit-per-second
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`rates.9 Reduced power consumption results in lowering the energy required for each
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`SWitehing operation- Since 1960 the required energy, called the power-delay prod-
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`uct. has decreased by six orders of magnitude.m
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`ORGANIZATION OF THE BOOK
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`Figure 8 shows how the 12 chapters of this book are organized. Chapter 1 considers
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`cleilllt‘ooin technology. The continued miniaturization in ULSI devices implies more
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`ss ii
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`Introduction
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`50
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`Ill “,5:
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`1
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`on
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`uni
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`lb) Junction
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`depth
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`(e) Gale oxide
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`thickness
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`(«13% reduction per year)
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`“1th
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`moon
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`molt
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`' 40A
`2000
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`
`0.004
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`
`I960
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`l9'i'0
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`I980
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`Year
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`I 990
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`FIGURE 6
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`Exponential decrease of (a) minimum feature length. to} Junction depth. and
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`(c) gate oxide thickness of MOSFbT.
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`stringent requirements with respect to contamination control. Without an uluaclean
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`processing environment, ULSI circuits simply cannot be realized. ”
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`ULSl technology is synonymous with silicon ULSI technology. The unique
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`combination of silicon‘s adequate bandgap. stable oxide. and abundance in nature
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`ensures that iii the foreseeable future no other semiconductor will seriously chal-
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`lenge its preeminent position in ULSI applications. Some important properties of
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`silicon are listed in Appendix A.
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`Once the silicon wafers are in the cleanroom. we enter into the wafer- processing
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`sequence, described in Chapters 2 through 8 and depicted in the wafer-shaped cen-
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`tral circle of Fig. 8. Each of these chapters considers a specific process step. Of
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`course. many processing steps are repeated many times in IC fabricat ion; for exam-
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`ple. lithography and etching steps may be repeated Ill to 20 times. In ULSI tech-
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`nology the wafer-cleaning technology is as important as the clennroom technology.
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`Without a contamination-free wafer surface. the le will suffer front low yield and
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`poor reliability. Because of limitations on the total length of the book. many clas-
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`sic topics. such as crystal growth. oxidation. diffusion. and ion implantation. are
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`only briefly mentioned. The reader may consult textbooks on VLSI teehno‘lOgy for
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`details.”
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`The individual processing steps described in Chapters 2 through 8 are com-
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`bined in Chapter 9 to form devices and integrated circuits. Chapter 9 considers the
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`fundamental building process modules and four important IC families: CMOS (com.
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`plementary MOSFET). bipolar le, BiCMOS (a combination of bipolar and CMOS).
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`Introduction
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`Eleclron tube —-|-
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`10-“
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`Relativevalue
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`Device size \
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`1 tr“
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`1U"°
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`1930
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`1940
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`1950
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`1950
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`1970
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`1930
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`1990
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`2000
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`Year
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`FIGURE 7
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`Price and size reduction of active electronic cempcnts. (After Strode, Rd 8.)
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`and MOS memory ICs. After the completely processed wafers are tested, these chips
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`that pass the tests are ready to be packaged. Chapter 10 describes the assembly and
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`packaging of U LSl chips. Chapter 11 considers the manufacturing technology, that
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`l81 the strategy and logistics to implement various technologies to produce ULSI
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`chips that meet customers’ specifications in a timely fashion and to generate ade-
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`quate return on investment for the IC manufacturer. Chapter 12 describes a multi-
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`tude of reliability issues related to ULSI processes. As device dimensions move to
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`lhe sub—half-micron and sub-quarter—micron regime, ULSI processing becomes more
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`automated, resulting in tighter control of all processing parameters. At every step of
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`Pl'Oduction, from wafer cleaning to device packaging, numerous requirements are
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`being imposed to improve the device performance and reliability.
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`To keep the notation simple in this book we sometimes found it necessary to use
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`a 331’mhol more than once, with different meanings. However, within each chapter a
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`Page 14 of 71
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`XXIV
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`A:.339.3335?«stutescfiz.
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`a“:£38wan—mania“EaafiEufiaa
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`#93m3..3nonmumznmuom.559."—
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`Introduction
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`xxv
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`symbol has only one meaning and is defined the first time it appears. Many symbols
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`do have the same or Similar meanings 901131361111)! throughout this book; they ate
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`summzu‘ized in Appendix Hf“
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`ULSl technology is presently moving at a rapid pace. The number of ULSI pub-
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`lications has doubled every year since 1990. the beginning of the ULSI era. Many
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`topics, such as lithograpl‘ty, rapid thermal processing, and metallization, are still 1m-
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`der intensive study. Their ultimate capabilities are not fully understood. The material
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`presented in this book is intended to serve as a foundation. The references listed at
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`the end of each chapter can supply more information.
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`REFERENCES
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`l.
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`12.
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`[994 Eileen-win: Market Data Book. Electronic industries Association, Wash—
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`ington, DC, 1994.
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`t 994 Annual Report ofb'ernieondnetnr Industry, Industrial Technology Research
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`Institute, Hsinchu, Taiwan. ROC, 1994.
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`1“. J. Zdebel, “Current Status ot'IIigh Performance Silicon Bipolar Technology,”
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`14rhAnmtnl IE‘EE Get/ts [C Sir-mp. Tech. Digest, 15 (1992).
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`. G. Moore, “VLSI, What Does the Future Hold," Electron Attst..42, 14 (1980).
`LII-L‘-
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`. W. Myers, “The Drive to the Year 21000," IEEE Micro, 11, 10 (1991).
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`(i. P. K. Chatterjce and G. B. [errant-re, “Gigabit Age Microelectronics and Their
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`Manufacture.” IEEE Trans. VLSI .S'y.s‘t.1, 7‘ (I993).
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`. K. Mori, H. Yamada, and S. Takizawa, “System on Chip Ago," Proceedings of
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`the Internt'trionnt Symposium on VLSI technology. Systems, and Applications,
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`1115 ( 1993).
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`. K. Shoda, “Home Electronics in the 1990s,” Proceedings oj'the International
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`Sytnposimn on VLSI technology. Systems, ctnd/ipplfcations. 1(1991).
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`H. Korniya, M. Yoshimoto, and H. Ishikura, “Future Technological and Eco-
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`nontic Prospects for VLSI,” [EICE Trans. Electron. E76-C, 1555 (1993).
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`R. W. Keyes. “Limitations of Smaii Devices and Large Systems,” in N. 0. Bio-
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`spruch, Ecl., VLSI Electronics, Academic, New York, 1981, Vol. 1, p. 186.
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`11. T. Ohmi, “ULSI Reliability through Ultraelean Processing," Prue. IEEE, 81,
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`7.16 (1993).
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`For example. 5. M. 820, ECL. VLSI 7ecnnoiogy, 2nd Ed, McGraw-Hilt, New
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`York, I988.
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`‘-—.____.__—
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`*Alsn included are the Internaholml System ot‘ Units (Appendix C) and Physical Constants [Ap-
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`pendix D),
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`Page 16 of 71
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`Page 16 of 71
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`CHAPTER ti
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`ithography
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`K. Nakamura
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`6.1
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`INTRODUCTION
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`Lithography is a kind of art made by impressing, in turn, several flat embossed slabs,
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`each covered with greasy ink of a particular color, onto a piece of paper. The unions
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`colors or levels must be accurately aligned with respect to one another within some
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`registration tolerance. Many “originals" can be made from the same slabs as long as
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`the quality remains adequately high.
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`Several methods can be used to make ULSI circuit patterns on wafers, as shown
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`in Fig. la. The most common process is to make the master photomask using an elec-
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`tron beam exposure system and replicating its image by optical printers, as shown in
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`Fig. 1b. The exposing radiation is transmitted through the “clear" part of a mask. The
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`opaque part of the circuit pattern blocks some of the radiation. The resist, which is
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`sensitive to the radiation and has resistance to the etching, is coated on the wafer sur-
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`face. The mask is aligned within the required tolerance on the wafer; then radiation
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`is applied through the mask, the resist image is developed, and the layer underneath
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`the resist is etched.
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`Therefore, lithography for integrated circuit manufacturing is analogous to the
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`lithography of the art world. The slabs correspond to masks for the various circuit
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`levels. The press con'esponds to the exposure system, which not only exposes each
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`level but also aligns it to a completed level. The ink may be compared to either the
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`exposing radiation or the radiation-sensitive resist; the paper can represent the wafer
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`into which the pattern will be etched, using the resist as a stencil.
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`Lithography is the key technology in semiconductor manufacturing, because
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`it is used repeatedly in a process sequence that depends on the device design. It
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`determines the device dimensions, which affect not only the device’s quality but
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`also its product amount and manufacturing cost.
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`270
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`scam?“mammogxmIV
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`gammanofiurufl
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`wIEamiv‘url‘r
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`35383.0I.wEa-IIIIIIIII-
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`3V3
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`”.32
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`:mauu$5
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`EufionomEgan—
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`.mmuooumgougingWEEDQ:.515Ho.“mmuocaomamfimofifi3.nonammflonumEnsumofi:02quuHEDGE
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`Page 18 of 71
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`271
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`272 ULSI Technology
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`6.2
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`OPTICAL LITHOGRAPI‘IY
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`Optical lithography comprises the formation of images with visible or ultraviojet
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`radiation in a photoresist using proximity or projection printing. Two methods are
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`available to make masks for optical lithography: electron beam exposure and lager
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`beam scanning. These are described in the next section. In the 1970s, the major tech-
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`nology was the combination of a negative resist and proximity printing. At progem
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`the most common method is the combination of a positive resist attd a stepper. How-
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`ever, proximity printing is still used because of its convenience and low cost.
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`Table 1 lists examples of commercially available optical printers" designed to
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`manufacture ULSl circuits. These machines are Classified into three groups: prob
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`imity. reflective projection, and refractive projection. The key parameters such as
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`numerical aperture (NA), depth of focus (DOF). resolution (usable linewidth), OVel-_
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`lay accuracy, and throughput are also listed.
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`The most advanced ULSl has a minimum feature size of 0.3 pm to 0.4 ptm1
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`which has been reported by several organizations in 64—Mbit dynamic random access
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`memories (DRAMs). It is believed that the linewidth limit of optical lithography lies
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`near 0.2 um using phase-shifting masks combined with a high numerical aperture
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`projector and a short—wavelength light source. The performances of the machines
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`listed in Table 1 are very close to the resolution limit of optical lithography.
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`6.2.1 Contact and Proximity Printing
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`Contact and proximity printings are relatively simple because they do not have any
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`means of image formation between masks and wafers. A typical contact or proxim-
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`ity mask aligner consists of a light source, a condenser, a filter. a mirror, a shutter,
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`the wafer stage, and the alignment microscope. In contact printing, a photomask is
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`pressed against the resist-covered wafer, with pressures typically in the range of 0.05
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`arm to 0.3 atm, and is exposed by light with a wavelength near 400 nm. Very high
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`resolution of less than 0.5 um iinewidth is possible, but because of spatial nonuni-
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`formity of the contact, resolution may vary considerably across the wafer. To provide
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`better contact over the whole wafer, a thin (0.2 mm) flexible mask has been used;
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`02-pin space patterns have been formed by using 3—ttm—thick PMMA (poly—methyl
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`methacrylatc) resist and 200 to 260 urn radiation.2 Quartz or A1203 mask substrates
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`must be used to pass these shorter wavelengths, since the usual borosilieate glass
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`strongly absorbs wavelengths less than 300 nm.
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`Contact printing produces defects in both the mask and the wafer while the two
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`are in contact and as they are separated from each other, so that the mask, whether
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`thick or thin. may have to b