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`APPLE 1014
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`System
`Architecture,
`Fourth Edition
`
`MINDSHARE, INC.
`
`Don Anderson
`
`Tom Shanley
`
`A
`VV
`
`ADDISON-WESLEY
`
`An imprint of Addison Wesley Longman, Inc.
`
`Reading, Massachusetts ° Menlo Park, California ° New York
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`2
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`

`
`Many of the designations used by manufacturers and sellers to distinguish their prod-
`ucts are claimed as trademarks. Where those designators appear in this book, and
`Addison-Wesley was aware of the trademark claim, the designations have been printed
`in initial capital letters or all capital letters.
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`The authors and publisher have taken care in preparation of this book, but make no
`expressed or implied warranty of any kind and assume no responsibility for errors or
`omissions. No liability is assumed for incidental or consequential damages in connec-
`tion with or arising out of the use of the information or programs contained herein.
`The publisher offers discounts on this book when ordered in quantity for special sales.
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`For more information, please contact:
`Corporate, Government and Special Sales Group
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`Library of Congress Cataloging-in-Publication Data is available.
`
`ISBN: 0-201-30974-2
`
`Copyright ©1999 by MindShare, Inc.
`All rights reserved. No part of this publication may be reproduced, stored in a retrieval
`system, or transmitted, in any form or by any means, electronic, mechanical, photocopy-
`ing, recording, or otherwise, without the prior written permission of the publisher.
`Printed in the United States of America. Published simultaneously in Canada.
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`Sponsoring Editor: Karen Gettman
`Production Coordinator: Iacquelyn Young
`Cover Designer: Simone R. Payment
`Set in 10 point Palatino by MindShare, Inc.
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`1 2 3 4 5 6 7 8 9-MA-0302010099
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`First Printing, May 1999
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`:-
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`s
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`B
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`Contents
`
`About This Book
`The MindShare Architecture Series
`
`Organiiation of This Book .....................
`Designation of Specification Changes.
`Cautionary Note .......................................
`Who this Book is For .......... ..
`
`Prerequisite Knowledge ......
`Object Size Designations ....................................................................................................... .. 4
`Documentation Conventions .............................., .................................................................... 5
`Hex Notation .............................................................................................................
`....... .. 5
`
`Binary Notation .................................................................................................................. .. 5
`Decimal Notation ............................................................................................... ., .............. .. 5
`Signal Name Representation ............................... ............................................................. .. 5
`Identification of Bit Fields (logical groups of bits or signals) ...................................... .. 6
`We Want Your Feedback ............................................................................
`.......................... .;. 6
`
`Chapter 1: Intro To PCI
`PCI Bus History...;..
`PCI Bus Features.....
`PCI Device vs. Function ..
`
`4
`
`Specifications Book is Based On..
`Obtaining PCI Bus Specification(s) ...........................................................v.-.......................... 13
`
`Chapter 2: Intro to PCI Bus Operation
`Burst Transfer .........;................................................................................................................. 15
`
`Initiator, Target and Agents .......................................................................................§..'......... 17
`Single- Vs. Multi-Function PCI Devices ............................................................................. 17
`PCI Bus Clock ........................................................................................................................... 17
`Address Phase ........................................................................................................................... 18
`
`Claiming the Transaction
`Data Phase(s) . .. ... ........... ... ... .. .
`... .. ........ .. .. .. ..
`Transaction Duration .....................................
`Transaction Completion and Return of Bus to Idle State
`Response to Illegal Behavior ........
`-
`'
`”Green” Machine .......................... ..
`
`.......................................................................... 19
`..... 19
`..... 20
`20
`20
`21
`
`. .
`
`Chapter 3: Intro to Reflected-Wave Switching
`Each Trace Is a Transmission Line ........................................................................................ 23
`
`Old Method: Incident-Wave Switching............................................................................... 24
`
`4
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`
` Intro To PCI
`
`,_/
`
`This Chapter
`
`This chapter provides a brief history of PCI, introduces its major feature set, the
`concept of a PCI device versus a PCI function, and identifies the specifications
`that this book is based upon.
`
`The Next Chapter
`
`The next chapter provides an introduction to the PCI -transfer mechanism,
`including a definition of the following basic concepts: burst transfers, the initia-
`tor, targets, agents, single and multi-function devices, the PCI bus clock, the
`address phase, claiming the transaction, the data phase, transaction completion
`and the return of the bus to the idle state. It defines how a device must respond
`if the device that it is transferring data with exhibits a protocol violation. Finally,
`it introduces the "green" nature of PCI-—power conservation is stressed in the
`spec.
`
`PCI Bus History
`
`Intel made the decision not to back the VESA VL standard because the emerg-
`ing standard did not take a sufficiently long-term approach towards the prob-
`lems presented at that time and those to be faced in the coming five years. In
`addition, the VL bus had very limited support for burst transfers, thereby limit-
`ing the achievable throughput.
`'
`v
`
`Intel defined the PCI bus to ensure that the marketplace would not become
`crowded with various permutations of ‘local bus architectures peculiar to a spe-
`cific processor bus. The first release of the specification, version 1.0, became
`available on 6/22/92. Revision 2.0 became available in April of 1993. Revision
`2.1 was issued in Q1 of 1995. The latest version, 2.2, was completed on Decem-
`ber 18, 1998, and became available in February of 1999.
`
`5
`
`

`
`PCI System Architecture
`
`PCI Bus Features
`
`PCI stands for Peripheral Component Interconnect. The PCI bus can be popu-
`lated with adapters requiring fast accesses to each other and/ or system mem-
`ory and that can be accessed by the processor at speeds approaching that of the
`processor ’s full native bus speed. It is very important to note that all read and
`write transfers over the PCI bus can be performed as burst transfers. The length
`of the burst is determined by the bus master. The target is given the start
`address and the transaction typeat the start of the transaction, but is not told
`the transfer length. As the master becomes ready to transfer each data item, it
`informs the target whether or not it's the last one. The transaction completes
`when the final data item has been transferred.
`
`Figure 1-1 on page 11 illustrates the basic relationship of the PCI, expansion,
`processor and memory buses.
`
`0
`
`The host/PCI bridge, frequently referred to as the North Bridge, connects
`the host processor bus to the root PCI bus.
`The ‘PCI-to-ISA bridge, frequently referred to as the South Bridge, connects
`the root PCI bus to the ISA (or EISA) bus. The South Bridge also typically
`incorporates the Interrupt Controller, IDE Controller, USB Host Controller,
`and the DMA Controller. The North and South Bridges comprise the
`chipset.
`One or more PCI-to-PCI bridges (not shown) may be embedded on the root
`PCI bus, or may reside on a PCI add’-in card.
`In addition, a chipset may support more than one North Bridge (not
`shown).
`
`Table 1-1: Major PCI Features
`
`_ C
`
`omponents designed for the PCI bus are PCI-specific, not
`processor—specific, thereby isolating device design from pro-
`cessor upgrade treadmill.
`'
`
`Processor Indepen-
`dence
`
`Support for up to
`approximately 80
`PCI functions per
`PCI bus
`
`A typical PCI bus implementation supports approximately ten
`electrical loads, and each device presents a load to the bus.
`Each device, in turn, may contain up to eight PCI functions.
`/
`.
`
`6
`
`

`
`Chapter 1: Intro To PCI
`
`Table 1-1: Major PCI Features (Continued)
`
`4, Support for up to
`l 256 PCI buses
`
`Low-power con-
`sumption
`
`A major design goal of the PCI specification is the creation of a
`system design that draws as little current as possible.
`
`Bursts can be per-
`I formed on all read
`" and write transfers
`
`A 32-bit PCI bus supports a 132Mbytes per second peak trans-
`fer rate for both read and write transfers, and a 264Mbytes per
`second peak transfer rate for 64-bit PCI transfers. Transfer
`rates of up to 528Mbytes per second are achievable on a 64-bit,
`66MHz PCI bus.
`
`Bus speed
`
`Revision 2.0 spec supported PCI bus speeds up to 33MHz.
`Revision 2.1 adds support for 66MHz bus operation.
`
`64-bit bus width
`
`Full definition of a 64-bit extension. V
`
`Access time
`
`As fast as 60ns (at a bus speed of 333MHz when an initiator
`parked on the PCI bus is writing to a PCI target).
`
`Concurrent bus
`operation
`
`Bridges support full bus concurrency with processor bus, PCI
`bus (or buses), and the expansion bus simultaneously in use.
`
`Bus master support
`
`Full support of PCI bus masters allows peer-to-peer PCI bus
`access, as well as access to main memory and expansion bus
`devices through PCI-to—PCI and expansion bus bridges. In
`addition, a PCI master can access a target that resides on
`another PCI bus lower in the bus hierarchy.
`
`Hidden bus arbitra- Arbitration for the PCI bus can take place while another bus
`tion
`master is performing a transfer on the PCI bus.
`.
`
`Low—pin count
`
`Transaction integ-
`rity check
`
`Three address
`spaces
`
`Economical use of bus signals allows implementation of a
`functional PCI target with 47 pins and an initiator with 49
`pins.
`’
`‘
`
`Parity checking on the _address, command and data.
`
`Memory, 1/ O and configuration address space.
`
`7
`
`

`
`PCI System Architecture
`
`Table 1-1: Major PCI Features (Continued)
`
`Auto-Configuration
`
`L—
`Software Transpar-
`ency
`
`sary to support automatic device detection and configuration.
`
`Software drivers utilize same command set and status defini-
`tion when communicating with PCI device or its expansion
`bus-orientedcousin.
`'
`
`Add-In Cards
`
`The specification includes a definition of PCI connectors and
`add—in cards.
`
`Add-In Card Size
`L_
`
`The specification defines three card sizes: long, short and vari-
`able-height short cards.
`
`8
`
`

`
`Chapter 1: Intro To PCI
`
`Figure 1-1: The PCI System
`
`(Vldeo Module IIF)
`
`9
`
`

`
`PCI System Architecture
`
`PCI Device vs. Function
`
`The typical‘PCI device consists of a complete peripheral adapter encapsulated
`within an IC package or integrated onto a PCI expansion card. Typical examples
`would be a network, display or SCSI adapter. During the initial period after the
`introduction of the PCI specification, many vendors chose to interface pre-exis-
`tent, non-PCI compliant devices to the PCI bus. This was easilyaccomplished
`using programmable logic arrays (PLAS). Figure 1-2 on page 12 illustrates ten
`PCI-compliant devices attached to the PCI bus on the system board. It should
`also be noted that each PCI-compliant package (embedded component or add-
`in card) may contain up to eight PCI functions. A function is a logical device.
`
`Figure 1-2: PCI Devices Attached to the PCI Bus
`
`/‘
`_
`Sideband
`Signals
`
`10
`
`

`
`I
`
`Chapter 1: Intro To PCI
`
`cifications Book is Based On
`
`This book is based on the documents indicated in Table 1-2 on page 13.
`
`l'C[—to-PCI Bridge Specification
`
`PCI System Design Guide
`
`PCI BIOS Specification
`
`PCI Bus Power Management I_nterface Specification
`
`PCI Hot-Plug Specification
`
`Obtaining PCI Bus Specification(s)
`
`The PCI bus specification, version 1.0, was developed by Intel Corporation. The
`specification is now managed by a consortium of industry partners known as
`the PCI Special Interest Group (SIG). MindShare, Inc. is a member of the SIG.
`The specifications are commercially available for purchase from the SIG. The
`latest revision of the specification (as of this printing) is 2.2. For information
`regarding the specifications and / or SIG membership, contact:
`
`PCI Special Interest Group
`2575 N.E. Kathryn #17
`Hillsboro, Oregon 97124
`1-800-433-5177 _(USA)
`503-693-6232 (International)
`503-693-8344 (Fax)
`pcisig@pcisig.com
`http: / /www.pcisig.com
`
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