EXHIBIT 1102
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`
`QUALCOMM INCORPORATED, GLOBALFOUNDRIES INC.,
`GLOBALFOUNDRIES U.S. INC., GLOBALFOUNDRIES DRESDEN
`MODULE ONE LLC & CO. KG, GLOBALFOUNDRIES DRESDEN MODULE
`TWO LLC & CO. KG
`Petitioner
`
`v.
`
`DSS Technology Management, Inc.
`Patent Owner
`
`U.S. Patent No. 6,784,552
`Claims 8-12
`____________________________________________
`
`
`
`DECLARATION OF RICHARD BLANCHARD, PH.D.
`ON BEHALF OF PETITIONER
`
`
`
`
`
`
`
`
`
`Qualcomm v. DSS
`Qualcomm, Exhibit 1102
`Page 1 of 87
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`

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`U.S. Patent No. 6,784,552
`Claims 8-12
`
`TABLE OF CONTENTS
`
`I.
`
`Relevant Law ................................................................................................. ..7
`
`A.
`
`B.
`
`C.
`
`Claim Construction.............................................................................. ..7
`
`Anticipation ......................................................................................... ..8
`
`Obviousness ......................................................................................... ..8
`
`II.
`
`III.
`
`Summary of Opinions .................................................................................. ..l1
`
`Brief Description of the Technology ........................................................... ..l1
`
`A.
`
`B.
`
`Basic Structure of Transistors ........................................................... ..l1
`
`Overview of Transistor Fabrication .................................................. ..l3
`
`1. Formation of Transistor Components ............................................... ..l3
`
`2. Etching to Create Contact Openings ................................................. ..l4
`
`IV. Overview of The ’552 Patent ....................................................................... ..l9
`
`A.
`
`B.
`
`C.
`
`The Alleged Problem in the Art ........................................................ ..l9
`
`The Alleged ’552 Patent Invention ................................................... ..22
`
`Prosecution History ........................................................................... ..24
`
`V.
`
`Overview of the Primary Prior Art References ........................................... ..27
`
`A.
`
`B.
`
`C.
`
`Summary of the Prior Art .................................................................. ..27
`
`Overview of Heath (Ex. 1103) .......................................................... ..28
`
`Overview of Dennison (Ex. 1104) .................................................... ..30
`
`VI.
`
`Claim Construction ...................................................................................... ..31
`
`VII. Level of Ordinary Skill In The Art .............................................................. ..37
`
`VIII. Specific Grounds for Petition ...................................................................... ..37
`
`A.
`
`Ground 1: Claims 8-12 are Anticipated by Heath............................ ..38
`
`1. Independent Claim 8 ......................................................................... ..38
`
`2. Claim 9: “The structure of claim 8, wherein the electrically insulative
`spacer has a surface portion without overlying etch stop material” ...... ..48
`
`3. Claim 10: “The structure of claim 9, wherein the electrically
`insulative spacer surface portion without overlying etch stop material
`comprises a surface portion most distant from the substrate”................ ..49
`
`1
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`Qualcomm,
`Exhibit 1 102
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`Page 2 of 87
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`Page 2 of 87
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`Qualcomm,
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`

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`U.S. Patent No. 6,784,552
`Claims 8-12
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`4. Claim 11: “The structure of claim 8, further comprising a second
`insulating layer on the etch stop layer and over the conductive layer”....50
`
`5. Claim 12: “The structure of claim 11, further comprising a second
`conductive material in the contact region” ............................................. ..5l
`
`B.
`
`Ground 2: Claims 8-12 Would Have Been Obvious Over Heath in
`
`View of Dennison .............................................................................. ..52
`
`1. Heath, in combination with Dennison, renders the claims obvious
`
`under an overly narrow construction of the “angle” limitation—e.g.,
`limiting it to a particular portion of the “side” of the insulative spacer-
`recited in claim 8 (element 8(g)) ............................................................ ..52
`
`2. Even if Heath is found to not disclose an etch stop material over the
`insulating spacer, Heath, in combination with Dennison, renders the
`claims obvious. ....................................................................................... ..64
`
`IX. Availability for Cross-Examination ............................................................ ..67
`
`X.
`
`Right to Supplement .................................................................................... ..68
`
`2
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`Qualcomm,
`Exhibit 1 102
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`Page 3 of 87
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`Page 3 of 87
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`Qualcomm,
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`

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`U.S. Patent No. 6,784,552
`Claims 8-12
`
`I, Richard Blanchard, declare as follows:
`
`1.
`
`2.
`
`My name is Richard Blanchard.
`
`My academic credentials include both a Bachelor of Science Degree
`
`in Electrical Engineering (BSEE) and a Master of Science Degree in Electrical
`
`Engineering (MSEE) from the Massachusetts Institute of Technology in 1968 and
`
`1970, respectively. I subsequently obtained a Ph.D. in Electrical Engineering in
`
`1982 from Stanford University
`
`3.
`
`I have worked or consulted for more than 40 years as an
`
`Electrical Engineer. My primary focus has been on the development,
`
`manufacture, operation, and use of devices and integrated circuits, the
`
`assembly of these devices and integrated circuits, products that use them,
`
`and their failures. My employment history following my graduation from
`
`MIT began at Fairchild Semiconductor in 1970. At Fairchild, my
`
`responsibilities included circuit and device design, process development, and
`
`product engineering in the Linear Integrated Circuits Department.
`
`4.
`
`In 1974, Ijoined Foothill College as an Associate Professor in
`
`the Engineering & Technology Division. My responsibilities included
`
`developing a program in Semiconductor Technology as well as teaching
`
`other courses in the division. While at Foothill College, I co-founded two
`
`companies, Cognition and Supertex, and later joined Supertex as a Vice
`
`3
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`Qualcomm,
`Exhibit 1 102
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`Page 4 of 87
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`Page 4 of 87
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`Qualcomm,
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`

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`U.S. Patent No. 6,784,552
`Claims 8-12
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`President in 1978. At Supertex, I designed and developed discrete DMOS
`
`(double-diffused metal oxide semiconductor) transistors, as well as
`
`integrated circuits that contained DMOS transistors. At Supertex, I also
`
`supervised the in-house assembly area, which included responsibility for the
`
`associated manufacturing processes.
`
`I left Suptertex to join Siliconix in
`
`1982, where I soon became Vice President of Engineering, with the
`
`responsibility for directing all of the company's product design and
`
`development. At Siliconix, I directed and contributed to the development of
`
`both discrete transistors and integrated circuits, including aspects of their
`
`assembly.
`
`5.
`
`In 1987, I joined IXYS Corporation as a Senior Vice President
`
`with the responsibility for organizing an integrated circuit department. At
`
`IXYS, I developed integrated circuits that contained DMOS devices or that
`
`interfaced to DMOS devices. My responsibilities included the design,
`
`assembly, and testing of these integrated circuits.
`
`6.
`
`These duties continued until 1991, when I left IXYS to set up
`
`Blanchard Associates, a consulting firm specializing in semiconductor
`
`technology, including intellectual property. Soon thereafter, I was invited to
`
`join Failure Analysis Associates, which I did in late 1991. At Failure
`
`4
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`Qualcomm,
`Exhibit 1 102
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`Page 5 of 87
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`Page 5 of 87
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`Qualcomm,
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`

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`U.S. Patent No. 6,784,552
`Claims 8-12
`
`Analysis Associates, I investigated failures in electrical and electronic
`
`systems in addition to performing design and development consulting.
`
`7.
`
`I left Failure Analysis in 1998 to join IP Managers, which later
`
`merged with Silicon Valley Expert Witness Group, now known as Thomson
`
`Reuters Expert Witness Services ("Thomson Reuters"). At Thomson Reuters,
`
`I work with companies on patent and trade secret matters.
`
`I also consult for
`
`a number of semiconductor companies, working with them to develop
`
`products and intellectual property, or assisting them in other technical areas
`
`through Blanchard Associates. Design and development projects that I have
`
`worked on range from the design and evaluation of specific components, to
`
`the selection of the technology appropriate for the fabrication of different
`
`subsystems of a system.
`
`8.
`
`I am a member of a number of professional societies, including
`
`the Institute of Electrical and Electronic Engineers, the International
`
`Microelectronics and Packaging Society, the American Vacuum Society, the
`
`Electronic Device Failure Analysis Society, and the Electrostatic Discharge
`
`Society.
`
`9.
`
`A copy of my curriculum vitae (including a list of all publications
`
`authored in the previous 10 years) is attached as Appendix A.
`
`5
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`Qualcomm,
`Exhibit 1 102
`
`Page 6 of 87
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`Page 6 of 87
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`Qualcomm,
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`

`
`U.S. Patent No. 6,784,552
`Claims 8-12
`
`10.
`
`I have reviewed the specification, claims and file history of U.S.
`
`Patent No. 6,784,552, as well as the petition for inter partes review of this patent:
`
`IPR20l6-00288, including the Declaration of Dr. John C. Bravman. I understand
`
`that the ’552 patent was filed on March 31, 2000 and claims priority to U.S. Patent
`
`Appl. No. 08/577,751 (now U.S. Patent No. 6,066,555) filed on December 22,
`
`1995.
`
`I understand that, for purposes of determining whether a publication will
`
`qualify as prior art, the earliest date that the ’5 52 patent could be entitled to is
`
`December 22, 1995. However, I further understand that the prior assignee claimed
`
`a priority date prior to April 21, 1995 during prosecution of the ’55 5 parent
`
`application.
`
`’555 Declaration Under 37 C.F.R. 1.131, Feb. 25, 1999 (Ex. 1108) at
`
`3. In any case, the cited references are prior art and invalidate the ’552 patent.
`
`11.
`
`I have reviewed the following patents and publications in preparing
`
`this declaration:
`
`0 U.S. Patent No. 4,686,000 (“Heath”) (Ex. 1103).
`
`0 U.S. Patent No. 5,338,700 (“Dennison”) (Ex. 1104).
`
`0
`
`J. Dulak et al., Etch mechanism in the reactive ion etching ofsilicon
`
`nitride, Journal of Vacuum Science & Technology A 9, 775 (1991)
`
`(“Dulak”) (Ex. 1107).
`
`12.
`
`I have reviewed the above patents and publications and any other
`
`publication cited in this declaration.
`
`6
`
`Qualcomm,
`Exhibit 1 102
`
`Page 7 of 87
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`Page 7 of 87
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`Qualcomm,
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`

`
`U.S. Patent No. 6,784,552
`Claims 8-12
`
`13.
`
`I have considered certain issues from the perspective of a person of
`
`ordinary skill in the art as described below at the time the ’552 patent application
`
`was filed. In my opinion, a person of ordinary skill in the art for the ’5 52 patent
`
`would have found the ’552 patent invalid.
`
`14.
`
`I have been retained by the Petitioner as an expert in the field of
`
`semiconductor device fabrication and design.
`
`I am working as an independent
`
`consultant in this matter and am being compensated at my normal consulting rate
`
`of $375 per hour for my time. My compensation is not dependent on and in no
`
`way affects the substance of my statements in this Declaration.
`
`15.
`
`I have no financial interest in the Petitioner.
`
`I similarly have no
`
`financial interest in the ’5 52 patent, and have had no contact with the named
`
`inventor of the ’552 patent.
`
`I. RELEVANT LAW
`
`16.
`
`I am not an attorney. For the purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law is as follows:
`
`A. Claim Construction
`
`17.
`
`I have been informed that claim construction is a matter of law and
`
`that the final claim construction will ultimately be determined by the Board. For
`
`the purposes of my analysis in this proceeding and with respect to the prior art, I
`
`7
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`Qualcomm,
`Exhibit 1 102
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`Page 8 of 87
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`Page 8 of 87
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`Qualcomm,
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`

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`U.S. Patent No. 6,784,552
`Claims 8-12
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`have been informed that I should apply what is known as the Phillips standard,
`
`rather than the broadest reasonable interpretation standard.
`
`18.
`
`Specifically, I have been informed and understand that the ’552
`
`patent has expired and the Phillips standard applies for the purposes of claim
`
`construction.
`
`I fiirther understand that the Phillips standard means that claim terms
`
`are given their plain and ordinary meaning as understood by a person of ordinary
`
`skill in the art at the time of the invention in light of the claim language and the
`
`patent specification.
`
`19.
`
`I have also been informed and understand that any claim term that
`
`lacks a definition in the specification is therefore given its plain and ordinary
`
`meaning as understood by one of ordinary skill in the art.
`
`B. Anticipation
`
`20.
`
`I have been informed and understand that a patent claim may be
`
`“anticipated” if each element of that claim is present either explicitly, implicitly, or
`
`inherently in a single prior art reference.
`
`I have also been informed that, to be an
`
`inherent disclosure, the prior art reference must necessarily disclose the limitation,
`
`and the fact that the reference might possibly practice or contain a claimed
`
`limitation is insufficient to establish that the reference inherently teaches the
`
`limitation.
`
`C. Obviousness
`
`8
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`Qualcomm,
`Exhibit 1 102
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`Page 9 of 87
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`Page 9 of 87
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`Qualcomm,
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`

`
`U.S. Patent No. 6,784,552
`Claims 8-12
`
`21.
`
`I have been informed and understand that a patent claim can be
`
`considered to have been obvious to a person of ordinary skill in the art at the time
`
`the application was filed. This means that, even if all of the requirements of a
`
`claim are not found in a single prior art reference, the claim is not patentable if the
`
`differences between the subject matter in the prior art and the subject matter in the
`
`claim would have been obvious to a person of ordinary skill in the art at the time
`
`the application was filed.
`
`22.
`
`I have been informed and understand that a determination of whether
`
`a claim would have been obvious should be based upon several factors, including,
`
`among others:
`
`0
`
`0
`
`the level of ordinary skill in the art at the time the application was filed;
`
`the scope and content of the prior art; and
`
`0 what differences, if any, existed between the claimed invention and the
`
`prior art.
`
`23.
`
`I have been informed and understand that the teachings of two or
`
`more references may be combined in the same way as disclosed in the claims, if
`
`such a combination would have been obvious to one having ordinary skill in the
`
`art. In determining whether a combination based on either a single reference or
`
`multiple references would have been obvious, it is appropriate to consider, among
`
`other factors:
`
`9
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`Exhibit 1 102
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`Page 10 of 87
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`U.S. Patent No. 6,784,552
`Claims 8-12
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`0 whether the teachings of the prior art references disclose known concepts
`
`combined in familiar ways, which, when combined, would yield
`
`predictable results;
`
`0 whether a person of ordinary skill in the art could implement a
`
`predictable variation, and would see the benefit of doing so;
`
`0 whether the claimed elements represent one of a limited number of
`
`known design choices, and would have a reasonable expectation of
`
`success by those skilled in the art;
`
`0 whether a person of ordinary skill would have recognized a reason to
`
`combine known elements in the manner described in the claim;
`
`0 whether there is some teaching or suggestion in the prior art to make the
`
`modification or combination of elements claimed in the patent; and
`
`0 whether the innovation applies a known technique that had been used to
`
`improve a similar device or method in a similar way.
`
`24.
`
`I understand that one of ordinary skill in the art has ordinary
`
`creativity, and is not an automaton.
`
`25.
`
`I understand that in considering obviousness, it is important not to
`
`determine obviousness using the benefit of hindsight derived from the patent being
`
`considered.
`
`10
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`Qualcomm,
`Exhibit 1 102
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`Page ll of 87
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`Page 11 of 87
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`Qualcomm,
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`

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`U.S. Patent No. 6,784,552
`Claims 8-12
`
`II. SUMMARY OF OPINIONS
`
`26.
`
`It is my opinion that every limitation of the structures described in
`
`claims 8 through 12 of the ’552 patent are disclosed by the prior art, and are
`
`anticipated and/or rendered obvious by the prior art.
`
`The following discussion and analysis is substantially the same as that of Dr.
`
`John C. Bravman in IPR20l6-00288, supplemented with additional analysis and
`
`comments provided throughout this declaration.
`
`III. BRIEF DESCRIPTION OF THE TECHNOLOGY
`
`A. Basic Structure of Transistors
`
`27.
`
`The ’552 patent relates to the field of semiconductor integrated circuit
`
`manufacturing. Semiconductor integrated circuits, such as microprocessors and
`
`computer memory, are typically made up of hundreds of millions (and in some
`
`cases billions) of microscopic structures called transistors. Transistors act as
`
`microscopic switches that turn on and off at extraordinarily high rates to enable
`
`aggregations of transistors (and other components) to process data.
`
`28. As shown in the figure below, transistors typically include three
`
`primary “electrodes” or “terminals”—a gate, a source, and a drain—embedded in
`
`or on a substrate and surrounded by dielectric and other materials:
`
`1 1
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`Qualcomm,
`Exhibit 1102
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`Page 12 of 87
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`Page 12 of 87
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`Qualcomm,
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`

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`U.S. Patent No. 6,784,552
`
`Claims 8-12
`
`
`
`29.
`
`The source and drain regions (also referred to as “diffusion regions”)
`
`are transistor components that emit (source) and receive (drain) current/carriers
`
`when the transistor is “on.” The gate typically sits between the source and drain
`
`and is a terminal that can have a Voltage applied to it that in turn causes a current to
`
`flow between the source and drain.
`
`30.
`
`The gate, source and drain of a transistor typically need to be
`
`connected to other components to form an electrical circuit. The ’552 patent refers
`
`to the structures used to make these connections as “contacts.” Contacts consist of
`
`one or more conducting materials (e.g., a metal) that allow current to flow between
`
`transistor components. In many cases, it is important to maintain electrical
`
`isolation between contacts and other nearby components (such as a gate electrode)
`
`so that current that is supposed to flow to other parts of the circuit does not instead
`
`flow to these nearby components (e.g. , the gate). As described in more detail
`
`below, structures called sidewall spacers can be formed between the contact and
`
`the nearby components to maintain this electrical isolation.
`
`12
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`Qualcomm,
`Exhibit 1 102
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`Page 13 of 87
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`Page 13 of 87
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`Qualcomm,
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`

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`U.S. Patent No. 6,784,552
`
`Claims 8-12
`
`B. Overview of Transistor Fabrication
`
`1. Formation of Transistor Components
`
`31.
`
`Transistor fabrication typically starts with a silicon substrate. In
`
`typical planar transistors, source and drain regions (“diffusion regions”) are created
`
`by implanting regions of the substrate with ions (charged atomic particles) of
`
`different materials—called “dopants” or “impurities”. (Once implanted the ions
`
`become neutral atoms.) This process—referred to as “doping” because it dopes the
`
`silicon substrate with atomic particles that have additional charge carriers—is
`
`shown below:
`
`
`
`A mask can be used for directing the charged particles to specific locations on the
`
`substrate.
`
`32.
`
`Structures can then be formed above the substrate by depositing layers
`
`of other materials onto the substrate. A gate electrode, for example, is formed by
`
`first growing or depositing a “gate oxide” (an insulator) on the substrate followed
`
`by depositing a conductive material (metal or polysilicon) on top of the gate oxide.
`
`The conductive material acts as the gate and the gate oxide creates a layer of
`
`13
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`Qualcomm,
`Exhibit 1 102
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`Page 14 of 87
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`Page 14 of 87
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`U.S. Patent No. 6,784,552
`
`Claims 8-12
`
`isolation between the gate and the source/drain and substrate regions (“S/D
`
`regions” or “diffusion regions”).
`
`33.
`
`Insulating materials may then be deposited around and over the gate
`
`and the S/D regions to maintain electrical isolation where desired. Sidewall
`
`spacers, for instance, can be formed on each side of the gate electrode as shown
`
`below:
`
`
`
`As was known as of the time of the alleged ’5 52 invention, such sidewall spacers
`
`help prevent direct electrical contact between the gate electrode and nearby
`
`components and thus help to prevent short-circuits.
`
`2. Etching to Create Contact Openings
`
`34. Gate electrodes and S/D regions of transistors must typically be
`
`connected to other components in the semiconductor device. These connections
`
`are made using “contacts”—connections between components that allow electrical
`
`signals to pass between the components. Contacts are formed by creating openings
`
`through the layers of a semiconductor device (i. e. “contact openings”) and then
`
`performing a process that fills the openings with a conductive material. Fig. 4(J)
`
`14
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`Qualcomm,
`Exhibit 1 102
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`Page 15 of 87
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`U.S. Patent No. 6,784,552
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`Claims 8-12
`
`of the ’5 52 patent shows a fully-formed contact opening 460, while Fig. 4(L)
`
`shows the contact opening after it has been filled with a conductive material 480
`
`(pink) to form the contactlz
`
`
`
`The process of removing material to create contact openings is known as
`
`“etching.” To perform etching, semiconductor manufacturers use “etchants.” As
`
`was known at the time of the alleged ’552 invention, etchants have various known
`
`properties that can be chosen depending on the type of etching desired.
`
`35.
`
`Etching can be performed “isotropically” or “anisotropically.” An
`
`isotropic etch will etch material in all directions (e.g., both vertically and
`
`horizontally with respect to the substrate surface). An anisotropic etch will etch
`
`material more effectively in a particular direction (e.g. , vertically but not
`
`horizontally relative to the substrate surface).
`
`36.
`
`Etching can also be “wet” or “dry.” Wet etching refers to etching in
`
`which the etchant is a liquid, which will dissolve through a particular material to
`
`1 All emphasis and annotations added unless otherwise indicated.
`
`15
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`Qualcomm,
`Exhibit 1 102
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`Page 16 of 87
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`U.S. Patent No. 6,784,552
`Claims 8-12
`
`create a contact opening. Dry etching—sometimes based on the physical process
`
`known as “sputtering”—is etching away material by using a gas or plasma to
`
`bombard the material to be etched with ions. Generally, wet etching is used to
`
`perform isotropic etching (i. e., all directions) and dry etching is used to perform
`
`anisotropic etching (z'.e., one direction).
`
`37.
`
`Etchants can also be “selective” or “non-selective.” The “selectivity”
`
`of an etchant refers to its effectiveness at etching away one type of material versus
`
`another type of material. A highly-selective etchant relative to a particular material
`
`will etch away that material at a much faster rate than a different type of material.
`
`A non-selective etchant will etch away both types of materials at approximately the
`
`same rate. See, e.g., ’552 at 2:12-21; see also id. at 4266-5 :2. The same etchant
`
`can behave as either a selective or non-selective etchant depending on the material
`
`being etched, the processing conditions, and other parameters of the etching
`
`process. For example, an etchant that is selective as to one material can be non-
`
`selective as to another.
`
`38. As was well-known at the time of the ’552 patent, contact openings of
`
`various shapes and sizes can be created depending on the etching method chosen.
`
`As shown in Figs. 4(H) and 4(1) of the ’552 patent, the etchant removes material to
`
`create an “opening” in the layers of a semiconductor device. Fig. 4(H) shows a
`
`transistor structure with insulating material 450 (green) covering the diffusion
`
`16
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`Exhibit 1 102
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`Page 17 of 87
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`U.S. Patent No. 6,784,552
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`Claims 8-12
`
`regions 445 (orange). Fig. 4(1) shows the same structure after the insulating
`
`material has been etched to create contact openings 460 and 465 which extend
`
`down towards the diffusion regions:
`
`
`
`39. As was also well known, “etch stop layers” (material 440 in Figs.
`
`4(H) and 4(1)) can be used to avoid etching areas not intended to be removed. An
`
`etch stop layer, as its name suggests, effectively stops an etchant from further
`
`eroding or removing material once the etching process reaches the etch stop layer.
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`Etch stop layers are thus used to protect components (e.g., a gate electrode or S/D
`
`region) by stopping the etchant before it reaches the protected component.
`
`40.
`
`The following figures illustrate the process. The figure below (step 1)
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`shows a diffusion region with an etch stop layer above it and further covered by an
`
`insulating material:
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`17
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`Page 18 of 87
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`U.S. Patent No. 6,784,552
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`Claims 8-12
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`
`
`41. As shown in the figure below (step 2), to make a contact opening
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`down to the diffilsion region, an etchant is applied to the insulating material.
`
`(Masking layer not shown.) The etchant effectively etches away the insulating
`
`material but not the etch stop layer. As a result, when the etchant reaches the etch
`
`stop layer, etching is stopped. In this way, the etch stop layer prevents the etchant
`
`from etching into and damaging the diffusion region:
`
`
`
`42. As shown in the figure below (step 3), the etch stop layer can then be
`
`removed by using a different (and usually more precise) etching process to
`
`complete the contact opening down to the diffusion region (masking layer not
`
`shown):
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`18
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`Page 19 of 87
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`U.S. Patent No. 6,784,552
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`Claims 8-12
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`
`
`IV. OVERVIEW OF THE ’552 PATENT
`
`A. The Alleged Problem in the Art
`
`43.
`
`The ’5 52 patent purports to describe an improved technique for
`
`forming contact openings in transistors. The patent asserts that prior art techniques
`
`for forming contact openings resulted in an unacceptably high risk of creating
`
`unintentional connections (and thus a short-circuit) between the contacts and
`
`nearby components. Specifically, according to the patent, the use of highly
`
`selective etchants to create contact openings caused the sidewall spacers between a
`
`contact opening and a nearby component (such as a gate electrode) to become
`
`sloped.
`
`’552 at 5:6-14 (“The properties of the highly selective etch of the
`
`overlying etch stop layer 240 will transform a substantially rectangular spacer
`
`into a sloped spacer.”); id. at 2:4-6, 2:39-41. This is shown in Fig. 2(B):
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`19
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`U.S. Patent No. 6,784,552
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`Claims 8-12
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`
`
`The figure, described as “Prior Art,” shows a contact opening 270, a sidewall
`
`spacer 235, and a gate electrode 220 that needs to remain isolated from the contact
`
`opening. As shown, the sidewall spacer has become “sloped.” ’552 at 526-14; see
`
`also id. at 5:51-55.
`
`44.
`
`The patent then explains that, in subsequent fabrication steps, a sloped
`
`sidewall is particularly susceptible to erosion such that it can be worn down to the
`
`point that the contact opening and a nearby component (e.g., the gate electrode)
`
`can come into unintentional contact. Specifically, the patent explains that, after the
`
`contact opening is formed, an additional etching step is usually performed to clean
`
`the contact opening.
`
`’552 at 5:55-56 (explaining that “RF sputter etch 380” is
`
`performed). This final etching step—which is a dry etch performed using vertical
`
`bombardment—can erode the remaining insulating material separating the gate
`
`electrode from the contact opening. The patent explains that because the sidewall
`
`spacer has become sloped, it is more directly exposed to the vertical bombardment
`
`20
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`Page 21 of 87
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`U.S. Patent No. 6,784,552
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`Claims 8-12
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`and thus more susceptible to erosion.
`
`’552 at 5:59-6:1 (“The dynamics of the
`
`sputter etch 380 are that it proceeds vertically, directing high-energy particles at
`
`the contact region. .
`
`.
`
`. Because the spacer portion 370 is sloping or diagonal, a
`
`significant surface area portion of the spacer portion 3 70 is directly exposed to
`
`the high-energy particles from the RF spatter etch 380.”). This is shown in Fig.
`
`3:
`
`
`
`As shown, as a result of this process, the sloped sidewall spacer has become further
`
`eroded from the dotted line (370) to the solid line such that the gate electrode 320
`
`is now exposed to the contact opening.
`
`’552 at 6: 14-19 (“[T]he result of the
`
`sputter etch 380 is that the sputter etch 380 laterally erodes the diagonal portion of
`
`the TEOS spacer portion 370 adjacent to the contact region to a point where the
`
`polysilicon layer 320 [i.e., the gate electrode] is no longer isolated from the contact
`
`region 360 by an insulating layer.”). According to the patent, such contact results
`
`21
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`U.S. Patent No. 6,784,552
`Claims 8-12
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`in a short-circuit and thus a non-functioning transistor.
`
`’5 52 at 6: 19-21.
`
`B. The Alleged ’552 Patent Invention
`
`45.
`
`The patent purports to solve this problem by using a process that
`
`prevents the formation of a sloped spacer and instead retains the “substantially
`
`rectangular” shape of the lateral spacer.
`
`’552 at 11:48-49 (“[C]are is taken to etch
`
`the spacers 435 such that the spacers 435 have a substantially rectangular
`
`profile.”), 13:9-16 (“Of primary significance, the spacer portion 435 of the TEOS
`
`layer retains its substantially rectangular profile. .
`
`.
`
`. The invention relates to these
`
`process conditions as well as others that result in the retention of a boxy spacer.”
`
`(TEOS is a common type of insulator used in integrated circuits)).
`
`46.
`
`The patent does not purport to have invented the use of sidewall
`
`spacers, the use of anisotropic etchants to etch in a vertical direction, or the use of
`
`such etchants to form contact openings. All of this was indisputably well-
`
`known.
`
`’552 at 1:10-7:13 (Background). Instead, the patent claims as its novel
`
`concept the use of a known etchant in such a way that retains the “substantially
`
`rectangular” shape of the sidewall spacer. Specifically, the patent describes using
`
`an anisotropic etchant that etches only vertically relative to the substrate surface to
`
`form a contact opening. According to the patent, the use of such an etchant avoids
`
`the problem of creating a sloped spacer and instead “retains the substantially
`
`rectangular lateral spacer portion” of the lateral spacer.
`
`’552 at 7:45-51 (“The
`
`22
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`U.S. Patent No. 6,784,552
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`Claims 8-12
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`etch-stop is also almost completely anisotropic, meaning that the etchant etches in
`
`one direction-in this case, vertically (or perpendicular relative to the substrate
`
`surface) rather than horizontally. The etch removes the etch stop insulating layer
`
`and retains the substantially rectangular lateral spacer portion of the first
`
`insulating layer.”).
`
`47.
`
`Figs. 4(J) and 4(K) (which is a blow-up of 4(J)) show the contact
`
`opening after etching is complete:
`
`
`
`’552 at 12:54-13: 10. As shown by the red lines in the figures, after the contact
`
`opening 460 has been etched, the sidewalls (420) have vertical sides thus retaining
`
`their “substantially rectangular” shape.
`
`48. As a result, according to the patent, the lateral spacer is less
`
`susceptible to erosion in the subsequent sputter etch step—which involves the
`
`vertical bombardment of the contact region with high energy particles—and thus
`
`the risk of unintentional contact (and short-circuit) with nearby components is
`
`reduced.
`
`’5 52 at 7:62-8:3 (“Unlike prior art processes whereby the sputter etch
`
`23
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`U.S. Patent No. 6,784,552
`Claims 8-12
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`erodes the underlying sloping lateral spacer portion of the first insulating layer
`
`adjacent to the conducting layer, the sputter etch does not significantly erode the
`
`substantially rectangular lateral spacer of the first insulating layer, thus allowing
`
`the conductive layer of the device structure to remain completely isolated. .
`
`. .”).
`
`Claim 8 is the sole challenged independent claim. The dependent claims add only
`
`implementation details such as: additional specificity regarding the materials
`
`around the insulative spacer (claims 9-10); additional insulating layers on the
`
`structure (claim 11); and conductive material in the contact o