`Petition for Inter Partes Review
`
`
`DOCKET NO.: 54918.5
`Filed on behalf of Qualcomm and GlobalFoundries
`
`By: David L. McCombs, Reg. No. 32,271
`
`David M. O’Dell, Reg. No. 42,044
`
`
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
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`__________________
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`___________________
`
`
`
`QUALCOMM INCORPORATED, GLOBALFOUNDRIES INC.,
`GLOBALFOUNDRIES U.S. INC., GLOBALFOUNDRIES DRESDEN
`MODULE ONE LLC & CO. KG, GLOBALFOUNDRIES DRESDEN MODULE
`TWO LLC & CO. KG
`Petitioner
`
`v.
`
`DSS Technology Management, Inc.
`Patent Owner
`
`Case IPR2016-01313
`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 5,965,924
`CHALLENGING CLAIMS 1-6, 13, 14 and 16
`UNDER 35 U.S.C. § 312 AND 37 C.F.R. § 42.104
`
`
`
`
`
`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
`
`TABLE OF CONTENTS
`
`
`
`
`I.
`Introduction ........................................................................................................ 3
`II. Mandatory Notices ............................................................................................. 7
`A. Real Party-in-Interest .................................................................................... 7
`B. Related Matters .............................................................................................. 7
`C. Counsel .......................................................................................................... 8
`III. Certification of Grounds for Standing .............................................................. 8
`IV. Overview of Challenge and Relief Requested ................................................. 9
`A. Prior Art Patents ............................................................................................ 9
`B. Grounds for Challenge .................................................................................. 9
`V. Brief Description of Technology ....................................................................... 9
`A. Overview of Transistor Fabrication ............................................................ 10
`1. Basic Structure of Transistors .................................................................. 10
`2. Formation of Transistor Components ...................................................... 11
`3. Local Interconnects .................................................................................. 12
`B. Overview of the ’924 Patent ........................................................................ 14
`1. Alleged Problem ....................................................................................... 14
`2. Summary of Alleged Invention of the ’924 Patent .................................. 15
`3. The Challenged Claims ............................................................................ 17
`4. Prosecution History .................................................................................. 18
`VI. Overview of the Primary Prior Art References .............................................. 21
`A. Overview of Sakamoto ................................................................................ 21
`B. Overview of Cederbaum ............................................................................. 23
`VII. Claim Construction ...................................................................................... 25
`A.
`“diffusion region formed in said substrate” ................................................ 25
`VIII. Level of Ordinary Skill In The Art .............................................................. 28
`IX. Specific Grounds for Petition ......................................................................... 29
`A. Ground I: Claims 1-3, 14 and 16 are anticipated by Sakamoto ................. 29
`
`1
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`
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`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
`1.
`Independent Claim 1 ................................................................................ 29
`2. Claim 2: “A semiconductor structure according to claim 1, wherein said
`diffusion region is an N+ or a P+ region” ........................................................ 45
`3. Claim 3: “A semiconductor structure according to claim 1, wherein said
`insulator layer is formed of a material selected from the group consisting of
`silicon oxide and silicon nitride.” .................................................................... 46
`4. Claim 14: “A semiconductor structure according to claim 1, wherein said
`polysilicon gate and said diffusion region being exposed in said via in the
`absence of said conducting plug.” ................................................................... 47
`5. Claim 16: “The structure according to claim 1, wherein said gate
`comprises polysilicon.” .................................................................................... 48
`B. Ground II: Claims 4-6 and 13 are obvious in view of the combination of
`Sakamoto and Cederbaum ................................................................................... 49
`1. Claim 4: “a semiconductor structure according to claim 1, wherein said
`electrically conducting plug is a metal plug” / Claim 5: “a semiconductor
`structure according to claim 1, wherein said electrically conducting plug is a
`refractory metal plug.” / Claim 6: “a semiconductor structure according to
`claim 1, wherein said electrically conducting plug is formed of a material
`selected from the group consisting of titanium, tantalum, molybdenum and
`tungsten” .......................................................................................................... 49
`2. Claim 13: A semiconductor structure according to claim 1, wherein said
`conducting plug comprises an outer glue layer and a plug material therein ... 55
`X. Conclusion ....................................................................................................... 57
`
`
`
`
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`
`
`2
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`
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`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
`
`Petitioner respectfully requests Inter Partes Review of claims 1-6, 13, 14
`
`and 16 of U.S. Patent No. 5,965,924 (the “’924 patent”) (Ex. 1001) pursuant to 35
`
`U.S.C. §§ 311-19 and 37 C.F.R. § 42.1 et seq. The above-listed claims of the ’924
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`patent are presently the subject of a substantially identical petition for inter partes
`
`review styled Intel Corporation v. DSS Technology Management, Inc., which was
`
`filed December 8, 2015 and assigned Case No. IPR2016-00289. Petitioner will
`
`seek joinder with that inter partes review under 35 U.S.C. § 315(c), 37 C.F.R. §§
`
`42.22 and 42.122(b).
`
`I. INTRODUCTION
`
`The ’924 patent claims a purportedly novel structure for transistors in
`
`semiconductors. But in fact, the claimed structure merely duplicates a well-known
`
`technique disclosed by Osamu Sakamoto and others nearly three years before the
`
`alleged invention.
`
`The ’924 patent is directed to certain aspects of the structure and fabrication
`
`of transistors used in semiconductor and integrated circuit products such as
`
`microprocessors and memory. Transistors act as microscopic switches that turn on
`
`and off at extraordinarily high rates to enable aggregations of transistors (and other
`
`components) to process data. Transistors are made up of various structures
`
`including “contacts” that provide electrically conductive pathways into and out of
`
`certain structures within a transistor, and which thereby are used to connect
`
`3
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`
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`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
`
`transistors together. Declaration of Dr. Richard Blanchard (“Decl.”) ¶ 26 (Ex.
`
`1002).
`
`The ’924 patent is concerned with electrically connecting different transistor
`
`parts to each other in a particular way. Transistors typically have three terminals
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`through which electrical signals may pass: a “source,” a “drain,” and a “gate.” The
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`’924 patent is concerned with connecting the gate of one transistor to, for example,
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`the source or drain of a neighboring transistor. Decl. ¶ 27 (Ex. 1002).
`
`As the specification of the ’924 patent admits, there were many well-known
`
`ways of making electrical connections between different transistor parts. As
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`shown in Figure 2B (below), for instance, one of the admitted prior art ways of
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`connecting the components of two transistors was by using two electrical
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`connections called “plugs”—one connected to the gate of one transistor, and the
`
`other connected to the source or drain of the other—and then connecting those
`
`plugs together. As shown in Figure 3B (below), the purported invention of the
`
`’924 patent was to replace the two plugs with one plug. Decl. ¶ 28 (Ex. 1002). 1
`
`
`1 All emphasis and annotations are added unless otherwise indicated.
`
`4
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`
`
`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
`
`Admitted Prior Art: Fig. 2B
`
`Allegedly Novel Structure: Fig. 3B
`
`In both the admitted prior art (Figure 2B) and the allegedly novel structure
`
`
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`of the ’924 patent (Figure 3B), the gate is connected to a diffusion region (i.e., a
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`source or drain) by either two connected plugs, or a single plug. The patent does
`
`not claim that the one-plug structure provides any performance benefits over the
`
`two-plug structure. Instead, the only purported benefit was that the one-plug
`
`structure was easier to manufacture than the admitted prior art. ’924 patent at
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`1:57-2:63, 4:18-5:12 (Ex. 1001); Decl. ¶ 29 (Ex. 1002).
`
`But long before the ’924 patent’s November 22, 1995 priority date,2 many
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`others had already developed and used the exact same one-plug structure. U.S.
`
`
`2 The prior assignee claimed a conception date of May 17, 1995 during prosecution
`
`of the ’924 application. Amendment and Rule 131 Declaration dated Jan. 5, 1998
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`(Ex. 1006). Even under that alleged conception date, the references relied upon by
`
`Petitioner all qualify as prior art and invalidate the ’924 patent.
`
`5
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`
`
`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
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`Patent No. 5,475,240 (“Sakamoto”), for instance, which has an effective filing date
`
`of March 4, 1992, discloses the same one-plug structure that the ’924 patent
`
`contends is novel. Specifically, as shown in the patents’ respective figures, the
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`one-plug structure of Sakamoto (Figure 1) is in all relevant aspects identical to the
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`one-plug structure of the ’924 patent (Figure 3B). Decl. ¶ 30 (Ex. 1002).
`
`Sakamoto: Fig. 1
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`’924 Patent: Fig. 3B
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`As shown, both structures include a gate connected to a source or drain
`
`through a single plug. Decl. ¶ 31 (Ex. 1002).
`
`Similarly, U.S. Patent No. 5,100,817 (“Cederbaum”) issued on March 31,
`
`1992, and, just like the ’924 one-plug structure, discloses a single conducting plug
`
`connecting a gate to a source or drain. Decl. ¶ 32 (Ex. 1002).
`
`6
`
`
`
`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
`
`Cederbaum: Fig. 7
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`These prior art references, which were not at issue during prosecution of the
`
`
`
`’924 patent, anticipate and/or render obvious claims 1-6, 13, 14 and 16 the ’924
`
`patent. Decl. ¶ 33 (Ex. 1002).
`
`II. MANDATORY NOTICES
`
`A. Real Party-in-Interest
`
`Qualcomm Incorporated and GLOBALFOUNDRIES Inc.,
`
`GLOBALFOUNDRIES U.S. Inc., GLOBALFOUNDRIES Dresden Module One
`
`LLC & Co. KG, GLOBALFOUNDRIES Dresden Module Two LLC & Co. KG
`
`(collectively “Petitioner”) are the real party-in-interest.
`
`B. Related Matters
`DSS has asserted the ’924 patent in two separate proceedings: (1) DSS Tech.
`
`Mgmt., Inc. v. Intel Corp. et al., Civil Action No. 6:15-CV-130-RWS (E.D. Tex.
`
`2015); and (2) DSS Tech. Mgmt., Inc. v. Qualcomm Inc., Civil Action No. 6:15-
`
`CV-692-JRG (E.D. Tex. 2015). These proceedings may be affected by a decision
`
`in this instant proceeding.
`
`7
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`
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`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
`
`The ’552 patent is currently being challenged before the Board in the
`
`following cases: Intel Corporation v. DSS Technology Management, Inc.,
`
`IPR2016-00289 and 00290. Also, the Petitioner is filing a separate inter partes
`
`review petition for claims 7-12, 15 and 17 of the ’924 patent.
`
`C. Counsel
`
`Back-up Counsel
`
`Lead Counsel
`
`David M. O’Dell
`HAYNES AND BOONE, LLP
`2323 Victory Ave. Suite 700
`Dallas, TX 75219
`
`Phone: (972) 739-8635
`Fax: (214) 200-0853
`david.odell.ipr@haynesboone.com
`
`USPTO Customer No. 27683
`USPTO Reg. No. 42,044
`
`Please address all correspondence to lead and back-up counsel. Petitioner
`
`David L. McCombs
`HAYNES AND BOONE, LLP
`2323 Victory Ave. Suite 700
`Dallas, TX 75219
`
`Phone: (214) 651-5533
`Fax: (214) 200-0853
`david.mccombs.ipr@haynesboone.com
`
`USPTO Customer No. 27683
`USPTO Reg. No. 32,271
`
`also consents to electronic service by email.
`
`III. CERTIFICATION OF GROUNDS FOR STANDING
`
`Petitioner certifies pursuant to Rule 42.104(a) that the patent for which
`
`review is sought is available for inter partes review and that Petitioner is not
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`barred or estopped from requesting an inter partes review challenging the patent
`
`claims on the grounds identified in this Petition.
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`
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`8
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`
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`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
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`IV. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`
`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)-(2), Petitioner challenges
`
`claims 1-6, 13, 14 and 16 of the ’924 patent.
`
`A. Prior Art Patents
`Petitioner relies upon the patents listed in the Table of Exhibits, including:
`
`1.
`
`U.S. Pat. No. 5,475,240 (“Sakamoto” (Ex. 1003)), which was filed on
`
`August 19, 1994, as a continuation of an earlier filed application filed on March 4,
`
`1992, and issued on December 12, 1995. Sakamoto is prior art under 35 U.S.C. §
`
`102(e).
`
`2. U.S. Pat. No. 5,100,817 (“Cederbaum” (Ex. 1004)), which was issued
`
`on March 31, 1992, is prior art under 35 U.S.C. §§ 102(b).
`
`B. Grounds for Challenge
`
`Petitioner requests cancellation of claims 1-6, 13, 14 and 16 of the ’924
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`patent as unpatentable under 35 U.S.C. § 102 and § 103. This Petition, supported
`
`by the declaration of Dr. Richard Blanchard (Ex. 1002) filed herewith,
`
`demonstrates that there is a reasonable likelihood that Petitioner will prevail with
`
`respect to cancellation of at least one challenged claim. See 35 U.S.C. § 314(a).
`
`V. BRIEF DESCRIPTION OF TECHNOLOGY
`
`The ’924 patent generally relates to the field of semiconductor integrated
`
`circuit manufacturing and claims particular structures for transistors in
`
`9
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`
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`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
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`semiconductors, as well as a related method for manufacturing those structures.
`
`Decl. ¶ 34 (Ex. 1002).
`
`A. Overview of Transistor Fabrication
`1. Basic Structure of Transistors
`
`Semiconductor integrated circuits, such as microprocessors and computer
`
`memory, are typically made up of hundreds of millions (and in some cases billions)
`
`of microscopic structures called transistors. Transistors act as microscopic
`
`switches that turn on and off at extraordinarily high rates to enable aggregations of
`
`transistors (and other components) to process data. Decl. ¶ 35 (Ex. 1002).
`
`As shown in the figure below, transistors typically include three primary
`
`“electrodes” or “terminals”—a “gate,” a “source,” and a “drain.” Decl. ¶ 36 (Ex.
`
`1002).
`
`
`
`The source and drain regions (also referred to as “diffusion regions”) are
`
`transistor components that emit (source) and receive (drain) current when the
`
`transistor is “on.” The gate typically sits between the source and drain and is a
`
`10
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`
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`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
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`terminal that can have a voltage applied to it that in turn causes a current to flow
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`between the source and drain. As of the time of the invention of the ’924 patent,
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`the source and drain of a transistor were typically formed in the surface of a
`
`semiconductor “substrate,” while the gate typically sat above the substrate and
`
`separated from it by a thin layer of insulator (“gate oxide”). Decl. ¶ 37 (Ex. 1002).
`
`2. Formation of Transistor Components
`
`Transistor fabrication typically starts with a silicon substrate. In typical
`
`planar transistors, the source and drain regions (“diffusion regions”) are created by
`
`implanting regions of the substrate with ions (charged atomic particles) of different
`
`materials—called “dopants” or “impurities”—to make those regions conductive.
`
`(Once implanted the ions become neutral atoms). This process—referred to as
`
`“doping” because it dopes the silicon substrate with atomic particles that have
`
`additional charge carriers—is shown below. Decl. ¶ 38 (Ex. 1002).
`
`
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`Structures can then be formed above the substrate by depositing layers of
`
`other materials onto the substrate. A gate electrode, for example, is formed by first
`
`growing or depositing a “gate oxide” (an insulator) on the substrate followed by
`
`11
`
`
`
`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
`
`depositing a conductive material (metal or polysilicon) on top of the gate oxide.
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`The conductive material acts as the gate, and the gate oxide creates a layer of
`
`isolation between the gate and the source/drain regions (“S/D regions” or
`
`“diffusion regions”). Decl. ¶ 39 (Ex. 1002).
`
`Insulating materials may then be deposited around and over the gate and the
`
`source/drain regions to maintain electrical isolation where desired. Sidewall
`
`spacers, for instance, can be formed on each side of the gate electrode as shown
`
`below.
`
`
`
`As was known as of the time of the alleged ’924 invention, such sidewall spacers
`
`help to prevent direct electrical contact between the gate electrode and nearby
`
`components and thus help to prevent short-circuits. Decl. ¶ 40 (Ex. 1002).
`
`3. Local Interconnects
`
`Many transistors can be connected together to form electronic circuits. For
`
`certain types of circuits, it is sometimes useful to connect the gate of one transistor
`
`to a diffusion region (the source or drain) of a nearby transistor. This type of
`
`12
`
`
`
`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
`
`connection is called a “local interconnect,” because connections are made locally
`
`between nearby transistors. Decl. ¶ 41 (Ex. 1002).
`
`As the specification of the ’924 patent concedes, a variety of different types
`
`of local interconnects were well-known prior to the purported invention. For
`
`example, as shown in Figure 1B of the ’924 patent, one well-known way to form a
`
`local interconnect was to position the gate in a location where it physically touches
`
`the diffusion region on one side, creating an electrical connection. As shown in
`
`Figure 2B of the ’924 patent, another well-known way to make a local interconnect
`
`was to place one electrically conductive “plug” above the gate and another “plug”
`
`above the diffusion (e.g., source or drain) region, and then electrically connect the
`
`two plugs together. Decl. ¶ 42 (Ex. 1002).
`
`Admitted Prior Art: Fig. 1B
`
`Admitted Prior Art: Fig. 2B
`
`
`
`The ’924 patent acknowledges that both examples were known prior art. See
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`’924 patent at Figs. 1A, 1B, 2A, 2B, 1:25-2:45, 3:30-35 (Ex. 1001); Decl. ¶ 43 (Ex.
`
`1002).
`
`13
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`
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`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
`
`B. Overview of the ’924 Patent
`
`The ’924 patent issued from U.S. App. No. 08/900,047, which was filed on
`
`July 24, 1997, and claims priority to an application filed on November 22, 1995.
`
`’924 patent at cover page (Ex. 1001). The purported invention of the ’924 patent is
`
`a single plug to connect different transistor parts. ’924 patent at 2:32-67, 4:18-5:12
`
`(Ex. 1001); Decl. ¶ 44 (Ex. 1002).
`
`1. Alleged Problem
`
`The ’924 patent purports to address manufacturing inefficiencies in forming
`
`local interconnects. Figures 1 and 2 of the ’924 patent are admitted prior art and
`
`show examples of two well-known types of local interconnects that (according to
`
`the ’924 patent) are inefficient to manufacture. Decl. ¶ 45 (Ex. 1002).
`
`Figure 1B shows a “buried contact” local interconnect structure in which the
`
`gate directly touches—i.e., is in direct electrical connection with—a diffusion
`
`region. According to the ’924 patent, the problem with this structure is that the
`
`gate has to be implanted with the same type of impurities as those implanted in the
`
`diffusion region. See ’924 patent at 1:57-2:11 (Ex. 1001). But most manufacturers
`
`use a variety of different types of impurities in different transistors. To use the
`
`“buried contact” approach, a manufacturer would have to ensure that any two
`
`transistors connected using this approach use the same impurities, which
`
`complicates the manufacturing process. See id.; see also Decl. ¶ 46 (Ex. 1002).
`
`14
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`
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`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
`
`Admitted Prior Art: Fig. 1B
`
`Admitted Prior Art: Fig. 2B
`
`
`
`Figure 2B shows another prior art local interconnect structure, using what is
`
`called a “strapping” technique. To form this “strapping” local interconnect
`
`structure, a manufacturer creates two electrically conductive plugs (numbers 44
`
`and 46)—one above the gate and one above a diffusion region. The manufacturer
`
`then places an electrically conductive “local strap” (number 50) on top of the
`
`plugs, electrically connecting the two plugs together. This local strap is also
`
`sometimes called a “shunt” or a “shunt layer.” In combination, the two plugs and
`
`the local strap electrically connect the gate to a diffusion region. See ’924 patent at
`
`2:12-32 (Ex. 1001). According to the ’924 patent, the problem with the strapping
`
`technique is that it requires a large number of manufacturing process steps, as well
`
`as significant space to accommodate the two plugs and the local strap. See ’924
`
`patent at 2:33-41 (Ex. 1001); see also Decl. ¶ 47 (Ex. 1002).
`
`2. Summary of Alleged Invention of the ’924 Patent
`
`The ’924 patent’s claimed structure includes nearly identical components as
`
`15
`
`
`
`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
`
`the admitted prior art described in the specification. Specifically, both the claimed
`
`structure and the admitted prior art include a substrate, a gate, a diffusion region, a
`
`sidewall spacer adjacent to the gate, and an insulating layer. Decl. ¶ 48 (Ex. 1002).
`
`Admitted Prior Art: Fig. 2B
`
`Preferred Embodiment: Fig. 3B
`
`
`
`
`
`As shown in Figures 2B and 3B, in both the admitted prior art of the ’924
`
`patent and the allegedly novel structure, the gate is connected to the diffusion
`
`region (source or drain), by either two connected plugs, or a single plug. The
`
`diffusion region is located in a substrate and is not directly connected to the gate.
`
`The gate is substantially covered by an insulating layer. Decl. ¶49 (Ex. 1002).
`
`The patent’s only alleged novelty—shown in Figure 3B—is the use of a
`
`single metal plug to connect the gate and the diffusion region, rather than
`
`connecting the two components directly (as in the prior art “buried contact”
`
`technique (Figure 1B)) or using two plugs (as in the prior art “strapping” technique
`
`(Figure 2B)). ’924 patent at 2:64-67, 3:35-36 (describing Figure 3B as “a cross-
`
`16
`
`
`
`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
`
`sectional view of a preferred embodiment of the present invention.”), 4:18-5:12,
`
`claims 1, 7 (Ex. 1001); see also id. at 2:42-63; Decl. ¶ 50 (Ex. 1002).
`
`But as explained below, there is nothing novel about using a single
`
`conducting plug.
`
`3. The Challenged Claims
`
`This petition challenges claims 1-6, 13, 14 and 16 of the ’924 patent.
`
`Independent claim 1 describes a semiconductor structure, in which a plug provides
`
`a direct electrical connection between a diffusion region formed in a substrate and
`
`a gate formed on top of the substrate. ’924 patent at claim 1 (Ex. 1001). Claim 1
`
`also specifies additional well known features, including a sidewall spacer and
`
`insulator layer on the gate, as noted below.
`
`A semiconductor structure comprising:
`[a] a silicon substrate having a top surface,
`[b] a diffusion region formed in said substrate adjacent to said
`top surface,
`[c] a gate formed on the top surface of said substrate juxtaposed
`to but not contacting said diffusion region,
`[d] a sidewall spacer adjacent to said gate and disposed above
`said diffusion region,
`[e] an insulator layer substantially covering said gate and said
`diffusion region, and
`[f] a conducting plug at least partially filling a via in said
`
`17
`
`
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`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
`
`
`insulation layer that exposes said sidewall spacer in the absence of
`said conducting plug, said conducting plug providing direct electrical
`communication between said gate and said diffusion region.
`The dependent claims add well-known implementation details such as defining
`
`particular types of diffusion regions (id. at claim 2), insulating material (id. at
`
`claim 3), conducting plug material (id. at claims 4-6 and 13), and gate material (id.
`
`at claims 14, 16).
`
`4. Prosecution History
`
`The ’924 patent issued from a “continued prosecution application” (“CPA”)
`
`of U.S. App. No. 08/561,951. CPA Request dated Feb. 10, 1999 (Ex. 1005).
`
`During prosecution of the ’924 patent, the Applicant purportedly antedated a prior
`
`art reference, based on a lab notebook dated May 17, 1995. Amendment and Rule
`
`131 Declaration dated Jan. 5, 1998 (Ex. 1006). For purposes of this Petition, the
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`references relied upon by Petitioner all qualify as prior art even if the Patent Owner
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`could ultimately prove a conception date as early as May 17, 1995. Decl. ¶ 51 (Ex.
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`1002).
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`According to this lab notebook, the purported novelty of the ’924 invention
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`arises from the use of a single plug—which is what allegedly leads to fewer
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`processing steps as compared to known prior art techniques. See Rule 131
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`Declaration dated January 5, 1998, Exhibit A (“By placing a metallic plugged
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`contact where poly is required to shunt to diffusion, contacts to [different types of]
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`18
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`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
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`diffusion can be achieved …. [T]his will require no more layout area than the
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`traditional buried contact. This method has potential [manufacturing] process step
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`savings of 8-11 steps over Trad. BC [traditional buried contact local interconnect
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`(as shown in Figure 1B of the ’924 patent)] and 6-8 steps over strapping [local
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`interconnect (as shown in Figure 2B of the ’924 patent)].”) (Ex. 1006). Decl. ¶ 52
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`(Ex. 1002).
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`However, during prosecution, rather than relying on the supposedly novel
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`“single plug” structure, the Applicant relied on other alleged differences to
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`overcome the prior art applied by the Examiner. The present petition relies on new
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`art—not before the Examiner—that teaches not only the allegedly novel “single
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`plug” aspect of the invention, but also all of the additional minor differences that
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`the Applicant used to allegedly distinguish the Examiner’s prior art. Decl. ¶ 53
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`(Ex. 1002).
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`a) The “sidewall spacer” limitations
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`The Examiner rejected the original claims under 35 U.S.C. § 102(e) based
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`on U.S. Patent No. 5,451,434 to Nicholls (“Nicholls”). Office Action dated Nov.
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`7, 1996 at p. 3 (Ex. 1007). Nicholls taught a single metal plug that connects a
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`diffusion region and a gate. In order to overcome the rejection, the Applicant
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`added a limitation to the claims requiring a sidewall spacer adjacent to the gate.
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`Amendment dated June 9, 1997 at pp. 2-3 (Ex. 1009). Nicholls expressly teaches
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`19
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`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
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`the placement of a sidewall during manufacture, but also teaches that the sidewall
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`can be completely or “partially removed” in a later manufacturing step. Nicholls at
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`4:25-32 (Ex. 1008). The Applicant overcame the rejection by arguing that the
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`removal of the sidewall during manufacturing taught away from retaining a
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`sidewall spacer adjacent to the gate. Amendment dated June 9, 1997 at pp. 3-4
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`(Ex. 1009). The prior art relied upon in this petition teaches the “sidewall spacer”
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`limitation. Decl. ¶ 54 (Ex. 1002).
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`b) Direct electrical connection
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`The Examiner also rejected the claims under 35 U.S.C. § 102(e) based on
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`U.S. Patent No. 5,541,427 to Chappell (“Chappell”). Office Action dated February
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`24, 1998 (Ex. 1010). Chappell taught a single metal plug that connects to both a
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`diffusion region and a gate region. Chappell at 4:38-48 (Ex. 1011). The Applicant
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`overcame the rejection by arguing that the metal plug of Chappell purportedly
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`contacts a portion of the gate region that is not conductive, rather than the
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`conductive portion of the gate itself. See Amendment dated April 23, 1998 at p. 4
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`(“‘when the opening 42 is filled with an electrically conductive material, there is
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`no contact to the electrically conductive portion of the gate stack’”) (emphasis in
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`original) (quoting Chappell at 4:38-48) (Ex. 1012). The prior art references relied
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`upon in this petition teach a direct electrical connection between the diffusion
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`region and the electrically conductive portion of the gate. Decl. ¶ 55 (Ex. 1002).
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`20
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`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
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`VI. OVERVIEW OF THE PRIMARY PRIOR ART REFERENCES
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`The claimed invention of the ’924 patent—using a single plug to electrically
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`connect the gate to the diffusion region—was well-known as of the May 17, 1995
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`purported conception date. Decl. ¶ 56 (Ex. 1002). Each of the prior art references
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`relied upon in this petition has an effective filing date earlier than that alleged
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`conception date.
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`A. Overview of Sakamoto
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`Sakamoto was filed on August 19, 1994, as a continuation of an earlier
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`application filed on March 4, 1992, and issued on December 12, 1995. It is
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`therefore prior art to the ’924 patent under 35 U.S.C. § 102(e). Decl. ¶ 57 (Ex.
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`1002).
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`Sakamoto is directed to precisely the same problem as the ’924 patent —
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`how to effectively and efficiently connect different transistor portions together—
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`and discloses precisely the same solution claimed in the ’924 patent—using a
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`single plug. Sakamoto at 4:45-49 (“The first interconnection structure comprises a
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`silicon plug layer embedded within an opening formed in the interlevel insulating
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`layer and connected to both gate electrode of the first MOS drive transistor and
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`source/drain region of the second MOS transfer transistor…”) (Ex. 1003); see also
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`id. at 1:13-14. Figure 1 of Sakamoto shows a structure with the same components
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`arranged in the same way as shown in Figure 3B of the ’924 patent. Id. at Fig. 1;
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`21
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`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review
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`’924 patent at Fig. 3B (Ex. 1001); Decl. ¶ 58 (Ex. 1002).
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`Sakamoto: Fig. 1
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`’924 Patent: Fig. 3B
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`Both Figure 1 of Sakamoto and Figure 3B of the ’924 patent show a cross-
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`sectional structure with a single plug. The plug fills an opening (labeled 16 in
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`Sakamoto) containing a sidewall spacer and directly electrically connects a
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`diffusion region to a gate. The diffusion region is located in a substrate and is not
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`directly connected to the gate. The gate is also substantially covered by an
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`insulating layer. See Sakamoto at 6:52-58 (“An opening 16 is formed in an
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`interlevel insulating layer 9. An n+ source/drain region 7 of an n channel MOS
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`transfer transistor 22b and a gate electrode 6 of an n channel MOS drive transistor
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`20a are exposed at the bottom of opening 16. A plug layer 15 of polycrystalline
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`silicon directly connected to the n+ source/drain region 7 and gate electrode 6 is
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`embedded within opening 16.”), 7:47-51 (“An opening 16 for direct contact is
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`22
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`U.S. Patent No. 5,965,924 Claims 1-6, 13, 14 and 16
`Petition for Inter Partes Review