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`‘ UNITED STATEE PATENT AND
`
`OFFICE
`
`In re application of:
`Serial No.:
`Filed;
`For;
`
`Attorney Docket No.:
`
`TINGP. YEN
`08/561,951
`November 22, 1995
`METAL PLUG LOCAL
`INTERCONNECT
`64,663-O04
`
`Group Art Unit: 2503
`Examiner: WALLACE, V.
`In Response to Ofiice Action
`gfip/:rp 1996
`
`5/@
`L
`
`f 55 7 "f4
`REC ENED
`AUG 2 3 19%
`
`P’
`G
`Certificate ofMailing (37CFR 1.8a)
`I hereby certify that this paper (along with any referred to as being attached or enclosed) is being deposited with the United
`States Postal Service on the date shown below with sufficient postage as first class mail in an envelope addressed to the Assistant
`Commissioner for Patents, Washington D.C. 20231.
`
`Date:August 14, 1996 (Signature of person maili
`
`Assistant Commissioner for Patents
`
`Washington, D.C. 20231
`
`Dear Sir:
`
`A M E N D M E N T
`
`In response to the Oflice Action mailed April 17, 1996, please consider the following
`
`amendments and remarks regarding the above-identified application.
`
`
`
`INTEL 1014
`
`

`
`Please cancel claims 1 and 7, and replace with the new claims 13 and 14.
`
`IN THE CLAIMS
`
`/
`
`A semiconductor structure comprising:
`1§\
`a sili on substrate having atop surface,
`
`a diffiusi n region formed in said substrate adjacent to said top surface,
`
`a polysilic
`
`gate formed on the top surface of said substrate juxtaposed to but not
`
`contacting said diffusion regi
`
`ii,
`
`an insulator layer ubstantially covering said polysilicon gate and said difliision region,
`
`and
`
`
`aiconducting plug at le
`
`electrical communication between said
`
`lysilicon gate and said difliision region.
`
`t partially filling a via in said insulation layer, providing direct
`
`
`
`
`
`local interconnect in a semiconductor structure,
`
`14.
`
`A method of forming
`
`comprising the step of:
`
`depositing an electrically conductin material in a via exposing at least a portion of
`
`a gate and a portion of a diffusion region such that said
`
`ectrically conducting material contacts and
`
`provides electrical communication between said gate and aid diffusion region, said semiconductor
`
`structure comprising said diffusion region in a silicon subst
`
`te, said gate being on said substrate
`
`juxtaposed to but not contacting said diffusion region, said via be g in an insulating material on said
`
`
`gate.
`
`

`
`Amend clai
`
`s 2~6 an 8~l2 as follows:
`
`1, d:/Xv/claim l", and substitutetherewith--claim 13--.
`Claim2 1i
`
`Claim‘ , line
`etc “
`im 1", and substitute therewith --claim 13--.
`Claim 4,
`' e 1 del e“cl 'm 1", and substitute therewith --claim 13--.
`
`Claim
`'
`l, del<%:m 1", and substitutetherewith--claim 13--.
`
`
`
`, line 1, delete “claim 1", and substitute therewith --claim 13--
`
`Line 4, delete “a molybdenum”, and substitute therewith --, molybdenum
`
`’
`
`Claim 1
`
`, line 3, delete “and molybdenum” , and substitute therewith --, molybdenum
`
`and tungsten-- /
`andtungsten-—.
`
`/
`
`Add new claims l5~l7.
`
`
`
`\2
`
`A semiconductor structure according to claima1v3,’wherein said conducting
`
`l
`
`plug comprises an outer glue layer and a plug material therein.
`
`H
`.16
`
`l
`A semiconductor structure according to claim 1'3,’wherein said polysilicon gate
`
`and said diffusion region being exposed in said via in the absence of said conducting plug.
`
`*1
`\5
`A method according to claim 14: wherein said gate is a polysilicon gate.
`Pf
`
`
`
`
`

`
`R E M A R K S
`
`Claims 1 and 7 have been canceled. New claims l3~l7 have been added. Thus claims
`
`2~6 and 8~17 are now pending. No new matter is added by the present amendment.
`
`Support for the amendment to claims 6 and 12 can be found in the specification at p.
`
`10, lines 10-11; p. 11, step 24; p. 12, step 17 and p. 13, step 24.
`
`Support for claim 15 can be found in the specification at p. 11, steps 23~24; p. 13,
`
`steps 23~24; p. 12, steps 16~17 and Figure 3B.
`
`Rejection Under 35 USC §102(a)
`
`The rejection of Claims 1~12 under 35 USC §102(a) as being anticipated by Kinoshita,
`
`US. Patent No. 5,453,640, is respectfully traversed.
`
`Kinoshita teaches a Contact hole formed in an insulating layer over a diffiision region,
`
`and a conducting tungsten plug fills the contact hole. Kinoshita further teaches a block of static
`
`memory cells using CMOS transistors, wherein metal interconnections, e.g.,ground lines for the
`
`CMOS transistors, are simplified by using buried layers in the substrate. Buried tungsten contacts
`
`in the memory cell form connections of the n-MOS and p—MOS transistor diffusion layers to
`
`underlying layers of opposite conductivities. Kinoshita further uses supply voltage or ground
`
`potential to each buried layer from the substrate surface by using additional buried contacts which
`
`are made at convenient locations outside the memory block, As shown in Kinoshita’s Figure 5, the
`
`

`
`diffusion region 46 and the polysilicon gate electrode 26 are adjacent but not in contact with each
`
`other. A tungsten contact plug fills the contact hole 32 for making electrical contact only with the
`
`diffusion region 46 (and not with the gate electrode 26).
`
`The applicant’s claims 1~l2 are not anticipated by Kinoshita ‘640. To anticipate a
`
`claim of a patent, a single source must contain all its essential elements. See, e. g., Tights, Inc. v.
`
`Acme—McCrar)g Corg, 191 USPQ 305 (4th Cir. 1976),
`
`Kinoshita fails to teach a plugthat contacts and provides electrical communication
`
`between a polysilicon gate and a diflhsion region in a via opening exposing the gate and the diffusion
`
`region in the absence of the plug.
`
`Instead insulating layer 38 of silicon oxide or silicon nitride
`
`prevents polysilicon gate electrode 26 from being exposable or exposed in contact hole 32 (see Figure
`
`5 of Kinoshita).
`
`Therefore, Kinoshita does not anticipate the present invention. Withdrawal of the
`
`rejections of claims 1~l2 under 35 USC §l02(a) is respectfiilly requested.
`
`Rejection under 35 USC §102(b)
`
`The rejection of Claims 1~12 under 35 USC §lO2(b) as being anticipated by
`
`Nishigoori, US. Patent No..5,245,210, is respectfully traversed.
`
`Nishigoori 210 discloses a MOS type semiconductor device which has a contact hole
`
`

`
`opened in a layer of insulating material. This first contact hole has a length similar to the width of the
`
`corresponding source/drain dilfusion regions. A refractory metal is then deposited to fill the contact
`
`hole. As shown in Figure 2b ofNishigoori, polysilicon gate electrode 4 is insulated from the diflilsion
`
`regions 5 and 7 by gate oxide 4, side-wall oxide 7 and insulating layer 8. A contact plug is formed
`
`in contact hole 12 for making electrical contact to the diffusion region 7. The contact plug in contact
`
`hole 12 is insulated from the gate electrode 4 by the insulating layer 8 and the side-wall oxide 6.
`
`Therefore Nishigoori does not disclose or suggest a plug contacting and providing
`
`electrical communication between a polysilicon gate electrode and a difiusion region. Consequently,
`
`Nishigoori does not anticipate the present invention.
`
`Therefore, withdrawal of the rejection of claims 1~l2 under 35 USC §lO2(b) in view
`
`of Nishigoori ‘2l0 is respectfully requested.
`
`Based on the foregoing, it is respectfully submitted that all of the pending claims in
`
`the present application are in condition for allowance and such action at an early date is respectfully
`
`solicited.
`
`

`
`The Examiner is respectfiilly invited to call the applicant’s representative at his Detroit,
`
`Michigan Ofiice at (313) 962-4790 should it be desirable to do so to expedite allowance of the
`
`present application.
`
`Respectfully submitted,
`
`BARNES, KISSEL
`WHITT
`O
`
`
`
`‘
`
`RAISCH, CHOATE,
`& HULBERT, P.C.
`
`By:
`
`___,‘
`
`dy W. Tung
`Registration No. 31, 311
`Telephone: (313) 962-4790
`
`RWT:bp

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