U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`DOCKET NO.: 54918.6
`Filed on behalf of Qualcomm and GlobalFoundries
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`By: David M. O’Dell, Reg. No. 42,044
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`David L. McCombs, Reg. No. 32,271
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`
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________________
`
`QUALCOMM INCORPORATED, GLOBALFOUNDRIES INC.,
`GLOBALFOUNDRIES U.S. INC., GLOBALFOUNDRIES DRESDEN
`MODULE ONE LLC & CO. KG, GLOBALFOUNDRIES DRESDEN MODULE
`TWO LLC & CO. KG
`Petitioner
`
`
`v.
`
`DSS Technology Management, Inc.
`Patent Owner
`
`Case IPR2016-01312
`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 5,965,924
`CHALLENGING CLAIMS 7-12, 15 and 17
`UNDER 35 U.S.C. § 312 AND 37 C.F.R. § 42.104
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`TABLE OF CONTENTS
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`I. 
`Introduction ........................................................................................................ 1 
`II.  Mandatory Notices ............................................................................................. 5 
`A.  Real Party-in-Interest .................................................................................... 5 
`B.  Related Matters .............................................................................................. 6 
`C.  Counsel .......................................................................................................... 6 
`III.  Certification of Grounds for Standing .............................................................. 7 
`IV.  Overview of Challenge and Relief Requested ................................................. 7 
`A.  Prior Art Patents ............................................................................................ 7 
`B.  Grounds for Challenge .................................................................................. 7 
`V.  Brief Description of Technology ....................................................................... 8 
`A.  Overview of Transistor Fabrication .............................................................. 8 
`1.  Basic Structure of Transistors .................................................................... 8 
`2.  Formation of Transistor Components ........................................................ 9 
`3.  Local Interconnects .................................................................................. 11 
`B.  Overview of the ’924 Patent ........................................................................ 12 
`1.  Alleged Problem ....................................................................................... 13 
`2.  Summary of Alleged Invention of the ’924 Patent .................................. 15 
`3.  The Challenged Claims ............................................................................ 16 
`4.  Prosecution History .................................................................................. 17 
`VI.  Overview of the Primary Prior Art References .............................................. 20 
`A.  Overview of Sakamoto ................................................................................ 20 
`B.  Overview of Cederbaum ............................................................................. 22 
`VII.  Claim Construction ...................................................................................... 24 
`A. 
`“diffusion region in a silicon substrate” ...................................................... 24 
`VIII.  Level of Ordinary Skill In The Art .............................................................. 28 
`IX.  Specific Grounds for Petition ......................................................................... 28 
`A.  Ground I: Claims 7-9, 15 and 17 are anticipated by Sakamoto ................. 28 
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`1. 
`Independent Claim 7 ................................................................................ 28 
`2.  Claim 8: “A method according to claim 7, wherein said diffusion region
`is an N+ or a P+ region.” ................................................................................. 45 
`3.  Claim 9: “A method according to claim 7, wherein said insulating
`material is selected from the group consisting of silicon oxide and silicon
`nitride.” ............................................................................................................ 45 
`4.  Claim 15: “A method according to claim 7, wherein said gate is a
`polysilicon gate.” / Claim 17: “The method according to claim 7, wherein said
`gate comprises polysilicon.” ............................................................................ 47 
`B.  Ground II: Claims 10-12 are obvious in view of the combination of
`Sakamoto and Cederbaum ................................................................................... 48 
`1.  Claim 10: “a method according to claim 7, wherein said electrically
`conducting plug is a metal plug” / Claim 11: “a method according to claim 7,
`wherein said electrically conducting plug is preferably a refractory metal
`plug” / Claim 12: “a method according to claim 7, wherein said electrically
`conducting plug is formed of a material selected from the group consisting of
`titanium, tantalum, molybdenum and tungsten” .............................................. 48 
`X.  Conclusion ....................................................................................................... 54 
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`Petitioner respectfully requests Inter Partes Review of claims 7-12, 15 and
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`17 of U.S. Patent No. 5,965,924 (the “’924 patent”) (Ex. 1101) pursuant to 35
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`U.S.C. §§ 311-19 and 37 C.F.R. § 42.1 et seq. The above-listed claims of the ’924
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`patent are presently the subject of a substantially identical petition for inter partes
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`review styled Intel Corporation v. DSS Technology Management, Inc., which was
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`filed December 8, 2015 and assigned Case No. IPR2016-00289. Petitioner will
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`seek joinder with that inter partes review under 35 U.S.C. § 315(c), 37 C.F.R. §§
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`42.22 and 42.122(b).
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`I. INTRODUCTION
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`The ’924 patent claims a purportedly novel method for manufacturing
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`transistors in semiconductors. But in fact, the claimed method merely duplicates a
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`well-known technique disclosed by Osamu Sakamoto and others nearly three years
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`before the alleged invention.
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`The ’924 patent is directed to certain aspects of the structure and fabrication
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`of transistors used in semiconductor and integrated circuit products such as
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`microprocessors and memory. Transistors act as microscopic switches that turn on
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`and off at extraordinarily high rates to enable aggregations of transistors (and other
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`components) to process data. Transistors are made up of various structures
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`including “contacts” that provide electrically conductive pathways into and out of
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`certain structures within a transistor, and which thereby are used to connect
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`1
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`transistors together. Declaration of Dr. Richard Blanchard (“Decl.”) ¶ 26 (Ex.
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`1102).
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`The ’924 patent is concerned with electrically connecting different transistor
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`parts to each other in a particular way. Transistors typically have three terminals
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`through which electrical signals may pass: a “source,” a “drain,” and a “gate.” The
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`’924 patent is concerned with connecting the gate of one transistor to, for example,
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`the source or drain of a neighboring transistor. Decl. ¶ 27 (Ex. 1102).
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`As the specification of the ’924 patent admits, there were many well-known
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`ways of making electrical connections between different transistor parts. As
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`shown in Figure 2B (below), for instance, one of the admitted prior art ways of
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`connecting the components of two transistors was by using two electrical
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`connections called “plugs”—one connected to the gate of one transistor, and the
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`other connected to the source or drain of the other—and then connecting those
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`plugs together. As shown in Figure 3B (below), the purported invention of the
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`’924 patent was to replace the two plugs with one plug. Decl. ¶ 28 (Ex. 1102).1
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`1 All emphasis and annotations are added unless otherwise indicated.
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`2
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`Admitted Prior Art: Fig. 2B
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`Allegedly Novel Structure: Fig. 3B
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`In both the admitted prior art (Figure 2B) and the allegedly novel structure
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`of the ’924 patent (Figure 3B), the gate is connected to a diffusion region (i.e., a
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`source or drain) by either two connected plugs, or a single plug. The patent does
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`not claim that the one-plug structure provides any performance benefits over the
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`two-plug structure. Instead, the only purported benefit was that the one-plug
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`structure was easier to manufacture than the admitted prior art. ’924 patent at
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`1:57-2:63, 4:18-5:12 (Ex. 1101); Decl. ¶ 29 (Ex. 1102).
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`But long before the ’924 patent’s November 22, 1995 priority date,2 many
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`others had already developed and used the exact same one-plug structure. U.S.
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`Patent No. 5,475,240 (“Sakamoto”), for instance, which has an effective filing date
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`of March 4, 1992, discloses the same one-plug structure that the ’924 patent
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`contends is novel. Specifically, as shown in the patents’ respective figures, the
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`one-plug structure of Sakamoto (Figure 1) is in all relevant aspects identical to the
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`one-plug structure of the ’924 patent (Figure 3B). Decl. ¶ 30 (Ex. 1102).
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`Sakamoto: Fig. 1
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`’924 Patent: Fig. 3B
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`As shown, both structures include a gate connected to a source or drain
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`2 The prior assignee claimed a conception date of May 17, 1995 during prosecution
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`of the ’924 application. Amendment and Rule 131 Declaration dated Jan. 5, 1998
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`(Ex. 1106). Even under that alleged conception date, the references relied upon by
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`Petitioner all qualify as prior art and invalidate the ’924 patent.
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`through a single plug. Decl. ¶ 31 (Ex. 1102).
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`Similarly, U.S. Patent No. 5,100,817 (“Cederbaum”) issued on March 31,
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`1992, and, just like the ’924 one-plug structure, discloses a single conducting plug
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`connecting a gate to a source or drain. Decl. ¶ 32 (Ex. 1102).
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`Cederbaum: Fig. 7
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`These prior art references, which were not at issue during prosecution of the
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`’924 patent, anticipate and/or render obvious claims 7-12, 15 and 17 of the ’924
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`patent. Decl. ¶ 33 (Ex. 1102).
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`II. MANDATORY NOTICES
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`A. Real Party-in-Interest
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`Qualcomm Incorporated and GLOBALFOUNDRIES Inc.,
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`GLOBALFOUNDRIES U.S. Inc., GLOBALFOUNDRIES Dresden Module One
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`LLC & Co. KG, GLOBALFOUNDRIES Dresden Module Two LLC & Co. KG
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`(collectively “Petitioner”) are the real party-in-interest.
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`B. Related Matters
`DSS has asserted the ’924 patent in two separate proceedings: (1) DSS Tech.
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`Mgmt., Inc. v. Intel Corp. et al., Civil Action No. 6:15-CV-130-RWS (E.D. Tex.
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`2015); and (2) DSS Tech. Mgmt., Inc. v. Qualcomm Inc., Civil Action No. 6:15-
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`CV-692-JRG (E.D. Tex. 2015). These proceedings may be affected by a decision
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`in this instant proceeding.
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`The ’552 patent is currently being challenged before the Board in the
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`following cases: Intel Corporation v. DSS Technology Management, Inc.,
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`IPR2016-00289 and 00290. Also, the Petitioner is filing a separate inter partes
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`review petition for claims 1-6, 13, 14 and 16 of the ’924 patent.
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`C. Counsel
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`Lead Counsel
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`Back-up Counsel
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`David M. O’Dell
`HAYNES AND BOONE, LLP
`2323 Victory Ave. Suite 700
`Dallas, TX 75219
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`Phone: (972) 739-8635
`Fax: (214) 200-0853
`david.odell.ipr@haynesboone.com
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`USPTO Customer No. 27683
`USPTO Reg. No. 42,044
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`Please address all correspondence to lead and back-up counsel. Petitioner
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`David L. McCombs
`HAYNES AND BOONE, LLP
`2323 Victory Ave. Suite 700
`Dallas, TX 75219
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`Phone: (214) 651-5533
`Fax: (214) 200-0853
`david.mccombs.ipr@haynesboone.com
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`USPTO Customer No. 27683
`USPTO Reg. No. 32,271
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`also consents to electronic service by email.
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`III. CERTIFICATION OF GROUNDS FOR STANDING
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`Petitioner certifies pursuant to Rule 42.104(a) that the patent for which
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`review is sought is available for inter partes review and that Petitioner is not
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`barred or estopped from requesting an inter partes review challenging the patent
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`claims on the grounds identified in this Petition.
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`IV. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
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`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)-(2), Petitioner challenges
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`claims 7-12, 15 and 17 of the ’924 patent.
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`A. Prior Art Patents
`Petitioner relies upon the patents listed in the Table of Exhibits, including:
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`1.
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`U.S. Pat. No. 5,475,240 (“Sakamoto” (Ex. 1103)), which was filed on
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`August 19, 1994, as continuation of an earlier filed application filed on March 4,
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`1992, and issued on December 12, 1995. Sakamoto is prior art under 35 U.S.C. §
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`102(e).
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`2. U.S. Pat. No. 5,100,817 (“Cederbaum” (Ex. 1104)), which was issued
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`on March 31, 1992, is prior art under 35 U.S.C. §§ 102(b).
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`B. Grounds for Challenge
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`Petitioner requests cancellation of claims 7-12, 15 and 17 of the ’924 patent
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`as unpatentable under 35 U.S.C. § 102 and § 103. This Petition, supported by the
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`declaration of Dr. Richard Blanchard (Ex. 1102) filed herewith, demonstrates that
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`there is a reasonable likelihood that Petitioner will prevail with respect to
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`cancellation of at least one challenged claim. See 35 U.S.C. § 314(a).
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`V. BRIEF DESCRIPTION OF TECHNOLOGY
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`The ’924 patent generally relates to the field of semiconductor integrated
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`circuit manufacturing and claims particular structures for transistors in
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`semiconductors, as well as a related method for manufacturing those structures.
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`Decl. ¶ 34 (Ex. 1102).
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`A. Overview of Transistor Fabrication
`1. Basic Structure of Transistors
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`Semiconductor integrated circuits, such as microprocessors and computer
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`memory, are typically made up of hundreds of millions (and in some cases billions)
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`of microscopic structures called transistors. Transistors act as microscopic
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`switches that turn on and off at extraordinarily high rates to enable aggregations of
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`transistors (and other components) to process data. Decl. ¶ 35 (Ex. 1102).
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`As shown in the figure below, transistors typically include three primary
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`“electrodes” or “terminals”—a “gate,” a “source,” and a “drain.” Decl. ¶ 36 (Ex.
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`1102).
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`The source and drain regions (also referred to as “diffusion regions”) are
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`transistor components that emit (source) and receive (drain) current when the
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`transistor is “on.” The gate typically sits between the source and drain and is a
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`terminal that can have a voltage applied to it that in turn causes a current to flow
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`between the source and drain. As of the time of the invention of the ’924 patent,
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`the source and drain of a transistor were typically formed in the surface of a
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`semiconductor “substrate,” while the gate typically sat above the substrate and
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`separated from it by a thin layer of insulator (“gate oxide”). Decl. ¶ 37 (Ex. 1102).
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`2. Formation of Transistor Components
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`Transistor fabrication typically starts with a silicon substrate. In typical
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`planar transistors, the source and drain regions (“diffusion regions”) are created by
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`implanting regions of the substrate with ions (charged atomic particles) of different
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`materials—called “dopants” or “impurities”—to make those regions conductive.
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`(Once implanted the ions become neutral atoms). This process—referred to as
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`“doping” because it dopes the silicon substrate with atomic particles that have
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`additional charge carriers—is shown below. Decl. ¶ 38 (Ex. 1102).
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`Structures can then be formed above the substrate by depositing layers of
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`other materials onto the substrate. A gate electrode, for example, is formed by first
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`growing or depositing a “gate oxide” (an insulator) on the substrate followed by
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`depositing a conductive material (metal or polysilicon) on top of the gate oxide.
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`The conductive material acts as the gate, and the gate oxide creates a layer of
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`isolation between the gate and the source/drain regions (“S/D regions” or
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`“diffusion regions”). Decl. ¶ 39 (Ex. 1102).
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`Insulating materials may then be deposited around and over the gate and the
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`source/drain regions to maintain electrical isolation where desired. Sidewall
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`spacers, for instance, can be formed on each side of the gate electrode as shown
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`below.
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`10
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`As was known as of the time of the alleged ’924 invention, such sidewall spacers
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`help to prevent direct electrical contact between the gate electrode and nearby
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`components and thus help to prevent short-circuits. Decl. ¶ 40 (Ex. 1102).
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`3. Local Interconnects
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`Many transistors can be connected together to form electronic circuits. For
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`certain types of circuits, it is sometimes useful to connect the gate of one transistor
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`to a diffusion region (the source or drain) of a nearby transistor. This type of
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`connection is called a “local interconnect,” because connections are made locally
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`between nearby transistors. Decl. ¶ 41 (Ex. 1102).
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`As the specification of the ’924 patent concedes, a variety of different types
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`of local interconnects were well-known prior to the purported invention. For
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`example, as shown in Figure 1B of the ’924 patent, one well-known way to form a
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`local interconnect was to position the gate in a location where it physically touches
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`the diffusion region on one side, creating an electrical connection. As shown in
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`Figure 2B of the ’924 patent, another well-known way to make a local interconnect
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`was to place one electrically conductive “plug” above the gate and another “plug”
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`above the diffusion (e.g., source or drain) region, and then electrically connect the
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`two plugs together. Decl. ¶ 42 (Ex. 1102).
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`Admitted Prior Art: Fig. 1B
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`Admitted Prior Art: Fig. 2B
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`The ’924 patent acknowledges that both examples were known prior art. See
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`’924 patent at Figs. 1A, 1B, 2A, 2B, 1:25-2:45, 3:30-35 (Ex. 1101); Decl. ¶ 43 (Ex.
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`1102).
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`B. Overview of the ’924 Patent
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`The ’924 patent issued from U.S. App. No. 08/900,047, which was filed on
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`July 24, 1997, and claims priority to an application filed on November 22, 1995.
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`’924 patent at cover page (Ex. 1101). The purported invention of the ’924 patent is
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`a single plug to connect different transistor parts. ’924 patent at 2:32-67, 4:18-5:12
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`(Ex. 1101); Decl. ¶ 44 (Ex. 1102).
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`1. Alleged Problem
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`The ’924 patent purports to address manufacturing inefficiencies in forming
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`local interconnects. Figures 1 and 2 of the ’924 patent are admitted prior art and
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`show examples of two well-known types of local interconnects that (according to
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`the ’924 patent) are inefficient to manufacture. Decl. ¶ 45 (Ex. 1102).
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`Figure 1B shows a “buried contact” local interconnect structure in which the
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`gate directly touches—i.e., is in direct electrical connection with—a diffusion
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`region. According to the ’924 patent, the problem with this structure is that the
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`gate has to be implanted with the same type of impurities as those implanted in the
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`diffusion region. See ’924 patent at 1:57-2:11 (Ex. 1101). But most manufacturers
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`use a variety of different types of impurities in different transistors. To use the
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`“buried contact” approach, a manufacturer would have to ensure that any two
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`transistors connected using this approach use the same impurities, which
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`complicates the manufacturing process. See id.; see also Decl. ¶ 46 (Ex. 1102).
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`Admitted Prior Art: Fig. 1B
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`Admitted Prior Art: Fig. 2B
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`Figure 2B shows another prior art local interconnect structure, using what is
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`called a “strapping” technique. To form this “strapping” local interconnect
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`structure, a manufacturer creates two electrically conductive plugs (numbers 44
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`and 46)—one above the gate and one above a diffusion region. The manufacturer
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`then places an electrically conductive “local strap” (number 50) on top of the
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`plugs, electrically connecting the two plugs together. This local strap is also
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`sometimes called a “shunt” or a “shunt layer.” In combination, the two plugs and
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`the local strap electrically connect the gate to a diffusion region. See ’924 patent at
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`2:12-32 (Ex. 1101). According to the ’924 patent, the problem with the strapping
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`technique is that it requires a large number of manufacturing process steps, as well
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`as significant space to accommodate the two plugs and the local strap. See ’924
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`patent at 2:33-41 (Ex. 1101); see also Decl. ¶ 47 (Ex. 1102).
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`2. Summary of Alleged Invention of the ’924 Patent
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`The ’924 patent’s claimed structure includes nearly identical components as
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`the admitted prior art described in the specification. Decl. ¶ 48 (Ex. 1102).
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`Specifically, both the claimed structure and the admitted prior art include a
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`substrate, a gate, a diffusion region, a sidewall spacer adjacent to the gate, and an
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`insulating material. Decl. ¶ 48 (Ex. 1102).
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`Admitted Prior Art: Fig 2B
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`Preferred Embodiment: Fig 3B
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`As shown in Figures 2B and 3B, in both the admitted prior art of the ’924
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`patent and the allegedly novel structure, the gate is connected to the diffusion
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`region (source or drain), by either two connected plugs, or a single plug. The
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`diffusion region is located in a substrate and is not directly connected to the gate.
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`The gate is substantially covered by an insulating material. Decl. ¶ 49 (Ex. 1102).
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`The patent’s only alleged novelty—shown in Figure 3B—is the use of a
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`single metal plug to connect the gate and the diffusion region, rather than
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`connecting the two components directly (as in the prior art “buried contact”
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`technique (Figure 1B)) or using two plugs (as in the prior art “strapping” technique
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`(Figure 2B)). ’924 patent at 2:64-67, 3:35-36 (describing Figure 3B as “a cross-
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`sectional view of a preferred embodiment of the present invention.”), 4:18-5:12,
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`claims 1, 7 (Ex. 1101); see also id. at 2:42-63; Decl. ¶ 50 (Ex. 1102).
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`But as explained below, there is nothing novel about using a single
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`conducting plug.
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`3. The Challenged Claims
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`This petition challenges claims 7-12, 15 and 17 of the ’924 patent.
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`Independent claim 7 describes a method of forming a local interconnect in a
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`semiconductor structure, in which a plug provides a direct electrical connection
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`between a diffusion region formed in a substrate and a gate formed on top of the
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`substrate. ’924 patent at claim 7 (Ex. 1101). Claim 7 also specifies additional well
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`known features, including a sidewall spacer and insulating material on the gate, as
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`noted below.
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`7. A method of forming a local interconnect in a semiconductor
`structure, comprising the step of:
`[a] depositing an electrically conducting material in a via
`exposing at least a portion of a gate, a sidewall spacer adjacent to said
`gate and a portion of a diffusion region such that said electrically
`conducting material contacts and provides electrical communication
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`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
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`between said gate and said diffusion region,
`[b] said semiconductor structure comprising said diffusion
`region in a silicon substrate,
`[c] said gate being on said substrate juxtaposed to but not
`contacting said diffusion region,
`[d] said sidewall spacer being disposed above said diffusion
`region,
`[e] said via being in an insulating material on said gate.
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`The dependent claims add well-known implementation details such as
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`defining particular types of diffusion regions (id. at claim 8), insulating material
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`(id. at claim 9), conducting plug material (id. at claims 10-12), and gate material
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`(id. at claims 15, 17).
`
`4. Prosecution History
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`The ’924 patent issued from a “continued prosecution application” (“CPA”)
`
`of U.S. App. No. 08/561,951. CPA Request dated Feb. 10, 1999 (Ex. 1105).
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`During prosecution of the ’924 patent, the Applicant purportedly antedated a prior
`
`art reference, based on a lab notebook dated May 17, 1995. Amendment and Rule
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`131 Declaration dated Jan. 5, 1998 (Ex. 1106). For purposes of this Petition, the
`
`references relied upon by Petitioner all qualify as prior art even if the Patent Owner
`
`could ultimately prove a conception date as early as May 17, 1995. Decl. ¶ 51 (Ex.
`
`1102).
`
`17
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`

`

`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
`
`
`
`
`According to this lab notebook, the purported novelty of the ’924 invention
`
`
`
`arises from the use of a single plug—which is what allegedly leads to fewer
`
`processing steps as compared to known prior art techniques. See Rule 131
`
`Declaration dated January 5, 1998, Exhibit A (“By placing a metallic plugged
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`contact where poly is required to shunt to diffusion, contacts to [different types of]
`
`diffusion can be achieved …. [T]his will require no more layout area than the
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`traditional buried contact. This method has potential [manufacturing] process step
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`savings of 8-11 steps over Trad. BC [traditional buried contact local interconnect
`
`(as shown in Figure 1B of the ’924 patent)] and 6-8 steps over strapping [local
`
`interconnect (as shown in Figure 2B of the ’924 patent)].”) (Ex. 1106). Decl. ¶ 52
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`(Ex. 1102).
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`However, during prosecution, rather than relying on the supposedly novel
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`“single plug” structure, the Applicant relied on other alleged differences to
`
`overcome the prior art applied by the Examiner. The present petition relies on new
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`art—not before the Examiner—that teaches not only the allegedly novel “single
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`plug” aspect of the invention, but also all of the additional minor differences that
`
`the Applicant used to allegedly distinguish the Examiner’s prior art. Decl. ¶ 53
`
`(Ex. 1102).
`
`18
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`

`

`
`
`
`
`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
`
`
`
`a) The “sidewall spacer” limitations
`
`The Examiner rejected the original claims under 35 U.S.C. § 102(e) based
`
`on U.S. Patent No. 5,451,434 to Nicholls (“Nicholls”). Office Action dated Nov.
`
`7, 1996 at p. 3 (Ex. 1107). Nicholls taught a single metal plug that connects a
`
`diffusion region and a gate. In order to overcome the rejection, the Applicant
`
`added a limitation to the claims requiring a sidewall spacer adjacent to the gate.
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`Amendment dated June 9, 1997 at pp. 2-3 (Ex. 1109). Nicholls expressly teaches
`
`the placement of a sidewall during manufacture, but also teaches that the sidewall
`
`can be completely or “partially removed” in a later manufacturing step. Nicholls at
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`4:25-32 (Ex. 1108). The Applicant overcame the rejection by arguing that the
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`removal of the sidewall during manufacturing taught away from retaining a
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`sidewall spacer adjacent to the gate. Amendment dated June 9, 1997 at pp. 3-4
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`(Ex. 1109). The prior art relied upon in this petition teaches the “sidewall spacer”
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`limitation. Decl. ¶ 54 (Ex. 1102).
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`b) Direct electrical connection
`
`The Examiner also rejected the claims under 35 U.S.C. § 102(e) based on
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`U.S. Patent No. 5,541,427 to Chappell (“Chappell”). Office Action dated February
`
`24, 1998 (Ex. 1110). Chappell taught a single metal plug that connects to both a
`
`diffusion region and a gate region. Chappell at 4:38-48 (Ex. 1111). The Applicant
`
`overcame the rejection by arguing that the metal plug of Chappell purportedly
`
`19
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`

`

`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
`
`
`
`
`
`contacts a portion of the gate region that is not conductive, rather than the
`
`conductive portion of the gate itself. See Amendment dated April 23, 1998 at p. 4
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`(“‘when the opening 42 is filled with an electrically conductive material, there is
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`no contact to the electrically conductive portion of the gate stack’”) (emphasis in
`
`original) (quoting Chappell at 4:38-48) (Ex. 1112). The prior art references relied
`
`upon in this petition teach a direct electrical connection between the diffusion
`
`region and the electrically conductive portion of the gate. Decl. ¶ 55 (Ex. 1102).
`
`VI. OVERVIEW OF THE PRIMARY PRIOR ART REFERENCES
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`The claimed invention of the ’924 patent—using a single plug to electrically
`
`connect the gate to the diffusion region—was well-known as of the May 17, 1995
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`purported conception date. Decl. ¶ 56 (Ex. 1102). Each of the prior art references
`
`relied upon in this petition has an effective filing date earlier than that alleged
`
`conception date.
`
`A. Overview of Sakamoto
`
`Sakamoto was filed on August 19, 1994, as a continuation of an earlier
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`application filed on March 4, 1992, and issued on December 12, 1995. It is
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`therefore prior art to the ’924 patent under 35 U.S.C. § 102(e). Decl. ¶ 57 (Ex.
`
`1102).
`
`Sakamoto is directed to precisely the same problem as the ’924 patent—how
`
`to effectively and efficiently connect different transistor portions together —and
`
`20
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`

`

`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
`
`
`
`
`
`discloses precisely the same solution claimed in the ’924 patent—using a single
`
`plug. Sakamoto at 4:45-49 (“The first interconnection structure comprises a
`
`silicon plug layer embedded within an opening formed in the interlevel insulating
`
`layer and connected to both gate electrode of the first MOS drive transistor and
`
`source/drain region of the second MOS transfer transistor…”) (Ex. 1103); see also
`
`id. at 1:13-14. Figure 1 of Sakamoto shows a structure with the same components
`
`arranged in the same way as shown in Figure 3B of the ’924 patent. Id. at Fig. 1;
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`’924 patent at Fig. 3B (Ex. 1101); Decl. ¶ 58 (Ex. 1102).
`
`Sakamoto: Fig. 1
`
`’924 Patent: Fig. 3B
`
`
`
`Both Figure 1 of Sakamoto and Figure 3B of the ’924 patent show a cross-
`
`sectional structure with a single plug. The plug fills an opening (labeled 16 in
`
`Sakamoto) containing a sidewall spacer and directly electrically connects a
`
`diffusion region to a gate. The diffusion region is located in a substrate and is not
`
`21
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`

`U.S. Patent No. 5,965,924 Claims 7-12, 15 and 17
`Petition for Inter Partes Review
`
`
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`
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`directly connected to the gate. The gate is also substantially covered by an
`
`insulating material. See Sakamoto at 6:52-58 (“An opening 16 is formed in an
`
`interlevel insulating layer 9. An n+ source/drain region 7 of an n channel MOS
`
`transfer transistor 22b and a gate electrode 6 of an n channel MOS drive transistor
`
`20a are exposed at the bottom of opening 16. A plug layer 15 of polycrystalline
`
`silicon directly connected to the n+ source/drain region 7 and gate electrode 6 is
`
`embedded within opening 16.”), 7:47-51 (“An opening 16 for direct contact is
`
`formed in interlevel insulating layer 9 … formation of the opening 16 leaving a
`
`sidewall spacer 9' from the interlevel insulating layer 9 …”), 7:26-27 (“Oxide films
`
`5 form gate