Ting P. Yen
`
`Serial No.:
`
`as/900,047
`
`/ /
`
`Title:
`
`Filed:
`
`METAL PLUG LOCAL INTERCONNECT
`
`July 24, 1997
`
`Attorney Docket No.:
`
`O325.00l24
`
`Examiner:
`
`Art Unit:
`
`V. Wallace
`
`2503
`
`In Response To:
`
`Office Action mailed October 3, 1997
`
`RESPONSE
`
`Assistant Commissioner for Patents
`
`Washington, D.C. 20231
`
`Sir:
`
`In response to the Office Action mailed October 3, 1997,
`
`please consider the following remarks regarding the above—captioned
`
`patent application.
`
`R E M A R K §
`
`The presently claimed invention concerns a semiconductor
`
`structure comprising a silicon substrate having a top surface, a
`
`diffusion region formed in said substrate adjacent
`
`to said top
`
`1
`
`HVTIHQIIO6
`
`
`
`

`
`surface,
`
`a polysilicon gate formed on the top surface of
`
`the
`
`substrate juxtaposed to but not contacting said diffusion region,
`
`a sidewall spacer adjacent
`
`to the polysilicon gate and disposed
`
`above
`
`the diffusion region,
`
`an insulator
`
`layer substantially
`
`covering the polysilicon gate and the diffusion region,
`
`and a
`
`conducting plug at least partially filling a via in said insulation
`
`layer that exposes
`
`the sidewall
`
`spacer
`
`in the absence of
`
`the
`
`conducting plug.
`
`The conducting plug provides direct electrical
`
`communication between the polysilicon gate and.
`
`the diffusion
`
`region.
`
`Re'ect on Under 3 U.S.C.
`
`02
`
`The rejection of claims 3-6, 9-14 and 16-17 under 35
`
`U.S.C.
`
`§
`
`lO2(e) as being anticipated by Sugiyama U.S. Patent No.
`
`5,600,170 is respectfully traversed.
`
`. As evidenced by the attached Declaration (the executed
`
`version of which will be filed at
`
`the earliest opportunity)
`
`the
`
`present
`
`invention was conceived prior
`
`to the filing date of
`
`Sugiyama. Therefore,
`
`this ground of rejection is unsustainable,
`
`and should be withdrawn.
`
`
`
`

`
`REJECTIONS UNDER 35 U.S.C. 103
`
`The rejection of Claims 2,
`
`8 and 15 under 35 U.S.C.
`
`§
`
`103(a) as being unpatentable over Sugiyama et al.
`
`in View of Jones,
`
`Jr.
`
`(U.S. Patent No. 5,313,089) has been obviated in View of the
`
`attached Declaration under 37 C.F.R. 1.131 and should.be withdrawn.
`
`Jones alone does not render the presently pending claims
`
`2,
`
`8 and 15 obvious.
`
`Jones discloses a capacitor and memory cell
`
`formed therefrom. Nothing disclosed by Jones describes or suggests
`
`the via recited in the present claims. Therefore this ground of
`
`rejection should be withdrawn.
`
`Accordingly,
`
`the present application is in condition for
`
`allowance.
`
`Early and
`
`favorable action by
`
`the Examiner
`
`is
`
`respectfully solicited.
`
`

`
`Received:
`
`1/ 5/96 4:08PM;
`
`-> BLISS MCGLYNN, F'.(:_;
`
`Page 10
`
`Sent by: BLISS McGLYNN,
`
`r-ac.
`
`2451 me 6299;
`
`01105193
`
`,.s5PM;Jedix #18
`
`page 3/10
`
`The Examiner
`
`is respectfully invited to call
`
`the
`
`Applicant’:
`
`representative hould it be deemed benef1c1a,1 to
`
`turther advance prosecution of the application.
`
`If any additional fees are due, please charge our Deposit
`
`Account No. 02-2712.
`
`
`
`2075 Wee Big Beaver Road, Suite 600
`Troy,
`48084-3443
`(243) 649-6090
`
`Dated: dlanuggg 5
`
`1§2§
`
`Docket No. : 0325 . 001.24
`
`Iheteby certify that ads later. the response or aunendmeu attached harem an: bebg dewsiwd with the United States
`pom; Sgfviue u fin; cm; man in an envelope addrused wAssimnt Commissioner for Patents, Washlngmn, DC.
`20231, on _1anmnL.LJ.2E& -
`
`
`
`Respect ful ly submitted,
`
`BLISS MCGLYNN. P . C .
`
`‘fir-h““f;fl"D7
`55?.
`
`V-9 -No. 34', 600
`
`

`
`HBCSLVSUI
`
`1/ 5/98
`
`4:08PM-
`’
`
`-> BLISS MCGLYNN, F'.C.;
`
`Page 11
`
`T Sent "by: sues McG'_¥NN, ms.
`i’
`
`243 349 e299;
`
`o1/05/as 7
`
`Page 7110
`5PM;Je¢fix we
`é*/74% 2505
`
`D8l900.047 ur REQUIRED)
`
`IN RE APPUCAT1ON OF:
`SERIAL NUMBER:
`
`Ting P. Yuri
`
`FILED:
`
`Eon:
`ART um‘;
`
`my 24. 1997
`
`METAL PLUG LOCAL INTERCONNECT
`2:03
`
`'
`
`Attorney Docket: 0325190121
`
`imusurmu mo
`RESPONSE
`EXTENSION 01-‘ TIME REQUF: 3'!‘
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`
`EXAMINER:
`
`Wallace, v.
`
`ASSISTANT COMMISSIONER FOR PATENTS
`Waahinguan, DC. 2023!
`
`V T
`
`OTAL IF NOT SMALL ENTITY 5
`
`[L00
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`
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`
`SMALL EN'I'l'l'Y STATUS -, If applicable. divide, by 2 .
`Verified statement enclosed, If not previously filed.
`
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`Applicant also requests a
`for response to [be outstanding Office Action. The tee is .
`
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`Fee set farm in 37 C.F.R. 1.17 (p) for Information Disclosure
`1.md::r37 C.F.R. 1.97 (c).
`.
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`TOTAL FEE .
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`The Commissioner is hereby authorized to charge any overpayment or underpayment of the above fee associate d with this
`Cormaumication Io Deposit Account No. 02-2712. A duplicate copy of thin sheet Ls attached.
`
`2075 w. Big Beavei-,&1i1e600
`Troy. MI 48084-3443
`(268) 649-6090
`
`-
`
`By
`
`BLISS McGLYNN, 1=.c.
`
`Luis M|gue1Acnsra
`Reg Nun _i2.1§.7_..
`
`A161”.-D. 5,+,\‘7’ ?h-D.’ E52.
`_._?'il' ‘W’
`('31-! gm’
`
`I hereby certify that Lhla letter. the reaponse or amendment auachcd hereto are being deposited with the United Szatcs Poem).
`Service as rm: clasa mail in an envelope addressed to Assistant Commissioner for Patents. Wuhington. D.C. 20231. on
` -
`
`By;
`
`ulia A. Barber
`
`
`
`

`
`:5
`14/?
`
`TRANSMITTAL
`
`RECEWED
`FEB 0 6 7993
`
` Art Unit:
`
`)
`2503
`3
`Wallace, V.
`Examiner:
`5
`App1icant(s): Ting P. Yen
`i
`Serial No.:
`08/900,047
`;
`Filing Date:
`July 24, 1997
`For:
`METAL PLUG LOCAL INTERCONNECT %
`
`Assistant Commissioner for Patents
`
`Washington, D.C. 20231
`
`Sir:
`
`Enclosed is an executed Declaration of Jeff Watt Under 37
`
`C.F.R. 1.131, Exhibit A, and Jeff Watt's curriculum vitae.
`
`Respectfully submitted,
`
`BLISS MCGLYNN, P . C .
`
`
`
`Christoph 1: P. Maiorana
`Registration No. }?-42,829
`2075 West Big Beaver Road, Suite 600
`Troy, MI
`48084-3443
`(248) 649-6090
`
`Dated:
`
`Jangary 29, 1998
`
`Docket No.: O325.00124
`
`I hereby certify that this eorrespondence is being deposited with theUnited States Postal Service as first class mail
`in an envelope addressed to Assistant Commissioner for Patents, Washington, D.C. 20231, on 8.
`
`By:
`
`.
`
`Julie A. Barber
`
`

`
`
`
`:tfi/Q
` ..
`I)
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`2503
`) J
`)
`
`0
`
`Art Unit:
`
`Declaration of Jeff Watt
`Under 37 C.F.R. 1.131
`'
`
`) )
`
`)
`)
`)
`)
`
`) )
`
`Examiner:
`
`Wallace, V.
`
`Applicant(s): Ting P. Yen
`
`Serial No.2
`
`08/900,047
`
`Filing Date:
`
`July 24, 1997
`
`METAL PLUG LOCAL INTERCONNECT)
`For:
` )
`
`Assistant Commissioner for Patents
`
`Washington, D.C. 20231
`
`Dear Sir:
`
`I, Jeffrey Watt, hereby declare and state:
`
`1.
`
`2.
`
`My curriculum vitae is attached hereto as Appendix 14
`
`Ihave been employed by Cypress Semiconductor Corporation since fix} where
`
`my current job title is fiEHBEL (Q-’—' TECHNICA L
`
`S'7‘4FF.
`
`3.
`
`I have read the above—identified patent application and the subsequent amendment
`
`to the claims thereto filed on June 9, 1997. I understand the contents of said patent application and
`
`said amendment.
`
`

`
`4.
`
`I understand that the invention claimed in the above—identified patent application
`
`concerns:
`
`(A)
`
`a semiconductor structure comprising:
`
`a silicon substrate having a top surface,
`
`a diffusion region formed in the substrate adjacent to the top surface,
`
`a polysilicon gate formed on the top surface of the substrate juxtaposed to, but not
`
`contacting, the diffusion region,
`
`a sidewall spacer adjacent to the polysilicon gate and disposed above the diffitsion
`
`region,
`
`and
`
`an insulator layer substantially covering the polysilicon gate and the diffusion region,
`
`a conducting plug at least partially filling a via in the insulation layer that exposes the
`
`sidewall spacer in the absence of the conducting plug, the conducting plug providing direct electrical
`
`communication between the polysilicon gate and the diffiision region; and
`
`(B)
`
`a method of forming a local interconnect in a semiconductor structure,
`
`comprising the step of:
`
`depositing an electrically conducting material in a via exposing at least a portion of
`
`a gate, a sidewall spacer adjacent to the gate and a portion of a diffusion region such that the
`
`electrically conducting material contacts and provides electrical communication between the gate
`
`and the diffusion region, the semiconductor structure comprising the diffusion region in a silicon
`
`substrate, the gate being on the substrate juxtaposed to but not contacting the diffusion region, the
`
`2
`
`

`
`sidewall spacer being disposed above the diffusion region, the via being in an insulating material on
`
`the gate.
`
`5.
`
`Prior to June 7, 1995, I witnessed, read and understood an Invention Disclosure Form
`
`(copy attached hereto as Exhibit A) describing the subject matter claimed in the above-identified
`
`patent application.
`
`6.
`
`In my opinion, the Invention Disclosure Form that I witnessed describes the claimed
`
`invention and conveys information sufficient to enable one skilled in the relevant art to make and
`
`use the claimed invention.
`
`7.
`
`I declare that all statements made herein of my own knowledge are true and that all
`
`statements made on information and belief are believed to be true; and further that these statements
`
`were made with the knowledge that willful false statements and the like so made are punishable by
`
`fine or imprisonment, or both, under Section 1001 of Title 18 of the United States Code and that
`
`such willful false statements may jeopardize the validity of this application orany patent issuing
`
`thereon.
`
`Date
`
`

`
`
`EKr-l I 3 IT 5}
`_
`,
`Metal Plug_Local Shunt Patent Disclosure
`
`j "maven
`
`Invention Objective:
`The purpose of this invention is to provide a cheaper method of strapping transistor gates to both N+ &
`P+ diifusion by using metal plugs which are, in general, already designed into sub-metal contacts. By
`employing the contact plugs for strapping purpose no additional process steps are necessary.
`
`Current Method:
`
`In order to strap from gate poly to both N+ and P+ diffusion using traditional buried contacts requires
`a complex set of process additions. The reason for this is that gate poly requires to be doped both P+
`and N+, depending on the diffusion doping the poly is strapping to. Further more to minimize inter-
`di.fi'usion between N+ and P+ doping in poly, extra process steps are required to lower difliisivity. This
`is even more diflicult as design rules are scaled to deep sub-micron range. Other disadvantages are:
`- to avoid dopant penetration into channel region, P+ doped poly needs to be implanted with very low
`energy B11 instead of BF2 (to avoid F+ enhanced dopant diifusion); poor manufacturability.
`- For salicided poly: WSix case: this approach does not allow in-situ deposited doped poly/WSix
`Tisix case: this apprach makes it diflicnlt to match P+ doped and N+ doped polycide
`sheet resistance, plus where N+ and P+ poly is suppose to be connected
`as we have learned- there will be a BREAK in the polycide.
`'
`Other available method of strapping gate poly to both N+ and P+ diffusion:
`- another obvious method used today is to use a metallic local interconnect strap to shunt from the
`gate to difliision. However, this requires: 1) insulating layer between LI and gate 2) open via in insulator
`3) deposit LI layer 4) pattern LI layer. In addition from a topological point of view, this requires
`a lot more layout area than a buried contact at the intersection of gate to difiiision.
`
`New Method:
`
`(Assuming— sub-metal plugged contacts by design)
`By placing a metallic plugged contact where poly is required to shunt to diflusion, contacts to both 13+
`and N+ diffusion can be achieved independent of poly doping. Topologically, this will require no more
`layout area than the traditional buried contact. This method has potential process step savings of 8-11
`steps over Trad. BC and 6-8 steps over strapping Ll.
`
`
`Top View
`
`Traditional BC
`
`Met. Plug BC
`
`LI Strap '/A/////////A
`
`
`
`
`
`

`
`X—Section
`
`Traditional BC
`
`
`lllllllllllllll
`
`
`
`
`|l||||||||lH|||
`
`LI Strap
`
`lllllll
`
`
`
`
`
`
`Process Step Count:
`
`thin poly
`-1
`BC1 msk
`-1
`BC1 etch
`
`‘
`‘
`
`(BC irnpl msk)
`(BC P+ impl)
`(BC N+ impl)
`Amorp Si dep
`N+ Impl
`P+ poly msk
`P+ poly impl
`Si Recryst $111+
`WSix dep
`Nit/BPSG
`
`[nsitu dope Poly/Wsix
`Nit/BPSG
`
`-1
`-1
`-1
`-1
`-1
`-1
`-1
`-1
`
`-
`
`Contact msk/etch
`
`Contact msk/etch
`
`- Insitu Poly/WSix
`Nit/BPSG (ILD 1)
`Licon mask
`Licon etch
`
`Glue/LI dep
`(W-plug)
`(WEB)
`Li mask
`Li etch
`
`ILD2 dep
`Contact msk/etch
`
`1
`1
`
`1
`1
`1
`1
`1
`
`1
`
`G1ue2 dep
`Glue dep
`Glue dep
`W-dep2
`W-plug
`W-plug
`WEB2
`WEB
`WEB
`Metall
`Metall
`‘
`Metall
`
`Summary
`Current Technology
`
`LI Technology
`
`Plug BC
`3 Step Delta Estim from"Cun'ent"
`‘
`High=
`I
`Low=
`.
`Step Delta Estim fro1n"LI Techn"
`High=
`Low=
`
`I
`
`.
`
`5'//7/95'
`
`
`
`

`
`Jeffrey T. Watt
`
`Cypress Semiconductor
`3901 North First Street
`San Jose, CA 95134
`(408) 943-2916
`
`SUMMARY:
`
`Silicon process and device expert with over 8 years of industrial experience in the design, develop-
`ment, characterization, modeling and reliability of MOS transistors in advanced CMOS processes.
`
`EXPERIENCE:
`
`1997-Present: Member of Technical Staff, Advanced Development
`Cypress Semiconductor Corp., San Jose, CA
`Responsible for development of transistors for 0.18 um generation process technology.
`1993-1997: Device Engineering Manager
`Cypress Semiconductor Corp., San Jose, CA
`Leader of group responsible for development of HSPICE models for transistors and interconnects,
`development of ESD protection structures and design rules, development of design rules to meet
`latchup specifications and process development for MOS transistor modules on platform CMOS
`SRAM technologies. Specific accomplishments include:
`Developed transistor processes for Cypress 0.5, 0.4 and 0.35 um CMOS SRAM technologies.
`Established methodology and deliverables for transistor development.
`Established methodology for incremental product shrinks for reduced die cost.
`Provided support to product lines on device issues.
`Determined root cause for EOS failures in burn-in and qual stresses. Developed process moni-
`tor and design rules for reduce EOS fallout with no impact on process cost.
`Developed novel ESD protection devices to meet HBM and CDM requirements on salicided
`and non-salicided technologies.
`1989-1993': Senior Device Engineer,
`Cypress Semiconductor, San Jose, CA
`Responsible for transistor development, electrical design rule generation, electrical test structure
`design, ESD/latch-up design mles. Specific accomplishments include:
`Developed high-voltage transistor for 0.8 um PROM technology
`Developed transistor process for 0.65 um CMOS SRAM technology.
`Developed high-perforrnanoe 0.6 um transistors for SPARC microprocessor.
`Supervised two technicians operating the ESD/latch-up qualification testing and failure analy-
`sis lab.
`Developed ESD protection devices for all 0.8 and 0.65 um technologies including BiCMOS.
`SRAM, Logic. PROM and PLD.
`Developed design rules to protect against CDM ESD, thereby reducing hackend yield loss for
`ESD to -0%.
`
`

`
`EDUCATION
`
`1989: Ph.D., Electrical Engineering, Stanford University, Stanford, CA
`NSERC Postgraduate Scholarship 1984-1987
`Thesis: “Modeling the Performance of Liquid-Nitrogen Cooled CMOS"
`Advisor: James D. Plummer
`
`1984: M.S., Electrical Engineering, Stanford University, Stanford, CA
`Imperial Oil Graduate Research Fellowship 1983- 1986
`Sir James Lougheed Award of Distinction 1983-1985
`
`1983: BS, Electrical Engineering, Queen’s University, Kingston, Canada
`B.S. in Electrical Engineering
`Governor General’s Gold Medal 1983
`
`PUBLICATIONS:
`
`F. N. Troflmenkoff, R. H. Johnson, J. W. Haslett and J. T. Watt, “Image Theory Analysis of Fields
`Due to a Step in the Current on a Long Line on the Surface of the Earth,” IEEE Trans. Geosci.
`Remote Sensing, vol. GE-22, March 1984.
`J. T‘. Watt, B. J. Fishbein and J. D. Plummer, “A Low-Temperature NMOS Technology with
`Cesium—Implanted Load Devices,” IEEE Trans. Electron Devices. vol. ED-34, January 1987.
`A. K. Henning, N. N. Chan, J. T. Watt and J. D. Plummer, “Substrate Current at Cryogenic Tem-
`peratures: Measurements and a Two-Dimensional Model for CMOS Technology,” IEEE Trans.
`Electron Devices, vol. ED-34, January 1987.
`B. J. Fishbein, J. T. Watt and J. D. Plummer, “Time Resolved Annealing of Interface Traps in Pol-
`ysilicon Gate MOS Capacitors,” J. Electrochem. Soc., 134(3), March 1987.
`J. T. Watt and J. D. Plummer, “Efficient Numerical Simulation of the High-Frequency MOS
`Capacitance,” IEEE Trans. Electron Devices, vol. ED-34, October 1987.
`J. T‘. Watt. B. J. Fishbein and J. D. Plummer, “Characterization of Surface Mobility in MOS Struc-
`tures Containing Inter-facial Cesium Ions," IEEE Trans. Electron Devices, vol. 36, January 1989.
`J. '1‘. Watt and J. D. Plummer, “The Effect of Interconnection Resistance on the Performance of
`Liquid-Nitrogen Cooled CMOS Circuits,” IEEE Trans. Electron Devices, vol. 36, August 1989.
`J. T. Watt and J. D. Plummer, “Dispersion of MOS Capacitance-Voltage Characteristics Resulting
`from the Random Channel Dopant Ion Distribution,” IEEE Trans. Electron Devices, vol. 41,
`November 1994.
`
`CONFERENCE PRESENTATIONS:
`
`“Universal Mobility-Field Curves for Electrons and Holes in MOS Inversion Layers,” 1987 Sym-
`posium on VLSI Technology, Karuizawa, Japan.
`“Effect of Interconnection Delay on Liquid-Nitrogen Temperature CMOS Circuit Performance,”
`1987 International Electron Devices Meeting, Washington, D.C.
`“Surface Potential_F1uctuations in MOS Devices Induced by the Random Distribution of Channel
`Dopant Ions,” 1988 Device Research Conference, Boulder, CO.
`“A Hot-Carrier Triggered SCR for Smart Power Bus ESD Protection," 1995 lntemational Electron
`Devices Meeting, Washington, DC.