Europiiisches Patentamt
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`0’
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`European Patent Office
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`Office européen des brevets
`
`@ Publication number: 0
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`@
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`EUROPEAN PATENT APPLICATION
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`@ Application number: 933o5751.5
`
`@ Int. C|.5: H01L 21/90, H01L 23/525
`
`@ Inventor: Hawley, Frank w.
`1360 Capri Drive
`Campbell, California 95008 (US)
`
`Representative : Senior, Alan Murray et al
`J.A. KEMP & CO. 14 South Square Gray's Inn
`London WC1R 5LX (GB)
`
`if a three layer dielec-
`the layer beneath it; and,
`tric is employed, etching the second etch-stop
`dielectric layer with a high % over-etch using an
`etchant having a high selectivity between the
`materials comprising the second etch-stop die-
`lectric layer and the underlying barrier layer or
`antifuse material
`layer,
`stopping
`on
`the
`underlying layer.
`
`second etch-stop dielectric layer may comprise
`the first material. A process for fonning a via
`according to the present
`invention comprises,
`in order, the steps of forming the first etch-stop,
`isolation, and,
`if used,
`the second etch-stop
`dielectric layers over
`the underlying antifuse
`structure; masking the sandwich of dielectric
`layers for formation of a via; etching the iso-
`lation dielectric layer with a high % over-etch
`using an etchant having a high selectivity be-
`tween the materials comprising the
`isolation
`dielectric layer and the first etch-stop dielectric
`layer, stopping on the underlying first etch-stop
`dielectric
`layer;
`etching
`the
`first
`etch-stop
`dielectric layer with high % over-etch, using an
`etchant having a high selectivity between the
`materials comprising the first etch-stop dielec-
`tric layer and the layer beneath it, stopping on
`
`EP0592078A1
`
`Jouve, 18, rue Saint-Denis, 75001 PARIS
`
`@ Date of filing: 21.07.93
`
`Priority: 23.09.92 us 950264
`
`Date of publication of application :
`13.04.94 Bulletin 94/15
`
`Designated Contracting States:
`DE FR GB IT
`
`(/3 Applicant: ACTEL CORPORATION
`955 East Arques Avenue
`Sunnyvale California 94086 (US)
`
`
`
`Antifuse element and fabrication method.
`
`@ A dielectric layer through which an antifuse
`via or an antifuse contact via is to be formed
`comprises a sandwich of at
`least
`two, and
`preferably three,
`individual
`layers. A first etch-
`stop dielectric layer
`(42)
`is disposed over an
`underlying layer comprising either a lower or
`upper antifuse electrode barrier layer (14) or an
`antifuse material
`layer. The
`first
`etch-stop
`dielectric layer comprises a thin layer of dielec-
`tric material. An isolation dielectric layer (44) is
`disposed over the first etch-stop dielectric layer
`and comprises a second material comprising
`most of
`the thickness of
`the sandwich and
`
`from
`having a substantial etch-time differential
`the first etch-stop dielectric material for a se|ec-
`ted etchant
`for
`the first etch-stop dielectric
`
`material. A second etch-stop dielectric layer
`
`(48) may be provided under the first etch-stop
`dielectric layer and may be formed from a third
`material having a substantial etch time differen-
`tial
`from the first etch-stop dielectric material
`for a selected etchant for the first material. The
`
`44
`
`42\
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`45
`
`22
`
`so
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`55
`54
`
`}46
`
`18
`V2
`
`FIG. 3a
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`INTEL 1004
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`EP 0 592 078 A1
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`BACKGROUND OF THE INVENTION
`
`1.Fie|d Of The Invention
`
`The present invention relates to antifuse technol-
`ogy and to methods for fabricating antifuse elements.
`More particularly, the present invention relates to
`methods for fabricating antifuses which minimize the
`damage to antifuse films during the etch steps per-
`formed to form antifuse vias or antifuse contact vias.
`
`2. The Prior Art
`
`Antifuse fabrication processes universally em-
`ploy an etching step which is used to form an antifuse
`via in an inter-electrode dielectric layer which sepa-
`rates the upper and lower antifuse electrodes. During
`this etching step, it is important to protect the under-
`lying layer of material whether it be an already-formed
`antifuse material (such as amorphous silicon, silicon
`dioxide or silicon nitride or some combination thereof)
`or the upper surface of the upper or lower antifuse
`electrode (comprising a material such as TiW, Ti, TiN,
`TiW:N or some other effective metallic barrier film).
`Where an amorphous silicon antifuse material is em-
`ployed it is important to maintain the integrity of the
`barrier layer protecting the amorphous silicon anti-
`fuse layer from metal diffusion. Acertain barrier metal
`thickness must be maintained in order to prevent dif-
`fusion of atoms from the electrodes into the amor-
`
`phous silicon. Such contamination degrades the per-
`formance of the amorphous silicon dielectric. It is also
`important to maintain the as-deposited thickness of
`the amorphous silicon in order to maintain control of
`the voltage at which the antifuse material will rupture.
`In some antifuse structures, the lower antifuse
`electrode comprises a first metal interconnect layer
`and the upper electrode of the antifuse comprises a
`barrier layer to which electrical connection is made
`through an antifuse contact via etched through a di-
`electric layer underlying a second metal interconnect
`layer. In such embodiments, the upper electrode/bar-
`rier layer protects the underlying antifuse material
`from diffusion of atoms from the second metal inter-
`
`connect layer. It is important to maintain the integrity
`of this upper electrode/barrier layer to protect the un-
`derlying amorphous silicon antifuse layer from metal
`diffusion.
`When either an antifuse via or an antifuse contact
`
`via is etched through a traditional continuous dielec-
`tric film, such as PECVD oxide, either the antifuse
`material or the barrier layer over the lower electrode
`is exposed to the etch during the final over-etch por-
`tion of the etch step. Since a typical over-etch is spe-
`cified at from about 30-60% of the etch time, the ex-
`posure of the antifuse material or the barrier layer
`during the over-etch process will damage these lay-
`ers. The typical via depth through an intermetal di-
`
`electric layer is between about 0.5-1.0 microns deep,
`and the antifuse material or lower electrode barrier
`
`layer is relatively thin, i.e., between about 0.1 to 0.3
`microns. Both the antifuse material layer and the bar-
`rier layer are sensitive to the loss of 100 angstroms
`of material. It is thus important to find a way to mini-
`mize the amount of via overetch to which these films
`
`are exposed.
`
`BRIEF DESCRIPTION OF THE INVENTION
`
`According to the present invention, an interlayer
`dielectric layerthrough which an antifuse via or an an-
`tifuse contact via is to be formed comprises a sand-
`wich of at least two, and preferably three, individual
`layers. A first etch-stop dielectric layer is disposed
`over an underlying layer comprising either a lower or
`upper antifuse electrode barrier layer or an antifuse
`material layer. The first etch-stop dielectric layer com-
`prises a thin layer of a first dielectric material. An iso-
`lation dielectric layer is disposed over the first etch-
`stop dielectric layer and comprises a second material
`comprising most of the thickness of the sandwich and
`having a substantial etch-time differential from the
`first material for a selected etchant for the first mate-
`
`rial. Asecond etch-stop dielectric layer may be provid-
`ed under the first etch-stop dielectric layer and may
`be formed from a third material having a substantial
`etch time differential from the first material for a se-
`lected etchant for the first material. The additional di-
`
`electric layer may comprise the first material.
`The compositions and thicknesses of the first
`and second etch-stop dielectric layers can be adjust-
`ed so as to act as etch stops during the via etch. This
`acts to reduce the amount of etch exposure the ma-
`terial at the bottom of the via will see, thus reducing
`the amount of etch damage the bottom material in-
`curs.
`
`According to a presently preferred embodiment
`of the invention, the first etch-stop dielectric layer
`may comprise a thin layer of silicon nitride, the isola-
`tion dielectric layer may comprise a thick layer of sil-
`icon dioxide. The second etch-stop dielectric layer, if
`used, may comprise a thin layer of silicon dioxide.
`As a part of an antifuse fabrication process ac-
`cording to the present invention, a via etch process in-
`cludes the steps of first etching the isolation dielectric
`layerwith a high % over-etch (i.e.,50%) using an etch-
`ant having a high selectivity between the materials
`comprising the isolation dielectric and first etch-stop
`dielectric layers, stopping on the underlying firstetch-
`stop dielectric layer; next, etching the first-etch-stop
`dielectric layer with high % over-etch (i.e., 50%), us-
`ing an etchant having a high selectivity between the
`materials comprising the first etch-stop dielectric lay-
`er and the layer beneath it, stopping on the underly-
`ing layer. According to a first embodiment of the in-
`vention, the underlying layer will comprise either the
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`EP 0 592 078 A1
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`barrier layer or the antifuse material layer, depending
`on the antifuse structure employed. According to a
`second embodiment of the invention, the underlying
`layer will comprise the second etch-stop dielectric
`layer, and a third step of the process comprises etch-
`ing the second etch—stop dielectric layer with a high
`% over-etch (i.e., 50%) using an etchant having a high
`selectivity between the materials comprising the sec-
`ond etch-stop dielectric layer and the underlying bar-
`rier layer or antifuse material layer, stopping on the
`underlying layer. With short etch time exposure and
`good selectivity, the potential etch damage to the un-
`derlying antifuse layer or barrier layer is minimized
`while providing a reliable via etch process.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIGS. 1a—1c are cross-sectional views of three
`
`different antifuse structures processed through via
`formation, illustrating the problem solved by the pres-
`ent invention.
`
`FIG. 2a is a cross-sectional view of an interlayer
`dielectric layer for employment in an antifuse struc-
`ture according to a first embodiment ofthe present in-
`vention is shown.
`
`FIG. 2b is a cross-sectional view of an interlayer
`dielectric layer for employment in an antifuse struc-
`ture according to a second embodiment oft he present
`invention is shown.
`FIG. 3a is a cross-sectional view of an antifuse
`
`structure according to a first embodiment of the pres-
`ent invention.
`FIG. 3b is a cross-sectional view of an antifuse
`
`structure according to a second embodiment of the
`present invention.
`FIG. 3c is a cross-sectional view of an antifuse
`
`structure according to a third embodimentofthe pres-
`ent invention.
`
`FIG. 4a is a flow diagram illustrating the process
`for fabricating the antifuse structure of FIG. 3a.
`FIG. 4b is a flow diagram illustrating the process
`for fabricating the antifuse structure of FIG. 3b.
`FIG. 4c is a flow diagram illustrating the process
`for fabricating the antifuse structure of FIG. 3c.
`
`DETAILED DESCRIPTION OF A PREFERRED
`EMBODIMENT
`
`Those of ordinary skill in the art will realize that
`the following description of the present invention is il-
`lustrative only and not in any way limiting. Other em-
`bodiments of the invention will readily suggest them-
`selves to such skilled persons.
`Referring first to FIGS. 1a—1c, cross sectional
`views are presented of three different antifuse struc-
`tures which illustrate the problem solved by the pres-
`ent invention. The antifuse structures depicted in
`FIGS. 1a—1c have been processed through via forma-
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`tion.
`
`FIG. 1a depicts an antifuse structure 10 wherein
`a lower electrode 12 comprises a metal interconnect
`layer in an integrated circuit. Such interconnect layers
`are typically formed from an alloy of AI/Si/Cu. A lower
`electrode barrier layer 14 is disposed over lower elec-
`trode 12. The function of lower electrode barrier layer
`14 is to prevent diffusion of atoms from the material
`comprising lower electrode 12 into the antifuse mate-
`rial layer which is disposed over lower electrode bar-
`rier layer 14. Lower electrode barrier layer 14 may
`comprise materials such as Ti:W, Ti:N, Ti:W:N, etc.
`An interlayer dielectric layer 16 is disposed over
`lower electrode barrier layer 14. interlayer dielectric
`layer 16 usually comprises a thick layer of a material
`such as PECVD silicon dioxide. An antifuse via 18 is
`
`etched through interlayerdielectric layer 18 to expose
`the upper surface of barrier layer 14.
`At the point in the fabrication process depicted in
`FIG. 1a, an antifuse material layer will be formed in
`antifuse via 18. Later an upper electrode barrier layer
`and an upper electrode will be formed over the anti-
`fuse material layer to complete the antifuse structure.
`Referring now to FIG. 1b, it may be seen that an-
`tifuse structure 20 depicted therein is similar to anti-
`fuse structure 10 of FIG. 1a. The difference is that an-
`
`tifuse material layer 22 is disposed over lower elec-
`trode barrier layer 14 prior to the formation of inter-
`layer dielectric layer 16. Antifuse material layer typi-
`cally comprises a layer of amorphous silicon, but may
`also comprise other materials, such as one or more
`layers of dielectric materials, such as silicon dioxide,
`silicon nitride, etc. Those of ordinary skill in the artwill
`be familiar with the various compositions used for an-
`tifuse material
`layer 16. Antifuse via 18 is etched
`through interlayer dielectric layer 18 to expose the
`upper surface of antifuse material layer 22.
`At the point in the fabrication process depicted in
`FIG. 1b, an upper electrode barrierlayer and an upper
`electrode will be formed in via 18 over the antifuse
`
`material layer to complete the antifuse structure.
`Referring now to FIG. 1c, it may be seen thatan-
`tifuse structure 30 depicted therein is similar to anti-
`fuse structure 20 of FIG. 1 b. The difference is that top
`antifuse electrode barrier layer 32, which may com-
`prise a barrier material similar to lower electrode bar-
`rier Iayer 14, is disposed over antifuse material layer
`22 prior to the formation of interlayer dielectric layer
`16. Antifuse via 18 is etched through interlayerdielec-
`tric layer 16 to expose the upper surface ofthe top an-
`tifuse electrode barrier layer 22.
`Unlike the embodiments of FIGS. 1a and 1b, the
`entire antifuse structure is already formed before in-
`terlayer dielectric layer 16 is formed in the embodi-
`ment of FIG. 1c. The function of interlayer dielectric
`layer 16 is to isolate the completed antifuse structure
`from a metal
`interconnect layer which will later be
`formed.
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`At the point in the fabrication process depicted in
`FIG. 1c, a metal interconnect layer will be formed in
`via 18 over the antifuse material layer to complete the
`antifuse structure.
`
`in the art will recognize
`Those of ordinary skill
`that an antifuse material comprising one or more thin
`dielectric layers may be substituted for the amor-
`phous silicon in any ofthe embodiments of FIGS. 1a-
`1c. Where dielectric layers such as ONO are em-
`ployed as the antifuse material, the barrier layers be-
`tween which the antifuse material
`is sandwiched
`
`should comprise a material such as Ti:W:N, since
`Ti:W will react with silicon dioxide.
`
`In the processes used to fabricate the structures
`depicted in FIGS. 1a-1c, via 18 is formed using an
`etching process to remove a portion of the interlayer
`dielectric layer 16 to define the via 18. Such an etch-
`ing process is conventional and is performed by first
`masking the surface of the interlayer dielectric layer
`16 to define the via 18. the exposed portion of the in-
`terlayer dielectric layer 16 is then subjected to either
`chemical or reactive etching as is known in the art.
`Those of ordinary skill
`in the art will recognize
`that conventional etching techniques employ an
`"over—etch" step. to assure removal of all of the ma-
`terial which it is desired to remove. Typical over-etch
`procedures comprise continuing the etch process for
`a period oftime equal to between about 30-70% ofthe
`nominal etch time required to remove the thickness of
`the material which it is desired to remove.
`
`When performing the via etch step in the struc-
`ture of FIG. 1a, the lower electrode barrier layer 14 is
`exposed to the over-etch step. Similarly, when per-
`forming the via etch step in the structure of FIG. 1b,
`the antifuse material layer 22 is exposed to the over-
`etch step, and when performing the via etch step in
`the structure of FIG. 1c, the upper electrode 32 is ex-
`posed to the over-etch step. The effect of over-etch
`process on layers 14, 22, and 32 leads to degradation
`ofthe finished antifuse. In the embodiments of FIGS.
`
`1a and 1c, the over-etch process will cause an unin-
`tentional thinning ofthe upper or lower barrier layers
`which prevent metal diffusion into the antifuse mate-
`rial layer 22. The effect ofthinning of either ofthese
`barrier layers reduces their effectiveness and in-
`creases the possibility that metal atoms from the low-
`er electrode (the embodiment of FIG. 1a) orthe upper
`metal interconnect layer (the embodiment of FIG. 1c)
`will diffuse into the antifuse material layer, thus un-
`predictably lowering its breakdown (i.e., program-
`ming) voltage or otherwise degrading it.
`Referring now to FIGS. 2a and 2b, an interlayer
`dielectric according to first and second embodiments,
`respectively, of the present invention are shown. Re-
`ferring first to FIG. 2a, an interlayer dielectric layer 40
`for employment in an antifuse according to a first em-
`bodiment of the present invention is depicted in cross-
`sectional view. Afirst etch-stop dielectric layer 42 of
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`the interlayer dielectric layer 40 comprises a thin lay-
`er ofdielectric material which can be etched selective-
`
`Iy with respect to the layer upon which it is disposed.
`For example, in the embodiment of FIG. 1a, the first
`etch-stop dielectric layer 42 is disposed over the low-
`er electrode barrier layer 14. Alayer of PECVD nitride
`having a thickness of between about 200 to 2,000
`angstroms, preferably about 1,000 angstroms may be
`employed for this layer.
`An isolation dielectric layer 44 is disposed over
`first etch-stop dielectric layer 42. Isolation dielectric
`layer 44 is formed from a layer of dielectric material
`which can be etched selectively with respect to first
`etch-stop dielectric layer 42 and may comprise a thick
`layer of PECVD silicon dioxide. This layer may have
`a thickness of between about 4,000 to 9,000 ang-
`stroms, and preferably about 7,000 angstroms.
`The isolation dielectric layer 44 serves as the in-
`terlayer isolation. The first etch-stop dielectric layer
`42 functions as an etch stop for isolation dielectric lay-
`er 44, allowing a complete overetch ofthe via through
`isolation dielectric layer 44 without etching thru the
`thin nitride layer comprising first etch-stop dielectric
`layer 42 and attacking the underlying layer of antifuse
`material or barrier material. This is due to the etch rate
`
`selectivity between the two dielectric materials, such
`as oxide and nitride.
`
`Referring now to FIG. 2b, an interlayer dielectric
`46 according to a second embodiment of the present
`invention is shown in cross-sectional view. Asecond
`
`etch-stop dielectric layer 48 comprises a thin layer of
`dielectric material which can be etched selectively
`with respect to the layer upon which it is disposed. For
`example, in the embodiment of FIG. 1a, the second
`etch-stop dielectric layer 48 is disposed over the low-
`er electrode barrier layer 14. A layer of PECVD silicon
`dioxide having a thickness of between about 200 to
`2,000 angstroms, preferably about 1,000 angstroms
`may be employed for this layer.
`Afirst etch-stop dielectric layer 42 of the interlay-
`er dielectric layer 46 comprises a thin layer of dielec-
`tric material which can be etched selectively with re-
`spect to the second etch-stop dielectric layer 48 upon
`which it is disposed. A layer of PECVD nitride having
`a thickness of between about 200 to 2,000 ang-
`stroms, preferably about 1,000 angstroms may be
`employed for this layer.
`An isolation dielectric layer 44 is disposed over
`first etch-stop dielectric layer 42. Second etch-stop
`dielectric layer 44 comprises a thick layer of dielectric
`material which can be etched selectively with respect
`to the first etch-stop dielectric layer 42 upon which it
`is disposed, and may comprise a thick layer of
`PECVD silicon dioxide. This layer may have a thick-
`ness of between about 4,000 to 9,000 angstroms, and
`preferably about 7,000 angstroms.
`In the embodiment of FIG. 2b, the isolation di-
`electric layer 44 serves as the principal interlayer iso-
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`Iation element. The first etch-stop dielectric layer 42
`functions as an etch stop for isolation dielectric layer
`44, allowing a complete overetch of the via through
`isolation dielectric layer 44 without etching thru the
`thin nitride layer comprising first etch-stop dielectric
`layer 42.
`The second etch-stop dielectric layer48 functions
`as an etch stop for the first etch-stop dielectric layer
`etch, allowing for an overetch to clear all the first etch-
`stop dielectric layer 42 thin nitride film away without
`etching thru the isolation dielectric layer thin oxide.
`The second etch-stop dielectric layer 48 is added be-
`cause there is a better etch selectivity between sili-
`con dioxide and amorphous silicon and barrier layer
`materials than between silicon nitride and those ma-
`
`terials. After the second etch-stop dielectric layer 48
`is cleared away, the underlying antifuse material or
`barrier layer material is exposed to only a very short,
`highly selective etch, thus giving a soft etch on the un-
`derlying material. This minimizes the etch damage to
`the underlying material. This is a more reliable and
`controllable manufacturing process than is employed
`in the prior art. .
`FIGS. 3a-3c illustrate the antifuse structures ac-
`
`cording to the present invention utilizing the interlayer
`dielectrics of FIG. 2b. The embodiments of FIGS. 3a-
`
`3c correspond to the antifuse structures depicted in
`FIGS 1a-1c, respectively. Like reference numerals
`have been employed for like structures in FIGS. 1a-
`1c and FIGS. 3a-3c.
`
`FIG 3a depicts a cross-sectional view of a metal-
`to-metal antifuse 60 according to a first embodiment
`of the present invention which may be disposed be-
`tween two metal interconnect layers. Bottom elec-
`trode 12 comprises a first metal interconnect layer
`and is covered by a barrier layer 14, which may be
`typically employed in a 0.8 micron CMOS process as
`a barrier and anti-reflective layer. interlayer dielectric
`46 comprises second etch-stop dielectric layer 48,
`first etch-stop dielectric layer 42, and isolation dielec-
`tric layer 44. Antifuse via 18 is formed therein and an-
`tifuse material layer 22 is formed in antifuse via 18. An
`upper barrier layer 54 is formed over antifuse material
`layer 22, and second metal interconnect layer 56 is
`formed over upper barrier layer 54. Those of ordinary
`skill in the art will recognize that if the interlayer di-
`electric of FIG. 2a is employed, second etch-stop di-
`electric layer 48 will be omitted, and first etch-stop di-
`electric layer 42 will be disposed directly over lower
`electrode barrier layer 14.
`FIG. 3b depicts a cross-sectional view of a metal-
`to-metal antifuse 62 according to a second embodi-
`ment of the present invention which may be disposed
`between two metal interconnect layers. Antifuse 62 is
`similar to antifuse 60, except that antifuse layer 22 is
`disposed over bottom electrode barrier layer 14 and
`the stacked layers of lower electrode 12, barrier layer
`14, and antifuse layer 22 are usually defined prior to
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`the formation of interlayer dielectric layer 46 in order
`to minimize the capacitance of the antifuse. interlayer
`dielectric 46 comprises second etch-stop dielectric
`layer 48, first etch-stop dielectric layer 42, and isola-
`tion dielectric layer 44. Antifuse via 18 is formed
`therein to expose antifuse material layer 22. An upper
`barrier layer 54 is formed in antifuse via 18, and sec-
`ond metal interconnect layer 56 is formed over upper
`barrier layer 54. As in the embodiment disclosed in
`FIG. 3a, those ofordinary skill in the artwill recognize
`that if the interlayer dielectric of FIG. 2a is employed,
`second etch-stop dielectric layer 48 will be omitted,
`and first etch-stop dielectric layer 42 will be disposed
`directly over lower electrode barrier layer 14.
`FIG. 3c depicts a cross-sectional view of a metal-
`to-metal antifuse 64 according to a third aspect of the
`present invention. Unlike the embodiments depicted
`in FIGS. 3a and 3b, antifuse 64 is completely con-
`tained beneath interlayer dielectric layer 46. In this
`embodiment, therefore, the via 18 is more accurately
`referred to as a contact via. As shown in FIG. 3c, bot-
`tom electrode 12, barrier layer 14, antifuse material
`layer 22, and upper antifuse electrode 66, formed
`from a barrier material, are defined prior to formation
`of interlayer dielectric 46, which comprises second
`etch-stop dielectric layer 48, first etch-stop dielectric
`layer 42, and isolation dielectric |ayer44. Second met-
`al interconnect layer 68 is formed in contact via 18.
`Referring now to FIG. 4a, a flow diagram illus-
`trates the process for fabricating the antifuse struc-
`ture illustrated in FIG. 3a. Reference numerals to the
`
`corresponding structures of FIG. 3a will also be used.
`First, at step 70, the lower antifuse electrode 12 is
`formed. This electrode may comprise a metal inter-
`connect layer and may be formed from a material
`such as AI/Si/Cu having a thickness of about 4,500
`angstroms as is known in the art, or from other ma-
`terials used to form interconnect layers in integrated
`circuits.
`
`At step 72, barrier layer 14 is formed from a
`known barrier layer material such as Ti:W, TiN, or
`Ti:W:N,
`to a thickness of about 3,000 angstroms.
`Next, at step 74, interlayer dielectric 40 (FIG. 2a) or
`46 (FIG. 2b) is formed. If a three—|ayer structure is to
`be formed, a second etch-stop dielectric layer 48
`which may comprise from about 200 to 2,000 ang-
`stroms of PECVD silicon dioxide is formed over the
`
`surface of barrier layer. Afirst etch-stop dielectric lay-
`er 42 , which may comprise from about 200 to 2,000
`angstroms of PECVD silicon nitride, is formed, either
`over second etch-stop dielectric layer 48 if a three-
`layer interlayer dielectric layer structure is to be
`formed, or over barrier layer 14 if a two-layer interlay-
`er dielectric layer is to be formed. Finally, isolation di-
`electric layer 44 is formed over the surface of first
`etch-stop dielectric layer 42.
`Atthis point in the process, the antifuse via18wiII
`be formed. First, isolation dielectric layer 44 is suit-
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`ably masked, using conventional photolithography
`techniques. At step 76, an etching step is used to etch
`via 18 through isolation dielectric layer using an etch-
`ant which is highly selective between isolation dielec-
`tric layer 44 and first etch-stop dielectric layer 42.
`Etchants such as CHF3 :02 with a 6:1 ratio are suit-
`able forthis procedure. An overetch procedure of from
`about 30-70%, preferably about 50% is employed.
`Next, at step 78, the one or more etch stop dielec-
`tric layers are removed. The via is etched into first
`etch-stop dielectric layer 42 etched using an etchant
`having a high selectivity between first etch-stop di-
`electric layer 42 and the underlying layer. When a
`three-layer interlayer dielectric layer is employed, the
`underlying layer will be second etch-stop dielectric
`layer 48, preferably formed from silicon dioxide, and
`an etchant such as CHF3 :02 with a 1:4 ratio may be
`employed. When a two-layer interlayer dielectric lay-
`er is employed, the underlying Iayer will be barrier
`layer 14, and an etchant such as CHF3 :02 with a 1:4
`ratio may be employed. An overetch procedure of
`from about 30-70%, preferably about 50% is em-
`ployed.
`If a three-layer interlayer dielectric layer is em-
`ployed, a final etching step is performed to continue
`via 18 through second etch-stop dielectric layer 48
`using an etchant having a high selectivity between
`second etch-stop dielectric layer 48 and barrier layer
`14. An overetch procedure of from about 30-70%,,
`preferably about 50% is employed. This will etch very
`little into barrier layer 14 because of the high selec-
`tivity and the short actual overetch time used when
`etching a thin oxide.
`Next, after removal of the via masking layer by
`conventional processing techniques, an antifuse lay-
`er 22 is formed in via 18. Antifuse layer 22 may com-
`prise a layer of amorphous silicon having a thickness
`of between about 1,000-3,000 angstroms, preferably
`about 1,200 angstroms, and may be formed using
`CVD techniques. Alternatively, a single or multi-layer
`dielectric structure, such as an nitride (N), N/amor-
`phous silicon, amorphous silicon/N, amorphous sili-
`con/N/amorphous silicon, N/amorphous silicon/N,
`ON, N0, ONO, NON, or similar structure may be
`formed using PECVD techniques. Finally, an upper
`barrier layer 54 and upper electrode 56 may be
`formed at step 82 using conventional processing
`techniques to thickness of about 3,000 angstroms
`and 7,000 angstroms, respectively.
`Referring now to FIG. 4b, a flow diagram illus-
`trates the process for fabricating the antifuse struc-
`ture illustrated in FIG. 3b. Reference numerals tothe
`
`corresponding structures of FIG. 3b will also be used.
`First, at step 90, the lower antifuse electrode 12 is
`formed. This electrode may comprise a metal inter-
`connect layer and may be formed from a material
`such as AI/Si/Cu having a thickness of about 4,500
`angstroms as is known in the art, or from other ma-
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`terials used to form interconnect layers in integrated
`circuits.
`
`At step 92, barrier layer 14 is formed from a
`known barrier layer material such as Ti:W, TiN, or
`Ti:W:N, to a thickness of about 3,000 angstroms. At
`step 94 an antifuse layer 22 is formed over barrier lay-
`er 14. Antifuse layer 22 may comprise a layer of amor-
`phous silicon having a thickness of between about
`1,000-3,000 angstroms, preferably about 1,200 ang-
`stroms, and may be formed using CVD techniques.
`Alternatively, a single or multilayer dielectric struc-
`ture, such as those previously described may be
`formed using PECVD techniques. The stacked struc-
`ture of lower electrode 12, barrier layer 14, and anti-
`fuse layer 22 is typically patterned and defined using
`conventional masking and etching techniques.
`Next, at step 96, interlayer dielectric 40 (FIG. 2a)
`or 46 (FIG. 2b) is formed. If a three—|ayer structure is
`to be formed, a second etch-stop dielectric layer 48
`which may comprise from about 200 to 2,000 ang-
`stroms of PECVD silicon dioxide is formed over the
`
`surface of barrier layer. Afirst etch-stop dielectric lay-
`er 42 , which may comprise from about 200 to 2,000
`angstroms of PECVD silicon nitride, is formed, either
`over second etch-stop dielectric layer 48 if a three-
`Iayer interlayer dielectric layer structure is to be
`formed, or over barrier layer 14 if a two-layer interlay-
`er dielectric layer is to be formed. Finally, isolation di-
`electric layer 44 is formed over the surface of first
`etch-stop dielectric layer 42.
`Atthis point in the process, the antifuse via 18wiII
`be formed. First, isolation dielectric layer 44 is suit-
`ably masked, using conventional photolithography
`techniques. At step 98, an etching step is used to etch
`via 18 through isolation dielectric layer using an etch-
`ant which is highly selective between isolation dielec-
`tric layer 44 and first etch-stop dielectric layer 42.
`Etchants such as CHF3 :02 with a 6:1 ratio, are suit-
`able forthis procedure. An overetch procedure offrom
`about 30-70%, preferably about 50% is employed.
`Next, at step 100, the one or more etch stop di-
`electric layers are removed. The via is etched into first
`etch-stop dielectric layer 42 etched using an etchant
`having a high selectivity between first etch-stop di-
`electric Iayer 42 and the underlying layer. When a
`three-layer interlayer dielectric layer is employed, the
`underlying layer will be second etch-stop dielectric
`layer 48, preferably formed from silicon dioxide, and
`an etchant such as CHF3 :02 with a 1:4 ratio may be
`employed. When a two-layer interlayer dielectric lay-
`er is employed, the underlying layer will be antifuse
`material layer 22, and an etchant such as CHF3 :02
`with a 1 :4 ratio may be employed. An overetch proce-
`dure of from about 30-70%, preferably about 50% is
`employed.
`If a three—layer interlayer dielectric layer is em-
`ployed, a final etching step is performed to continue
`via 18 through second etch-stop dielectric layer 48
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`using an etchant having a high selectivity between
`second etch-stop dielectric layer 48 an