United States Patent
`
`[19]
`
`[11] Patent Number:
`
`4,686,000
`
`Heath
`Aug. 11, 1987
`[45] Date of Patent:
`
`is
`
`MOS LS1," IEEE Trans. on Electron Devices, vol.
`ED—28, No. 1, Jan. 1981, pp. 77-82.
`Kuninobu, S., “A New Self—Aligning Poly—Contact
`Technology for MOS LSl,“ IEEE Trans. on Electron
`Devices, vol. ED~29, No. 8, Aug. 1982, pp. 1309-1313.
`Josquin et
`al., “The Oxidation Inhibition in Ni-
`trogen—Implanted
`Silicon,"
`J.
`Electrochem.
`Soc.:
`Solid—State Science and Technology, vol. 129, No. 8,
`Aug. 1982, pp. 1803-1811.
`Tanigaki et al., “A New Self—Aligned Contact Technol-
`ogy," J. Electrochem. Soc." Solid—State Science and
`Technology, vol. 125, No. 3, Mar. 1978, pp. 471-472.
`
`Primary Examiner—Wil1iam A. Powell
`
`[57]
`
`ABSTRACI‘
`
`An improved process for self-aligned contact window
`formation in an integrated circuit leaves a “Stick" of
`etch stop on vertical sidewall surfaces to be protected.
`The technique includes, in the preferred embodiment, a
`layer of oxide over active areas and on top of the gate
`electrode of a transistor. The oxide is thicker on top of
`the gate electrode than over the active area. A silicon
`nitride layer acting as an etch stop is included between
`the oxide and interlevel dielectric such as BPSG.
`Contact windows may deviate from their intended posi-
`tion and partially overlie a poly edge such as a gate
`electrode or an isolation (field-shield) or field oxide
`edge. Two-step etching comprises first etching the
`BPSG down to the etch stop layer, then etching the
`etch stop and underlying oxide, leaving a “stick” of etch
`stop on the side of the layer to be protected. This pro-
`cess preserves for the second step of the etch the differ-
`ential thickness ratio of the oxide over the gate elec-
`trodes as compared to the oxide over the active area.
`This process allows the simultaneous formation of self-
`aligned contacts to field oxide, field-shield, and gate
`electrode edges. It is independent of the type of gate
`dielectric, gate electrode material, and gate electrode
`sidewall processing.
`
`OTHER PUBLICATIONS
`
`Hosoya, T., “A Self—Aligning Contact Process for
`
`10 Claims, 20 Drawing Figures
`
`
`
`INTEL 1003
`
`[54] SELF-ALIGNED CONTACI‘ PROCESS
`
`[76]
`
`Inventor: Barbara A. Heath, 615 Hempstead
`Pl., Colorado Springs, Colo. 80906
`
`[21] Appl. No.: 831,463
`
`[22] Filed:
`
`Feb. 19, 1986
`
`Related U.S. Application Data
`
`[63]
`
`Continuation—in—part of Ser. No. 719,073, Apr. 2, 1985,
`abandoned.
`
`[51]
`
`Int. Cl.‘ .................... .. H0lL 21/306; B44C 1/22;
`C03C 15/00; C03C 25/06
`[52] U.S. Cl._ .................................. .. 156/643; 156/644;
`156/646; 156/653; 156/657; 156/662; 357/23.1;
`357/41; 437/235; 437/241; 437/40
`[58] Field of Search ............... .. 29/580, 589, 590, 591,
`' 29/571, 576 W; 156/643, 644, 646, 653, 657,
`659.1, 656, 661.1, 662; 427/88-90; 357/231, 41,
`49, 59, 65, 71; 148/1.5, 187
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`317/235
`148/187
`
`3/1972 Peltzer
`3,648,125
`3,849,216 11/1974 Salters .... ..
`3,913,211 10/1975 Seeds et al.
`3,936,858
`2/1976 Seeds et al.
`4,182,023
`1/1980 Cohen et al.
`4,210,993
`7/1980 Sunami ....... ..
`4,271,582
`6/1981 Shirai et al.
`..
`4,287,661
`9/1981 Stoffel ........ ..
`4,292,728 10/1981 Endo
`4,356,623 11/1982 Hunter .
`4,466,172
`8/1984 Batra .......... ..
`.,
`. 4,486,943 12/1984 Ryden et al.
`.
`. . . . .. 29/577
`4,505,026
`3/1985 Bohr . . . .. . . .. . . . .
`4,513,494 4/1985 Batra ............................... .. 29/576 B
`
`
`
`.... ..
`
`

`
`U. S. Patent Aug, 11,1987
`
`Sheet1of10
`
`4,686,000
`
`

`
`U. S. Patent Aug. 11, 1987
`
`Sheet2 of 10
`
`4,686,000
`
`

`
`U. S. Patent Aug. 11,1987
`
`Sheet3 ofl0
`
`4,686,000
`
`

`
`U. S. Patent Aug 11,1987
`
`Sheet4of1O
`
`4,686,000
`
`F/G’. 8.4
`F’/G. 8B
`
`
`

`
`U.S. Patent Aug. 11,1987
`
`Sheet5 ofl0
`
`4,686,000
`
` 50’ “*1
`
`FIG. 9,4
`
`‘._.5a._.‘
`
`34‘
`
`

`
`U. S. Patent Aug. 11,1987
`
`Sheet6 ofl0
`
`4,686,000
`
`t o O o C 0 O 0 n O u Q O O Q o u go
`
`g
`
`. o o o I 0 0 U Q O u 0 0 on
`
`§‘“‘T§
`
`9
`
`~ls\,
`
`7 7 7
`
`{"o"¢~' 'o'9'<r ,
`9.0
`
`E’
`
`E 0
`
`'3
`
`n
`
`3 it
`
`V
`
`9.
`
`K
`
`A
`
`3 // /V / »'ooo,o,0¢%*’o«/
`//
`[>'o’¢'09¢%’o"o'O'¢I‘
`A
`I
`A
`.x‘§x\ 1»
`/A{0XOX_>:9:¢:?:f:2:2oj‘A A /A
`3 5:;
`
`'
`
`:
`
`.
`I
`
`V V
`
`3|
`
`N
`W
`
`Q o o u o a o o o o o c so
`Q
`
`we
`: o o o o o o o o o o o o o no:
`
`

`
`U. S. Patent Aug. 11,1987
`
`Sheet7 of10
`
`4,686,000
`
`FIG /05
`
`

`
`U. S. Patent Aug, 11,1987
`
`Sheet8 ofl0
`
`4,686,000
`
`
`
`wax.Q\.\.N
`
`

`
`U. S. Patent Aug. 11, 1987
`
`Sheet9 oflO
`
`4,686,000
`
`

`
`U. S. Patent Aug. 11,1987
`
`Sheetl0 of10 4,686,000
`
`

`
`1
`
`SELF-ALIGNED CONTACT PROCESS
`
`4,686,000
`
`This is a continuation-in-part of Ser. No. 719,073 filed
`in the U.S. Patent and Trademark Office on Apr. 2,
`1985, now abandoned, the contents of which are hereby
`incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`The present invention is concerned with semiconduc-
`tor fabrication and particularly with design rules in-
`volving contact window placement and etching, as well
`as other aspects of the fabrication of integrated circuits.
`A first problem which the present
`invention ad-
`dresses relates to the fabrication of contact windows,
`which becomes a substantial problem in high-density
`integrated circuits. Integrated circuits are layered, hav-
`ing a silicon substrate, a first and sometimes a second
`layer of polysilicon thereover, and at least one layer of
`metal over that. Each of these layers is “defined” into
`circuit elements (such as lines). In order to provide
`electrical insulation between these various elements and
`layers, interlevel dielectric is used between the elements
`defined in the first (lowest or first deposited) polysilicon
`.layer
`(poly I) and elements defined in the second
`polysilicon layer (poly II), between poly II and the
`elements defined in the first metal layer, and between
`elements defined in subsequent metal
`layers. Contact
`windows permit contacts between two layers or be-
`tween a part of the substrate and a layer or element
`located above it.
`One use for a contact window is to provide electrical
`contact with a source/drain region which has been
`formed in a substrate. Near the contact window there
`will generally be found another element such as a gate
`electrode, a field shield edge, or a field oxide edge. with
`the increasing density of integrated circuits, the geome-
`tries become smaller, and obviously the space separat-
`ing the contact windows from nearby elements becomes
`less. To understand this problem, reference will be
`made to FIGS. 1A—1D.
`FIG. 1A is a representational plan view of a Contact
`window 1 which is placed on a source/drain region 2
`(inside broken lines) which has been established within
`a substrate 3. Window 1 is located a distance d repre-
`sented by an arrow 4 from an edge 5 which separates
`source/drain region 2 from isolation 6. Isolation 6 cov-
`ers substrate 3 outside of the source/drain region 2. A
`polysilicon line 7 forms a gate electrode where it passes
`over an active area defined by edge 5. As illustrated in
`FIG. 1A, the contact window is an adequate distance d
`away from edge 5.
`However, in FIG. 1B contact window 1 has not been
`aligned properly with respect to source/drain region 2.
`While it does predominantly lie upon region 2 and
`therefore will permit subsequently added metal
`to
`contact source/drain 2, window 1 has no separation
`from edge 5 and indeed is partially lying on top of isola-
`tion 6. Because the contact window is an etched open-
`ing which will be filled by a conductive metal, if part of
`isolation 6 (either a field shield gate electrode or the
`substrate underlying a field oxide) is exposed by contact
`window 1 as in FIG. 1B, then when the metal is added,
`isolation element 6 (or the material beneath it) will be
`shorted to the source/drain region 2 and to the metal
`interconnect. Obviously, this is to be avoided.
`The problem is further illustrated in FIGS. 1C and
`1D. A cross-sectional View along line A—A of FIG. 1B
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`is shown in FIG. 1C where element 6 is shown illustra-
`tively as a field shield electrode 6a (defined in poly 1)
`next to a source/drain region 2 in the substrate 3. (For
`a discussion of field shield electrodes, see U.S. Pat. No.
`4,570,331 filed Jan. 26, 1984, Pat. No. 4,570,331, entitled
`“Thick Oxide Field-Shield CMOS Process” which is
`incorporated herein by reference). A gate electrode 7
`(defined in poly II) is shown above and adjacent to
`source/drain region 2. Over substrate 3 and on top of
`field shield electrode 6a and gate electrode 7 is shown a
`representative thickness of oxide 8. Contact window 1
`has been formed beneath an arrow 9 which represents
`the positioning of the contact window as set up by the
`fabrication equipment. It can be seen in FIG. 1C that
`part of field shield electrode 6a has been exposed by
`etching oxide 8 to create contact window 1. When
`metal is added, it will short electrode 60 to source/drain
`region 2. It will be apparent that, in the same manner,
`where contact window 1 is misaligned such that it lays
`over the edge of electrode 7, the edge of electrode 7
`would be exposed by etching oxide 8 to open contact
`window 1, and again a short would occur.
`A variation is shown in FIG. ID, which is also a
`cross-sectional view along line A—A of FIG. 1B. How-
`ever, in this case element 6 refers illustratively to a field
`oxide 6b next to source/drain region 2 in substrate 3.
`Gate electrode 7 next to the source/drain region 2 and
`oxide 8 are included. Contact window 1 has been
`formed beneath arrow 9 which represents the position-
`ing of the contact window as set up by the fabrication
`equipment.
`It can be seen in FIG. ID that part of the field oxide
`6b under arrow 9 has been removed by etching through
`oxide 8 to open contact window 1. (Dotted line 6'
`shows the original thickness of field oxide 6b before the
`contact window was etched.) Some field oxide 6b was
`removed because it cannot be distinguished during etch-
`ing from oxide 8.
`Integrated circuits are formed on large substrates (4"
`to 8" in diameter) which contain typically hundreds of
`circuits and typically million of contact windows. Since
`a material cannot be deposited or grown uniformly in
`thickness over such a large area (at worst :l0%), an
`overetch of 20% is common to insure that all contact
`windows on the entire substrate will be etched open.
`In FIG. 1D the edge of field oxide 6!) is tapered, as is
`common when the field oxide/active area pattern is
`formed by local oxidation of silicon. The misalignment
`of contact window 1 illustrated by arrow 9 has exposed
`the tapered thin edge 6bb of field oxide 6b to the contact
`window etch. Since the etch cannot distinguish be-
`tween field oxide 6b and oxide 8 and an overetch is
`required or ordinarily employed, a region 3’ of substrate
`3 which does not include source/drain 2 has been ex-
`posed. When metal is added, it will short substrate 3 to
`source/drain region 2.
`In current high density dynamic random access mem-
`ories, a contact window will be on the order of 1.0 to 1.5
`microns in length and width. Often it will be located on
`an active area next to a polysilicon word line and isola-
`tion edge, such as element 7 and line 5 in FIGS. 1A, 1B,
`1C, and 1D. Perpendicular to the word line will be a bit
`line formed in an upper layer of metal. At this intersec-
`tion of the bit line and word line will be a memory cell.
`The contact window will allow the metal from the bit
`line to contact the source/drain region. The contact
`window may be separated by only about 1 micron from
`the polysilicon word line and the isolation edge.
`
`

`
`4,686,000
`
`4
`
`3
`However, the size of the contact window 1 itself has
`tolerances in its fabrication so that its actual dimensions
`may be up to 0.5 microns larger than the specified di-
`mension for the contact window. If the contact window
`is larger than specified, it will be closer to the polysili-
`con word line and the isolation edge.
`Accordingly,
`it
`is necessary to locate the contact
`window so as not to cause a short. One commonly
`desires to align the contact window to some known
`edge, typically one edge of a gate electrode or an isola-
`tion edge (e.g., an edge of field shield 6a or field oxide
`6b). However, there is a nonzero tolerance in aligning
`one level to the next level in forming an integrated
`circuit. This tolerance t (typically 0.5 microns for mini-
`mum feature sizes in the 1-2 micron range) is inherent in
`the wafer stepper equipment used for fabrication. If
`there were a misalignment of the contact window with
`respect to an isolation edge or other element, this could
`result in an undesired short unless there were a wide
`margin of error.
`Consider with respect to FIG. IA that contact win-
`dow 1 is to be aligned with respect to a sharp edge in
`any given layer,
`for example, edge 5. To prevent
`contact window 1 from unintentionally contacting iso-
`lation 6 to the right of line 5 despite the position toler-
`ance t, then the design rule for positioning the window
`would require it to be located nominally at a distance of
`at least t from edge 5.
`The problem of alignment tolerance becomes more
`severe with the use of multiple layers. If a contact win-
`dow is aligned to an element in Poly I, because there is
`a similar tolerance t also between poly I and poly II,
`there will be an even larger uncertainty (slightly less
`than 2t) of the location of the contact window with
`respect to the elements formed in Poly II.‘Similarly, if
`the contact window is aligned to an element defined in
`the substrate such as a field oxide edge, there will be an
`uncertainty of approximately 2t in the placement of the
`"contact window with respect to the edge of poly I and
`V’ poly II (provided they are both aligned to the field
`(‘oxide edge).
`In practice,
`the contact windows are
`‘aligned to the most critical layer, with a distance sepa-
`rating the contact from elements defined in that layer of
`greater than t. The distance separating the contacts
`from elements formed in other layers is then much
`larger than t.
`Considering all of these tolerances, then, in order to
`ensure that the metal does not short to any polysilicon
`feature or the substrate through the contact window,
`wide margins would be necessary between contact win-
`dows and nearby elements. This would increase the size
`of the integrated circuit significantly, resulting in fewer
`die per wafer and lower yield.
`I
`Such design rules, imposed by the tolerance obtained
`on optical alignment equipment and in the fabrication
`process, lead to wasted or unnecessarily large chip ar-
`eas. These design rules prevent designs from being
`scaled as aggressively as posssible. A design rule requir-
`ing an active area opening to be large could be relaxed
`if it were possible to provide self-alignment of the
`contact window with respect to a nearby element to
`which contact is to be avoided. In other words, it would
`be advantageous to permit variation in the position of a
`contact window with respect to the edge of active area
`or source/drain, even to the extent of allowing it to
`overlap a polysilicon or other element, provided that
`there would be not short circuit occasioned by the over-
`lap. Some technique to prevent such shorting would be
`
`highly desirable, but no solution suitable for aligning
`contact windows to gate electrode edges or isolation
`edges for a VLSI process has come forth.
`One possible solution referred to in Batra U.S. Pat.
`No. 4,466,172 has been devised for self-aligning contact
`windows to polysilicon gate electrodes. This involves
`using a nitride/oxide gate dielectric so that oxidation of
`the polysilicon gate electrode can be achieved with
`oxide grown on the tops and sides of the polysilicon
`elements and not on the source and drain regions of the
`substrate. An etch stop layer of nitride is then added
`over the structure and interlevel dielectric is then de-
`posited. Contact windows are patterned and etched
`down to the nitride etch stop layer. Then the etch stop
`layer is removed where exposed by the contact win-
`dow. Then the oxide over the source/drain is removed
`and metal is deposited. The differential between the
`thickness of oxide on the source/drains versus that on
`the top and sides of the polysilicon gate electrode re-
`sults in contact being made to the source/ drain region
`but not to the polysilicon gate electrode.
`However, the use of this approach has been fore-
`stalled in fabricating circuits of VLSI dimensions for
`several reasons. First, the use of nitride/oxide under the
`gate electrode is not common and is usually not desir-
`able for standard n-channel, p-channel, and CMOS
`processes. Such a nitride/oxide gate dielectric is used in
`the prior art to prevent oxidation of the source/drain
`region while a thick oxide, of “critical importance”
`(Batra, col. 3, line 6) is grown on the top and sides of the
`polysilicon electrode. This thick oxide protects the gate
`electrode from making contact with the metal.
`However, this oxide is subjected to hydrofluoric acid
`(HF) during the removal of the gate oxide. It is well
`known that oxides grown on polysilicon when sub-
`jected to HF solution have a much increased pinhole
`density over those same oxides as grown. These pin-
`holes will
`result
`in shorts between the metal and
`polysilicon when the metal is added. In addition, VLSI
`circuits are frequently fabricated with gate electrode
`materials which are not conveniently oxidized, such as
`polycide structures and silicides. This ‘raises a problem
`for the Batra process. Also, transistor structures opti-
`mized for
`1 micron and submicron channel
`lengths,
`such as lightly doped drain structures, require sidewall
`spacers which are not generally grown but are depos-
`ited and are of a specific thickness (O.1—O.5 microns)
`determined from the desired device characteristics.
`These sidewall spacers are probably inadequate to pre-
`vent metal to gate shorts. The use of the Batra process
`is not compatible with the formation of these devices.
`Finally, for transistors in the VLSI regime (under 2
`micron poly width) the sidewall oxide required by
`Batra consumes too much space. Hence, no manufactur-
`able, commercially acceptable process is apparent for
`permitting self-aligned contact windows in such struc-
`tures. Aggressive design rule scaling with respect to
`contact window spacing is not possible when thick
`interlevel dielectric is used.
`One object of this invention therefore is to provide a
`self-aligned contact process which is independent of
`gate dielectric type.
`Another object of the present invention is to provide
`a process for self-aligned contacts in a VLSI circuit
`which is independent of sidewall processes (on the gate
`electrode) used to optimize device performance. For
`example, the process should tolerate the absence of
`unnecessary or undesirable oxide on the sidewalls (un-
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`.
`
`

`
`4,686,000
`
`5
`like Batra). Presently, it is undesirable to oxidize some
`polycide gate electrodes such as titanium silicide. The
`process should also tolerate, on the other hand,
`the
`addition of any amount of oxide to the sidewall for any
`purpose such as isolation from a later established inter-
`connect or other element, or the addition of any mate-
`rial to the sidewall for the purpose of providing a spacer
`to fabricate optimized VLSI transistor structures such
`as double diffused drain or lightly doped drain devices.
`Therefore, another object of the present invention is
`to provide a process for locating and etching contact
`windows in transistors without imposing a design rule
`requiring wasted silicon area, and which can be applied
`to all gate and field oxide or field shield edge simulta-
`neously.
`Another object of the invention is to provide a tech-
`nique for self-aligning contacts in a semiconductor
`structure despite the use of interlevel dielectric, which
`ordinarily is relatively thick.
`A further object is to provide a method which per-
`mits reliable etching of the contact window despite
`tolerances in its placement, without jeopardizing the
`integrity of the memory cell, transistor or other device.
`SUMMARY OF THE INVENTION
`
`6
`stop and any “stick” of interlevel dielectric remaining
`after the etch stop layer is removed protects the side of
`the element. In the case of a field oxide edge, subsequent
`processing makes use of the relative different in thick-
`ness between the field oxide and the oxide covering the
`active area to permit overetching of the contact win-
`dow without etching entirely through the oxide cover-
`ing the field region. As shown below, the requirement
`that the field oxide edge be vertical can be relaxed
`somewhat depending on the extent of the diffusion of
`the source/drain implant underneath that edge. Thus
`metallization can be added, and contact can be made to
`the source/drain region without shorting to the top or
`edge of a polysilicon element or the substrate under the
`edge ofa field oxide.
`The extra layer added for the purpose described
`above will act as an etch stop in that it etches much
`slower than the interlevel dielectric above it. Silicon
`nitride is preferred for a variety of reasons, but one
`could use another material. One material which may
`work as an etch stop is aluminum oxide. Other sub-
`stances may be useful for the process, as long as they
`can be used as an etch stop for the interlevel dielectric,
`are insulators, and can be removed in subsequent pro-
`cess steps.
`The present invention is applicable to single and dou-
`ble poly processes, single and multilevel metal pro-
`cesses, processes using polycide, and processes using
`conventional local oxidation isolation, field-shield isola-
`tion, and other schemes including reduced bird’s beak
`isolation schemes (e.g., sealed interface local oxidation).
`It is applicable to aligning contacts to Poly 1, Poly II,
`isolation edges such as an edge of field oxide, or other
`edges. It applies to PMOS, NMOS, CMOS, and other
`integrated circuit technologies. It is especially useful in
`fabricating CMOS RAMS which are 256K or larger.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`In describing the present invention, reference is made
`to the accompanying drawings wherein:
`FIG. 1A is a sketch showing a contact window on an
`active area near an isolation edge and a gate electrode
`and is helpful in understanding one of the problems
`solved by the present invention:
`FIG. 1B is similar to FIG. 1A but shows a misaligned
`contact window;
`FIGS. 1C and ID are cross-sectional views along
`lines A—A of FIG. 1B;
`FIG. 2 is a cross~sectional illustration showing one
`illustrative structure according to various aspects of the
`present invention;
`FIGS. 3—'7 relate to the fabrication of the structure
`shown in FIG. 2. Of these, FIG. 3 shows two polysili-
`con gate electrodes on a susbstrate, covered by oxide;
`FIG. 4 shows a contact opening cut through photore-
`sist to the right gate electrode of FIG. 3 and shows ion
`implanted source and drain regions in the active area of
`the substrate, after heat driving;
`FIG. 5 shows an etch stop in layer form covering an
`intermediate, partially complete structure;
`FIG. 6 shows an interlevel dielectric layer over the
`etch stop layer;
`FIG. 7 shows the structure of FIG. 6 after it has been
`etched through Contact windows to the etch stop layer,
`and shows in dotted lines the further etching to be done
`by a different etchant (in the preferred embodiment);
`FIGS. 8A, 8B and 8C show, in expanded scale, how
`the_ present invention permits a contact" window for the
`
`10
`
`15
`
`20
`
`25
`
`35
`
`40
`
`45
`
`These and several other objects and advantages are
`obtained by providing a self-aligned contact process
`which involves establishing gate electrodes and/or iso-
`lation edges which are substantially vertical with re-
`spect to the substrate surface, protecting the tops of 30
`these elements with an insulating oxide, protecting the
`top and sides of these structures with a layer to serve as
`an etch stop, and removing the etch stop in an aniso-
`tropic manner, so as not to remove the etch stop from
`the sidewalls of the gate electrodes or isolation edges.
`Such etch stop is established between the relatively
`thick interlevel dielectric and the oxides covering the
`gate electrode and substrate. The etch stop preferably is
`silicon nitride. This permits the nominal position of the
`Contact window over the active area to be relatively
`independent of design rules which would otherwise
`prescribe a relatively large distance between a poly
`edge or field oxide edge and the nearest edge of the
`Contact window. This results in self-alignment, wherein
`the Contact window location due to tolerance in the
`fabrication equipment may partially overlap a gate elec-
`trode or isolation edge such as the edge of field oxide or
`a field-shield edge. Despite this departure from the
`nominal or ideal location, the contact window can be
`formed without undesirable short circuits.
`This is done illustratively by fabricating the poly
`edge or field oxide edge to be substantially vertical, and
`by providing an oxide covering over only the top of the
`poly element. Thereafter the etch stop material is de-
`posited followed by the interlevel dielectric. Subse-
`quently, the contact window is etched down to the etch
`stop. Thereafter, the exposed portion of the etch stop on
`top of the element to be protected is removed from the
`partially completed contact window in a manner so as
`to leave a “stick” of etch stop on the side of said ele-
`ment. In the case of self-alignment to a gate or field-
`shield transistor electrode edge, subsequent processing
`makes use of the relative thickness differences between
`the oxide covering the gate electrode as compared to
`the oxide over the active area to permit overetching in
`the contact window without etching entirely through
`the oxide covering the gate electrode or other element
`to which contact is not to be made. The “stick” of etch
`
`50
`
`55
`
`60
`
`65
`
`

`
`7
`source or drain to be located partially over gate or
`field-shield electrodes, without leading to a short to the
`gate or field-shield electrodes;
`FIGS. 9A and 9B show, in expanded scale, how the
`present invention permits a contact window for the
`source or drain to be located partially over a field oxide
`edge, without leading to a short to the substrate under-
`lying the field oxide;
`FIG. 10A is a plan view of some DRAM memory
`cells fabricated with a double poly field-shield process
`and the present invention;
`FIG. 10B is a schematic circuit diagram of FIG. 10A;
`FIG. 10C is a sectional View along lines B—B of FIG.
`10A;
`FIG. 10D is a sectional view along lines C—C of
`FIG. 10A; and
`FIG. 10E is a sectional view similar to FIG. 10D but
`with the contact window misaligned toward the edge of
`the source/drain region.
`DETAILED DESCRIPTIONS
`
`The following descriptions are illustrative of fabricat-
`ing contact windows including, as part of the method,
`providing a layer of material to be used as an etch stop.
`Applications Of Self-Aligned Contacts To Gate Or
`Field-Shield Edges
`FIG. 2 shows an illustrative semiconductor structure
`near the completion of processing according to the
`invented process applied illustratively for establishing a
`self-aligned contact window to a gate electrode or field-
`shield electrode edge. The structure is fabricated with,
`for ease of explanation, a single poly process. Use of the
`invention with other processes will be described subse-
`quently.
`FIG. 2 illustrates a layer 10 operable as an etch stop
`and a substrate 12 having poly gate electrodes 14 and 16
`over a relatively thin gate oxide 18. Between the gate
`electrodes but in the substrate is an arsenic, phospho-
`rous or boron implant 20 which acts as a transistor
`source or drain. Between layer 10 and the gate elec-
`trodes 14, 16 is a layer of oxide 24 having a relatively
`thick portion 24a and a relativelygthin portion 24b (on
`the order to l00 to 300 angstroms). Over gate electrode
`16, the oxide has a recess for a window 30 to permit
`Contact to the gate electrode. A further contact window
`32 is shown between gate electrodes 14 and 16 to permit
`contact to the source or drain. A very thick BPSG
`(borophosphosilicate glass) dielectric 34 covers the
`layer 10 except in contact windows 30 and 32. This
`structure of FIG. 2 is ready for etching through etch
`stop layer 10 in openings 30 and 32 and etching through
`thin oxide 24b at opening 32 to open a contact window.
`The process for producing this structure, or a closely
`related one, will now be explained.
`Referring now to FIG. 3, on a silicon substrate 12, a
`thin layer of gate oxide 18 is grown, and then a layer of
`polysilicon is deposited and doped. Oxidation of the
`poly occurs next to create a relatively thick (illustra-
`tively 3000 angstroms) oxide over the polysilicon layer.
`The definition of the polysilicon next occurs to result in
`the formation of a transistor gate electrode, leaving
`some of the gate oxide 24b in the source/drain regions.
`Illustratively, each gate electrode 14, 16 has a thickness
`of about 3000 angstroms, the gate oxide 18 below the
`gate electrode has a thickness of about 300 angstroms,
`and the oxide 24a over the polysilicon has a thickness of
`about 3000 angstroms. Illustratively, the oxide 24b over
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4,686,000
`
`8
`the source and drain regions has a thickness of about
`100 to 200 angstroms. Then source and drain implants
`of arsenic, boron or phosphorous are done, using such
`masks as customary to those skilled in the art. The im-
`plants impinge upon and enter the substrate. Next, the
`implants 20 are activated and are heat driven laterally
`and downward, as shown in FIG. 4.
`Referring further to FIG. 4, the next step is to mask
`contacts to polysilicon gate electrode 16 with openings
`in a photoresist 36 so that oxide 24a can be etched selec-
`tively down to the gate electrode. This will result in the
`contact window 30. This etching process can be a selec-
`tive dry etch using a standard process in a plasma, reac-
`tive ion or reactive sputter etch apparatus with a fluoro-
`carbon gas mixture. A Plasmatherm PK or Lam 590
`plasma etcher would be suitable. The photoresist 36 is
`then removed from the structure.
`
`Turning to FIG. 5, etch stop layer 10 is added to this
`intermediate, partially complete structure. Preferably
`this is a layer of silicon nitride (Si3N4) which is put on
`by a chemical" vapor deposition using Silane (SiH4) or
`dichlorosiliane (SiH2Cl2) with ammonia (NH3). This is
`heated in a furnace tube to about 700° C. to react the
`component gases. The deposition is allowed to occur
`until a layer 10 having a thickness of about 1000 ang-
`stroms is obtained. Other material can be used which
`has insulating properties, can be used as an etch stop for
`interlevel dielectric, can be subsequently removed se-
`lectively and anisotropically with respect to the inter-
`level dielectric, and can be left in the structure without
`causing subsequent processing or reliability problems.
`Silicon nitride is preferred, but other applications may
`make use of A1203. FIG. 5 shows the etch stop layer 10
`at this stage of processing.
`Turning to FIG. 6, an interlevel dielectric layer 34,
`such as about 7000 to 9000 angstroms of BPSG, next is
`added on top of the structure. FIG. 6 illustrates a struc-
`ture at this stage of processing. At this stage, interlevel
`dielectric layer 34 can be conformal, or can be reflowed
`if a substantially flat surface is required, such as when
`multiple levels of metal will subsequently be used. Line
`34a shows the top surface of BPSG 34 under these
`conditions.
`Following this, a masking is done for the contact
`window to the poly electrode 16 and the contact win-
`dow to the source or drain region 20 between the two
`electrodes 14 and 16. The contact window 32 will be
`self-aligned with respect to the polysilicon gate elec-
`trodes 14, 16 which have an oxide 24a thereover which
`is thicker than the oxide 24b covering the source/drain
`20. Because contact window 32 will be self-aligned with
`respect to the polysilicon electrodes, in setting up its
`position in the fabrication process, it can be aligned to
`another edge, such as, in the case of a single poly pro-
`cess, the edge of an isolation oxide (not shown in FIGS.
`2-7). In the case of a double poly field-shield process,
`the contact window can be aligned to the edge of the
`poly II active transistor gate electrode. In the case
`where a nearly vertical field isolation edge or field-
`shield isolation is used, or all poly layers have a thick
`oxide on top, alignment can be made to any convenient
`level because self-aligned contacts will be made to the
`isolation and all poly levels with this process.
`Next, using a first etchant, the BPSG interlevel di-
`electric 34 is etched to the etch stop layer 10, layer 34 is
`then reflowed, and using a second etchant, layer 10 and
`the oxide 24b therebelow are then etched.
`
`~
`
`

`
`9
`Preferably these etching steps are done by dry etch-
`ing alone. The first etchant will etch the BPS 34 aniso-
`tropically and selectively with respec