US007693924B2
`
`(12) United States Patent
`Cho et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,693,924 B2
`Apr. 6, 2010
`
`2N-POIN '1‘ AND N-POIN '1‘ Fl+"l‘/ll~‘F'l‘ DUAL
`MODE PROCESSOR
`
`Inventors: Sang In Cho, Daejeon (KR); Sangsung
`Choi, Daejeon (KR); Kwang Roh Park,
`Daejeon (KR)
`
`Assignee:
`
`Electronics and Telecommunications
`Research Institute, Daejeon (KR)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 1190 days.
`
`(21)
`
`Appl. No.: 11/264,886
`
`(22)
`
`(65)
`
`Filed:
`
`Nov. 2, 2005
`
`Prior Publication Data
`
`US 2006/0093052 A1
`
`May 4, 2006
`
`(30)
`Nov. 3, 2004
`
`Foreign Application Priority Data
`
`(KR)
`
`.................... .. 10—2004—0088768
`
`(52)
`(58)
`
`Int. Cl.
`(2006.01)
`G06F 1 7/14
`U.S. Cl.
`.................................................... .. 708/404
`Field of Classification Search ..................... .. None
`See application file for complete search history.
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`3/1994 Sayegh
`5,293,330 A
`............ .. 370/210
`1/2006 Greaves et al.
`6,990,062 B2 *
`7,461,114 B2 * 12/2008 Nakazuru el al.
`. 708/404
`
`...................... .. 708/403
`6/2009 Pisoni
`7,543,009 B2 *
`2006/0271613 Al "‘ 11/2006 Mitsuishi et al.
`.......... .. 708/404
`2007/0073796 A1 *
`3/2007 Meilliac et al.
`........... .. 708/404
`
`FOREIGN PATENT DOCUMENTS
`
`10-20040026910
`
`4/2004
`
`OTHER PUBLICATIONS
`
`“Coinputationally Eflicient Fast Algoritlnn and Architecture for the
`IFFT/FFT in DMT/OFDM Systems,” An-Yeu VVu et al, 1998 IEEE
`Workshop on Signal Processing Systems, pp. 356-365.
`
`* cited by examiner
`
`Primary Examiner David H Malzahn
`(74) Attorney, Agent, or Firm—Ladas & Parry LLP
`
`(57)
`
`ABSTRACT
`
`A 2N-point and N-poi11t FFT/IFFT dual mode processor is
`provided. The processor includes a butterfly operator, the flrst
`and second MUXs, and the first and second N-point EFT
`processors. The butterfly operator receives 2N data and but-
`terfly-operates on the received 2N data when receiving a
`control signal ‘0’ from the controller. The flrst and second
`MT TXs respectively receive results from the butterfly operator
`to output the results in an increment of N when receiving a
`control signal ‘0’ from the controller, and respectively outputs
`different N data when receiving a control signal ‘ 1 ’ from the
`controller. The first and second N-point
`l4l~"1' processors
`N-point FFT operate on the results from the first and second
`MUXS and respectively output the same under control of the
`controller. Since the N-point FFT operation can be si1nulta-
`neously performed two times at a receiver, the performance of
`the receiver can be enhanced.
`
`2 Claims, 6 Drawing Sheets
`
`220
`
`250
`
`10a ~x[N-H ----- -- x[0]
`
`l0b~x[2N-1] ----- »- x[N]
`
`100 ~x[N-1]‘ ----- -- x[0]'
`
`
`
`IBUTTERFLYOPERRTOR
`
`FIRST
`N-PO I NT EFT
`PROCESSOR
`
`SECOND
`N-POI NT FFT
`PROCESSOR
`
`I
`
`CONTROLLER
`
`1-» 210
`
`ZTE/SAMSUNG/HTC 1030-0001
`
`

`
`U.S. Patent
`
`Apr. 6, 2010
`
`Sheet 1 of6
`
`US 7,693,924 B2
`
`ZTE/SAMSUNG/HTC 1030-0002
`
`

`
`U.S. Patent
`
`Apr. 6, 2010
`
`Sheet 2 of6
`
`US 7,693,924 B2
`
`F I G _ 23
`
`(PRIOR ART)
`
`CONVENTIONAL
`FJLTFFI
`
`9531559
`Hum
`
`F 1 G . 2b
`
`(PRIOR ART)
`
`OONVENT l0flAL
`FILTER
`
`ngsmgg
`Hum
`
`i ¢
`
`ZTE/SAMSUNG/HTC 1030-0003
`
`

`
`U.S. Patent
`
`Apr. 6, 2010
`
`Sheet 3 of6
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`US 7,693,924 B2
`
`FIG. 3
`
`8%.1<:C:LIJ
`CLC)
`>-_n
`l...I_
`D:LIJ
`|.——
`5B3
`
`SECOND
`
`J N-P0INT EFT
`PROCESSOR N
`
`CONTROLLER
`
`ZTE/SAMSUNG/HTC 1030-0004
`
`

`
`U.S. Patent
`
`Apr. 6, 2010
`
`Sheet 4 of6
`
`US 7,693,924 B2
`
`o 250 .7 o
`o
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`: I:\\,vI4:III.:>xox,
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`ZTE/SAMSUNG/HTC 1030-0005
`
`

`
`U.S. Patent
`
`Apr. 6, 2010
`
`Sheet 5 of6
`
`US 7,693,924 B2
`
`SECOND
`
`N-POINT FFT
`
`PROCESSOR N
`
`CONTROLLER
`
`ILL]
`__J
`o_
`F_I:
`I.
`].—-
`
`2L
`
`EI
`
`ZTE/SAMSUNG/HTC 1030-0006
`
`

`
`U.S. Patent
`
`Apr. 6, 2010
`
`Sheet 6 of6
`
`US 7,693,924 B2
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`ZTE/SAMSUNG/HTC 1030-0007
`
`

`
`US 7,693,924 B2
`
`1
`2N-POINT AND N-POINT FFT/IFFT DUAL
`IVIODE PROCESSOR
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to a 2N—point and N-point fast
`Fourier
`transform (FFT)/inverse fast Fourier transform
`(IFFT) dual mode processor, and more particularly,
`to a
`2N-point and N-point FFT/IFFT dual mode processor for
`allowing a 2N-point FFT processor and a N-poi11t FFT pro-
`cessor to operate in a dual mode in achieving an IFFT/FFT
`processor used in a orthogonal frequency division multiplex-
`ing (OFDM) system.
`2. Description of the Related Art
`As known in the art, OFDM means a method for dividing
`data having a high-speed transmission rate into a plurality of
`data lines having a low-speed transmission rate and simulta-
`neously transmitting the plurality of data lines using a plural-
`ity of sub—earrier waves. A process for making such sub-
`carrier waves and conveying the data on the sub—earrier waves
`is an IFFT/FFT operation. The transmission terminal of
`OFDM requires an IFET operation so as to convey data on a
`plurality of sub-carrier waves, and the reception terminal of
`OFDM requires an FET operation so as to obtain data from a
`plurality of sub-carrier waves.
`FIG. 1 is a block diagram illustrating processes performed
`by an IFFT processor of the transmission terminal and by an
`FFT processor ofthe reception terminal. Referring to FIG. 1,
`an N-point IFFT processor 10 of an OFDM system conveys
`data on n sub-carrier waves. At this point, after a guard inter-
`
`2
`val (GI) is added to an N-point IFFT-processed signal at a next
`block 11, an N-point IFFT-processed signal is delivered to a
`digital—to—analog converter (DAC) 12. After that. the spec-
`trum of a signal from the DAC 12 has frequency spectrum
`waveforms 1a, 1b, and 1 c as illustrated in FIG. 2A. A low pass
`filter (LPF) 13 is used to pass only a baseband signal compo-
`nent 1a from the repeated frequency components.
`FIG. 2 is a view illustrating the spectrum of an N -point
`IFFT signal after the DAC 12 of the transmission terminal
`illustrated in FIG. 1. At this point, the frequency spectrums
`1a. 1b, and 1c of a signal are repeated by a period F(b). To
`convey a signal on a carrier wave frequency, only a baseband
`signal component la should be obtained and the other signal
`components lb and 10 should be removed. For that purpose,
`the LPF 13 is required as described above.
`The above obtained baseband signal la is wirelessly trans-
`mitted through a local oscillator 14 and an anterma 15. The
`reception terminals 16, 17, and 18 recover data using reverse
`processes with respect to the processes performed at the
`transmission terminals 11 to 15. Referring to FIG. 1, the
`OFDM system requires the N-point IFFT processor 10 ofthe
`transmission terminal and the N-point FFT processor 18 of
`the reception terminal. At this point, the IFFT processor can
`be replaced by the FFT processor. That is, when inputs ofthe
`real part and the imaginary part in the FFT processor are
`exchanged and the real part and the imaginary part of an
`output are exchanged, the IFFT operation can be possible.
`The proof thereof can be provided when A(k) and B(k) of
`Equation 1 is compared with a(n) and b(n) ofEquation 2 inthe
`following Equations 1 and 2.
`
`Equation 1
`
`X(/<) = AK/<) + J/Bt/<),
`
`Mn) = aw) + Mn)
`
`A(k) +1/Blik) =
`
`{a(n) + jb(fl)}{L‘0S[
`
`”
`
`Zn
`— J/sin(j/—’;]kn]}
`
`[la(Iz)Cos6,m_ + bt_'n)si11€/1,,
`
`l + _,ll{—z1(Il)S1110/m + l7(n)cos0/,,}]
`
`n
`
`{a(n)cos0m + b(n)sin9kn}
`
`n
`
`Bik)
`
`{—a(n)sin9t,, + b(n)cos0k,, I
`
`ZTE/SAMSUNG/HTC 1030-0008
`
`

`
`2/
`.'V—l
`k:u
`IFFT: X(n) = Z X(k)eJr7‘”-
`
`US 7,693,924 B2
`
`Fiquati on 2
`
`.Z7r‘...37r
`.,
`., 1’,
`am) +_[bI,n) = N
`{Atkj + [BL/()}{COS[_,7W/(I'll+_[iS11|{_flW/Vflj}
`
`=
`
`[|A(/c)cos6‘k,, — B(/<)sin0,(,,] + 1/[At/c )S1]10,(,, + B(/<)cos6‘,(,,]]
`
`[z(n) :
`
`b(n) =
`
`,(_
`
`I(:
`
`{A(k)sin€,v_.,, + A(l<)cos9k,,}
`
`{B(k)cos6,,,, + A(k)sin9k,,}
`
`As described above, the N -point FF'l' processor is replaced
`by the N -point lFF'l' processor in the OFDM system of FIG.
`1.
`
`Referring to FIG. 2, to convey a signal on a desired carrier
`wave frequency, only a baseband signal component la should
`be obtained and the other signal components lb and 1c should
`be removed. For that purpose, the LPF 13 is required as
`described above. To pass only the baseband signal component
`la a11d remove the signal lb having a main frequency F(b) in
`its frequency components, the LPF l3 having a very narrow
`transition band is required. However, when the transition
`band of the LPF 13 is larger than the interval of the repeated
`OFDM signal spectrum, noises are generated.
`To solve such a problem, the transition band of the LPF I3
`is made very narrow or the interval of the repeated OFDM
`signal spectrum is widened so that noises may not be gener-
`ated.
`
`At this point, when the interval between the intervals ofthe
`repeated frequency spectrums is too narrow, the LPF 13 is
`difficult to realize and filtering carmot be performed properly.
`To solve this problem, it is possible to widen the interval
`between the repeated frequency spectrums by inserting, at the
`IFFT processor, N-point ‘0‘ into N-point data. In that case, the
`IFFT processor performs an operation using 2N-point and the
`l4l~"l' processor perfomis an operation using N -point. As
`described above, the N-point FFT processor and the 2N-point
`IFFT processor can be simultaneously required in one sys-
`tem.
`
`However, in the case where the N-point FFT processor and
`the 2N—point IFFT processor can be simultaneously required
`in one system in the conventional art, the N-point FFT pro-
`cessor and the 2N-point FFT processor are separately and
`respectively designed to realize a system, so that a system
`design is diflicult and the manufacturing costs increase.
`
`SUMMARY OF IH 4 INV 4 N I ION
`
`Accordingly, the present inven ionis directed to a 2N-point
`and N-point FFT/IFFT dual mode processor, which substan-
`tially obviates one or more problems due to limitations and
`disadvantages of the related art.
`It is an object ofthe present invention to provide a 2N-point
`and N-point FFT/IFFT dual mode processor capable of efli—
`ciently using a hardware by allowing one processor to per-
`form a 2N-point FFT processor operation and a11N-point FFT
`processor operation in realizing a FFT/IFFT processor, or
`
`capable of enhancing the performance of a receiver by allow-
`ing an N-point operation to be performed two times simulta-
`neously.
`Additional advantages, objects, a11d features of the inven-
`tion will be set forth in part in the description which follows
`and in part will become apparent to those having ordinary
`skill in the art upon examination of the following or may be
`learned fror11 practice of the invention. The objectives and
`other advantages of the invention may be realized and
`attained by the structure particularly pointed out in the written
`description and claims hereof as well as the appended draw-
`ings.
`To achieve these objects and other advantages and in accor-
`dance with the purpose of the invention, as embodied and
`broadly described herein, there is provided a ZN-point and
`N-point FFT/IFFT dual mode processor including: a control-
`ler for outputting a corresponding control signal when an
`operation is a 2N-point FFT operation and outputting a cor-
`responding control signal when an operation is a N-point FFT
`operation;
`a butterfly operator
`for
`receiving ZN data
`.
`(x[N—l] .
`. x[0j, x[2N—lj .
`.
`. x[Nj) to perform a butterfly
`operation when a 2N-point FFT operation control signal is
`received from the controller; first and second MUXs for
`receiving results of the butterlly operator to output
`the
`received results in an increment of N when a 2\I-point FFT
`operation control signal is received from the controller, and
`receiving different N data (x[N—l] .
`. .x[0], x[N—l]' .
`. .x[0]‘)
`to output the same when a N-point FFT operation control
`signal is received from the controller, a first \I-point FFT
`processor for N -point Fl~"l'-operating on outputs from the first
`MUX to output even-numbered results of the 2\I-point FFT
`when a 2N—point FFT operation control signal is received
`from the controller, and N-point FFT-operating o11 outputs
`froin the first MUX to output the same when a \I-point FFT
`operation control signal is received from the controller; and a
`second N-point FFT processor for N-point FET—operating on
`outputs from the second MUX to output odd-numbered
`results of the 2N-point FFT when a 2N-point F :T operation
`control signal is received from the controller, and N-point
`FFT—operating on outputs from the second MUX to output the
`same when a N-point FFT operation control signal is received
`from the controller.
`
`In another aspect ofthe present invention, there is provided
`a 2N—point and N-point FFT/IFFT dual mode processor
`including: a first N-point FFT processor for receiving and
`N-point FFT operating on N data (x[N—l] .
`.
`. x[0]) to output
`the processed data; a controller for outputting a correspond-
`
`ZTE/SAMSUNG/HTC 1030-0009
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`US 7,693,924 B2
`
`6
`second MUXs 230 and 240, a first N—point FFT processor
`250, and a second N—point FFT processor 260.
`At this point, the controller 210 outputs a control signal ‘0’
`for a 2N—point FFT operation, and a control signal ‘I ’ for an
`N—point FFT operation to the butterfly operator 220, the first
`and second MUXs 230 and 240, and the first and second
`N—point FFT processors 250 and 260.
`When a control signal ‘0’ is received fro111 the controller
`210, the butterfly operator 220 receives 2N data (x[N—l] .
`.
`.
`x[0j, x[2N—lj .
`. .x[Nj)10a and 10/3, butterfly-operates onthe
`ZN data, and outputs the operated data to the first and second
`MLXS 230 and 240, respectively.
`Also, the first MUX 230 is connected to the first N—point
`FF" processor 250 to output results from the butterfly opera-
`tor 220 to the first N—point FFT processor 250 when a control
`signal ‘0’ is received from the controller 210. On the contrary,
`the first MUX 230 passes N data (x[N—l] .
`. .x[0]) 10a to the
`firs N—point FFT processor 250 when a control signal ‘l’ is
`received from the controller 210.
`
`The second MUX 240 is com1ected to the second N—point
`FF" processor 260 to pass results fron1 the butterfly operator
`220 to the second N—point FFT processor 260 when a control
`signal ‘0’ is received from the controller 210. On the contrary,
`the second MUX 240 passes N data (x[N—l]'
`.
`. .x[0j‘) 100 to
`the first N—point FFT processor 250 when a control signal ‘ 1 ’
`is received from the controller 210.
`
`When a control signal ‘0’ is received from the controller
`210, the first N—point FFT processor 250 N—point FFT-oper-
`ates on outputs fron1 the first MUX to output even-numbered
`results of a 2N-point FF". On the contrary, when a control
`signal ‘ l ’ is received froin the controller 210, the first N—point
`FFT processor 250 N—point FFT—operates on outputs from the
`first MUX and outputs the same.
`When a control signal ‘0’ is received from the controller
`210, the second N—point FFT processor 260 N—point FFT-
`operates on outputs from the second MUX to output odd-
`11umbered results ofa 2N- point FFT. On the contrary, when a
`control signal ‘l’ is received from the controller 210, the
`second N—point FFT processor 260 N—point FFT—operates on
`outputs from the second MUX to output the same.
`FIG. 4 is a View illustrating an operation procedure of a
`4-point FFT processor. In operation, after an addition of a
`butterfly structure 120 is performed using two data for its
`input, the addition result is repeatedly multiplied by a twiddle
`factor 130. When the above operation is changed by a deci-
`mation in frequency (DIF) FFT operation to rapidly operate
`on a discrete Fourier transform ODFT) equation, the following
`Equation 3 is given.
`
`Equation 3
`
`5
`ing control signal when an opera ion is a 2N-point FF" opera-
`tion and outputting a corresponding control signal when an
`operation is a N—point FFT operation: a twiddle factor multi-
`plier for receiving N data (x[I\—l] .
`.
`. x[0]) to perform a
`twiddle multiplication operation when a 2N-point FF" opera-
`tion control signal is received from the controller; a MUX for
`passing results froin the twiddle factor multiplier when a
`2N-point FFT operation contro signal is received from the
`controller and passing other N data (x[N—l]'
`.
`.
`. x[0 ') when
`an N—point FFT operation control signal is received from the
`controller; and a second N—point FFT processor for \I—point
`FFT-operating o11 outputs from L16 MUX to output on d-num-
`bered results of the 2N-point 3FT when a 2N-point FFT
`operation control signal is received from the controller, and
`N—point FFT—operating on outpu s (x[N—l]' .
`.
`. x[0]') from the
`MUX to output the same when a N—point FFT operation
`control signal is received from the controller.
`It is to be understood that botl1 the foregoing general
`description and the following detailed description of the
`present invention are exemplary and explanatory and are
`intended to provide further explanation of the invention as
`claimed.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The accompanying drawings. which are included to pro-
`vide a further understa11ding of the invention, are incorpo-
`rated in and constitute a part of this application, illustrate
`embodiments of the invention and together with the descrip-
`tion serve to explain the principle of the invention. In the
`drawir1gs:
`FIG. 1 is a functional block diagram of a conventional
`OFDM system having N sub-carrier waves;
`FIG. 2A is a view illustrating the frequency spectrum of an
`N—point IFFT signal after a DAC in the OFDM system illus-
`trated in FIG. 1;
`FIG. 2B is a view illustrating the frequency spectrum of a
`2N—point IFFT signal after a DAC in the OFDM system
`illustrated in FIG. 1;
`FIG. 3 is a function block diagram of a 2N—point and
`N—point FFT/IFFT dual mode processor according to one
`embodiment of the present invention;
`FIG. 4 is a view illustrating a 4-point FFT operation
`explaining an operation of 2N-point and N—point FFT/IFFT
`dual mode processor illustrated in FIG. 3;
`FIG. 5 is a view illustrating a 8-point FFT operation
`explaining an operation of a 2N—point and N—point FFT/IFFT
`dual mode processor illustrated in FIG. 3;
`FIG. 6 is a function block diagram of a 2N—point and
`N—point FFT/IFFT dual mode processor according to another
`embodiment of the present invention; and
`FIG. 7 is a view illustrating a 8-point FFT operation where
`N-poi11t ‘O’ is inserted, to explain an operation of a 2N-point
`and N—point FFT/IFFT dual mode processor illustrated in
`FIG. 6.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`Reference will now be made in detail to the preferred
`embodiments ofthe present invention, examples ofwhich are
`illustrated in the accompanying drawings.
`FIG. 3 is a functional block diagram of a 2N-point and
`N—point FFT/IFFT dual mode processor according to one
`embodiment ofthe present invention. Referring to FIG. 3, the
`2N-point and N—point FFT/IFFT dual mode processor
`includes a controller 210, a butterfly operator 220, first and
`
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`US 7,693,924 B2
`
`7
`
`-continued
`
`X(2r+l)= H:
`
`[.v(n) —
`
`+
`
`WK,W’;
`
`FIG. 5 is a view illustrating a11 operation procedure of an
`8-point FFT processor. At this point,
`it is reveal that the
`operation procedure of the 8-point FFT processor is substan-
`tially the same as that ofthe 4-point FFT processor illustrated
`in FIG. 4, and the procedure has a structure in which there are
`two 4-point FFT processors 250 and 260 when the butterfly
`operator 220 and the twiddle factor multiplication are
`excluded. As revealed from FIG. 5, the 2N—point FFT proces-
`sor can perform an N-point FFT operation and can also per-
`form two N-point FFT operations simultaneously.
`First, the 2N-point FFT operation will be described. The
`controller 210 outputs a control signal ‘0’ to the butterfly
`operator 220. the first and second MUXs 230 and 240, and the
`first and second N-point processors 250 and 260. Then, the
`butterfly operator 220 receives a control signal ‘O’ from the
`controllcr2l0, butterfly-operates on 2N data (x[N— 1] .
`. .x[ ],
`x[2N—l] .
`.
`. x[N]) 10a and 10b, and outputs the operated data
`to the first and second MUXs 230 and 240, respectively.
`At this point, when a control signal ‘O’ is received from the
`controller 210, the first and second MUXs 230 and 240
`receive results from the butterfly operator 220, respectively,
`and output the received results in an increment ofN to the first
`and second N-point FFT processors, respectively.
`After receiving a control signal ‘O’ from the controller 210,
`the first N-point FFT processor 250 N-point FFT-operates on
`outputs from the first MUX 230 to output even—numbered
`results from the 2N-point FFT processor.
`After receiving a control signal ‘O’ from the controller 210,
`the second N-point FFT processor 260 N-point FFT-operates
`on outputs from the second MUX 240 to output odd-num-
`bered results from the 2N-point FFT processor.
`Now, the N-point FFT operation will be described.
`The controller 210 outputs a control signal ‘I’ to the but-
`terfly operator 220, the first and second MUXS 230 and 240,
`and the first and second N-point processors 250 and 260.
`Next, the first and second MUXs 230 and 240 pass differen
`N data (x[N—l] .
`. .x[O], x[N—l]', .
`.
`. x[0]‘) 10a and 10c to the
`first and second N-point FFT processors 250 and 260, respec-
`tively, under control of the controller 210. The first N-poin
`FFT processor 250 N-point FFT-operates on outputs form the
`first MUX 230 to output the same, and the second N-poin
`FFT processor 260 N-point FFT-operates on outputs form the
`second MUX 240 to output the same.
`Now, description will be made in detail for a ZN-point anc
`N-point FFT/IFFT dual mode processor where an N-point ‘O’
`is inserted with reference to the accompanying drawings.
`FIG. 6 is a functional block diagram of a 2N—point anc
`N-point FFT/IFFT dual mode processor according to another
`embodiment of the present invention. The ZN-point anc
`N-point FFT/IFFT dual mode processor includes the firs
`N-point FFT processor 310, a controller 320, a twiddle factor
`(TWF) multiplier 330, a MUX 340, and the second N-poin
`FFT processor 350.
`. x[Oj) 20:1, the firs
`.
`.
`After receiving N data (x[N—1j
`N-point processor 310 N-point FFT-operates on the N data
`and outputs the same.
`The controller 320 outputs a control signal ‘O’ in case of a
`ZN-point FFT operation and outputs a control signal ‘l ‘ in '
`case of a11 N-point FFT operation to the TWF 330, the MUX
`340, and the second N-point FFT processor 350.
`
`8
`Also, when receiving a control signal ‘O’ from the control-
`ler 320, the TWF 330 performs a twiddle multiplication
`operation on the N data (x[N—1] .
`.
`. x[0]) 20a.
`The MUX 340 passes results from the TWF 330 to the
`second N-point FFT processor 350 when receiving a control
`signal ‘O’ fonn the controller 320, and passes other N data
`(x[N—1]'
`.
`.
`. x[O]') 20b when receiving a control signal ‘1’
`from the controller 320.
`The second N-point FFT processor 350 N-point FFT-op-
`erates on outputs from the MUX 340 to output odd-numbered
`results from the second N-point FFT processor 350 when
`receiving a control signal ‘0’ from the controller 320, and
`N-point FFT-operates on outputs (x[N—l]' .
`.
`. x[O]') from the
`MUX 340 to output the same when receiving a control signal
`‘ 1 ’ from the controller 320.
`The operation of the 2N-point and N-point FFT/IFFT dual
`mode processor according to another embodiment of the
`present invention will be described below.
`FIG. 7 is a view illustrating an 8-point FFT operation where
`4-point ‘O’ is inserted into 4-point data. Compared with FIG.
`5, FIG. 7 illustrates the butterfly operation is omitted, which
`ca11 be proved by the following Equation 4. Since )([4], x[5],
`x[6], and X[7] are all ‘0’, the second term
`
`is cancelled and only the first term
`
`N'>r
`
`}’L’0
`Z x(n)W,’§"
`
`remains in Equation 4. When X(l<) is divided into X(2l<) and
`X(2l<+l ), two Equations become the same with coefficients in
`X(2k+l) excluded. Such a part is the same as that of the
`4-point FFT processor’s operation.
`
`.
`31if
`
`Equation 4
`
`5 3
`
`ll
`
`II
`
`1
`
`2L
`:H0 /Ԥ\5m
`~12‘=‘Zio4_ ii5 5.-
`
`fl
`
`ll N12
`
`X(2k +1; =
`
`x(n;w'ziv_;f2
`
`At this point, referring to FIG. 7, the processor for perform-
`ing an 8-point FFT operation where 4-point ‘O’ is inserted into
`
`ZTE/SAMSUNG/HTC 1030-0011
`
`

`
`US 7,693,924 B2
`
`9
`the 4-point data can be achieved through an operation 330 of
`multiplying two 4-point FFT processors 310 and 350 by the
`TWF. lnputs for the 4-point FFT processors 310 and 350
`share the san1e 4-point data 20a and 20b, and the results from
`the FFT processors 310 and 350 are divided into even-nnm-
`bcrcd tcrms 20c and odd-numbcrod terms 2001.
`FIG. 6 is a block diagram of a 2N—point and N—point FFT/’
`IFFT dual mode processor where N—point ‘0’ is inserted. The
`2N -point and N -point l~'F'l'/ll~'l~"l' dual mode processor ofFIG .
`6 allows the 2N-point FFT operation and the N—point FFT
`operation to be performed using the MUX 340.
`At this point. when a co11trol signal from the controller 320
`is ‘O’, Ndata 20a is inputted to the TWF multiplier 330, wl1ere
`the first multiplication operation is performed and results
`thereofare inputted to the second N—point FFT processor 350,
`which outputs odd-numbered results thereof.
`On the contrary, Wl1en a control signal from the controller
`320 is ‘ 1 ’, other N data 20b is inputted to the second N -point
`FFT processor 350, which pcrforms an N—point FFT opcra-
`tion.
`The inventive 2N-point and N—point FFT/IFFT dual mode
`processor allows the 2N-point FFT processor and the N—point
`FFT processor to operate in the dual mode in achieving the
`FFT/IFFT processor. Therefore, a system requiring opera-
`tions in two modes (i.e., a 2N—point FFT processor mode and
`an N—point FFT processor mode) can share a hardware in
`achieving the FFT processor, so that small sizing and low
`power consumption can be achieved. Also, the present inven-
`tion allows the N—point FFT operation to be perfomied two
`times simultaneously, thereby making system design easy as
`well as enhancing the performance of a receiver.
`It will be apparent to those skilled in the art that various
`modifications and variations can be made in the present
`invention. Thus. it is intended that the present invention cov-
`ers the modifications and variations ofthis invention provided
`they come within the scope of the appended claims and their
`cquivalcnts.
`What is claimed is:
`1. A 2N-point and N—point FFT (fast Fouricr transform)/’
`IFFT (inverse fast Fourier transform) dual mode processor
`comprising:
`a controller for outputting a corresponding control signal
`when an operation is a 2N-point Fl—"l' operation and
`outputting a corrcsponding control signal whcn an
`operation is an N—point FFT operation;
`. x[0].
`.
`a butterfly operator for receiving 2N data (x[N—l] .
`x[2N—l] .
`.
`. x[N]) to perform a butterlly operation when
`receiving a 2N-point FFT operation control signal from
`the controller;
`
`10
`first and second MUXS for receiving results from the but-
`terfly operator to output the received results in an incre-
`ment of N when receiving a 2N-point FFT operation
`control signal from the controller, and respectively
`receiving different N data (x[N—l]
`.
`.
`. x[0] and X
`[N—l]'
`.
`.
`. x[0]') to output thc samc whcn receiving an
`N—point FFT operation control signal from the control-
`ler;
`a first N -point FF'l' processor for N -point Fl~"l'-operating on
`outputs from the first MUX to output even-numbered
`results of the 2N—point FFT when receiving a 2N—point
`FFT operation control signal from the controller, and
`N-poi11t FFT-operating 011 outputs fron1 the first MUX to
`output the same when receiving a N—point FFT operation
`control signal from the controller; and
`a second N—point FFT processor for N—point FFT-operating
`on outputs fron1 the second MUX to output odd-num-
`bered results of the 2N-point l~'l~"l' when receiving a
`2N-point FFT opcration control signal from thc control-
`ler, and N—point FET—operating on outputs from the sec-
`ond MUX to output the same whe11 receiving a N—point
`FFT operatio11 control signal fron1tl1e co11troller.
`2. A 2N-point and N—point FFT (fast Fourier transform)/'
`IFFT (inverse fast Fourier transform) dual mode processor
`comprising:
`a first N—point FFT processor for receiving and N—point
`FFT-operating on N data (x[N—l] .
`.
`. x[O]) to output the
`operated data;
`a controller for outputting a corresponding control signal
`wl1en an operation is a 2N-point FFT operation and
`outputting a corresponding control signal when an
`operation is a N—point FFT operation;
`a TWF (twiddle factor) multiplier for receiving N data
`(x[N—l] .
`.
`. x[0]) to perform a twiddle multiplication
`operatio11 Wl1en receiving a 2N-point FET operation
`control signal from the controller;
`a MUX for passing results from thc TWF multiplicr whcn
`receiving a 2N—point FFT operation control signal from
`the controller and passing other N data (x[N—l]'
`.
`.
`.
`X[0j‘) when receiving an N—point l~'l~"l' operation control
`signal from thc controllcr; and
`a second N—point FFT processor for N—point FFT—operating
`on outputs from the MUX to output odd-numbered
`results ofthe 2N-point FFT processor when receiving a
`2N-point FFT operation control signal from the control-
`ler, and N—point FFT—operating on outputs (x[N—l]'
`.
`.
`.
`x[0]') from the MUX to output the same when receiving
`a N—point FFT operation control signal from tl1e control-
`ler.
`
`ZTE/SAMSUNG/HTC 1030-0012