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`TSMC Exhibit 1021
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`

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`AS/WE f’roce€<{’_‘_’j-5Q /1”/"‘l”*"—‘°°(i
`" mo\mJ.(q¢TJ,/if Co~-{swore oi/old, puoutséa/»‘
`Advanced Semiconductor
`Manufacturing conlerence and workshop
`
`5‘9m’(°"‘/“f-74°"
`
`IEEE/SEMI®
`
`1998
`
`IEEE/ SEMI
`
`Advanced
`
`Semiconductor
`
`Manufacturing
`Conference
`
`And Workshop
`
`
`
`The-me— Semiconductor Manufacturing: Meeting the Challenges of
`the Global Marketplace
`
`ASMC 98 PROCEEDINGS
`
`The IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop is an
`annual forum that provides a venue for the presentation of methodologies, approaches and
`techniques required to achieve world class semiconductor manufacturing.
`A key role this
`conference plays is in promoting interaction among semiconductor professionals at all levels. The
`goal and objective of the conference are to assist in making the participating companies more
`knowledgeable of semiconductor production methods, encourage open communication between
`participants, and develop the strategic relationship between users and suppliers needed to achieve
`manufacturing excellence and improve global competitiveness.
`
`September 23 -— 25, 1998
`Boston, Massachusetts, USA
`
`Page 2 of 18
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`Page 2 of 18
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`

`
`1993 PROCEEDINGS
`IEEE/SEMI ADVANCED SEMICONDUCTOR
`MANUFACTURING CONFERENCE AND
`WORKSHOP (ASMC) Egg‘? 8 7/
`
`PERMISSION TO REPRINT OR COPY:
`
`':l:Q5o.
`l 7 C7 8
`
`Abstracting is permitted with credit to the source. Libraries are permitted to photocopy
`beyond the limit of U.S. copyright law for private use of patrons those articles in this volume that
`carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid
`through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 09123 USA.
`Instructors are permitted to photocopy isolated articles for non-commercial classroom use without
`fee. For other copying, reprint or re-publication permission, write to IEEE Copyright Manager,
`IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08855 USA; or SEMI, 805 East Middlefield
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`
`Copyright © 1998 by Institute of Electrical & Electronics Engineering, Inc. (IEEE) and
`Semiconductor Equipment and Materials International, Inc. (SEMI)
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`PRINTED AND BOUND IN THE UNITED STATES OF AMERICA
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`Additional copies of these Proceedings may be purchased from:
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`In the US 1-800-678-IEEE
`httgpz//www.ieee.org
`
`Refer to the IEEE Catalog Number, printed below:
`
`IEEE Catalog Number;
`
`98CH35163
`
`ISBN Number:
`
`ISSN:
`
`0-7803-4380-8
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`0-7803-4382-4
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`
`Advanced Processing — Isolation and Dielectric Issue at 0.18pm
`
`A Manufacturable Shallow Trench Isolation Process for 0.18pm and Beyond-Optimization, Stress Reduction
`and Electrical Performance
`F. Nouri, O. Laparra. H. Sur, G.C. Tai, D. Pramanik and M. Manley, VLSI Technology, Inc.
`
`Performance and Productivity Improvements in an Advanced Dielectric Etch Reactor for sub 0.3um Applications
`M. Srinivasan, R. Caple. G. Hills, G. Mueller, T. Nguyen, and E. Wagganer, Lam Research Corp.
`
`A Study of Boron Doping Profile Control for a Low Vt Device Used in the Advanced Low Power, High Speed Mixed Signal IC
`Alec Chen. Kyle Flessner and Farris Malone, Peyman Sana, Robert Dixon, Peter Ying and Lou Hutter, Texas Instruments, Inc.
`
`Silicon Nanoelectronics: 100nm Barriers and Potential Solutions
`Vijay Parihar, R. Singh, K.F. Poole, Clemson University
`
`On the Integration of Ta,0, as a Gate Dielectric in sub-0.18pm, CMOS Processes
`T. Devoivre and C. Papadw, ST Microelectronics; M. Setton, LAM Research; N. Sandler, Formerly with LAM Research;
`L. Vallier, CNET Grenoble; l. Bouras, Integrated System Development
`
`Factory Modeling/Simulation
`
`Batch Size Optimization of a Furnace and Pre—Clean Area By Using Dynamic Simulations
`H..l.A. Rulkens, E.J.J. van Campen and J. van Herk, Philips Semiconductor,‘ .l.E. Rooda, Eindhoven University of Technology
`
`Simulation Analysis of 300mm lntrabay Automation Vehicle Capacity Alternatives
`Gerald T. Mackulak, Ph.D., Arizona State University; Frederick P. Lawrence and John Rayter, PR] Automation, Inc.
`
`Management of Multiple-Pass Constraints
`J. Bonal, A. Sadai, C. Ortega, S. Aparicio, M. Fernandez, R. Oliva, L. Rodriguez, M. Rosendo, A. Sanchez,
`E. Paule and D. Ojeda, Lucent Technologies
`
`MOSAIC I Product Transfer Using Virtual Flow Concept
`Ping Wang, Steve Spivey, Edward Warda, Mark Bowser, Bridgette Cosentino, Ed Zabasajja, Piyush Shah, Salma imam,
`John Keller and Joe Fulton, Motorola, Inc.
`
`Dynamic Dispatch and Graphical Monitoring System
`Neal Pierce and Tanju Yurtscvcr, Motorola, Inc.
`
`BIOGRAPHIES OF SPEAKERS
`
`SEMI Publications, Standards. Videos, Network
`
`413
`
`419
`
`423
`
`427
`
`434
`
`439
`
`445
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`451
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`455
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`464
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`469
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`IEEE/SEMI Advanced Semiconductor Manufacturing Conference & Workshop 98
`
`Boston, MA
`
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`

`
`
`
`
`
`
`
`
`(DE
`IIIIIIIII
`Slurry A
`EMMMMMMMIIHWIII
`
`Slurry C
`169
`
`
`
`IHE%w
`
`137:1
`207:1
`~ 3:1
`
`
`Table 1. Copper removal rate and selectivity to barrier films for various copper CMP slurries at a platen speed of
`43 rpm and a wafer pressure of 4.0 psi.
`
`As shown in Table I, either slurry A or B can be
`used in the single slurry process since they have
`a high copper removal rate. Slurry C is well
`suited for clearing barrier layers since the copper
`removal rate in this slurry is comparable to
`barrier removal rates. An ideal single step slurry
`would polish Cu and the barrier film at similar
`removal rates (low selectivity to ban'ier) and
`would also have a very low removal rate for the
`field
`oxide
`(high
`selectivity
`to
`Si02).
`Additionally, such an ideal slurry would remove
`
`residual Cu and barrier without dishing Cu
`interconnects and eroding the dielectric layer.
`
`The majority of the single slurry process
`discussed in the present work was carried out
`with slurry A. The dependence of the copper
`dishing and oxide
`erosion on the process
`parameters such as slurry flow rate, platen speed
`and wafer pressure was investigated with this
`slurry. In every case, end-point was detected with
`the ISRM system. All wafers were 10% over-
`polished after the end-point was detected. Figure
`1 shows a end-point trace of a blanket copper
`film containing Ta barrier film.
`
`
`
`RefledanceIntensitycm98§E
`
`
`
`Time (a)
`
`Figure 1.
`
`ISRM trace of a blanket copper film containing Ta barrier. End-point is shown by the dotted line.
`
`Page 11 of 18
`
`1998 IEEEISEMI Advanced Semiconductor Manufacturing confonnce
`
`Page 11 of 18
`
`

`
`andErosion
`NormalizedDishing
`
`
`so
`
`70
`
`7
`
`so‘
`
`13.0
`- no
`2150
`51"“? F1°W(ml/min)
`'
`'
`‘
`Figure 2. Dependence of copper dishing and oxide erosion on slurry (slurry A) flow rate. Platen speed and wafer
`pressure were held constant. Dishing was measured on a 50mm thick- line (pitch 15.0mm) while erosion was
`measured at a 0.5mm thick line (pitch 1.0mm).
`
`170
`
`190
`
`difiérent
`1,
`shown in Figure
`As
`interfaces of the film stock can be accurately
`detected with the end-point system. The amount
`of over-polish in a single slurry process
`is
`defined as the percent polish time afler the end-
`1 .
`
`point is reached. Figures 2-4 show the extent cf
`copper dishing observed in a 50pm copper line
`and extent of oxide erosion observed in a 0,5|.lm
`feature as process parameters such as slurry flow
`rate, wafer pressure and platen speed are varied.
`‘.-'3
`.
`-
`
`
`
`€03‘U
`
`505
`
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`'2
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`2‘
`-2o--so-'
`~
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`.. vv .
`‘"7 _‘ i.
`_w 390'
`40‘
`to
`-Plntenufipeedirpm)
`‘
`
`7
`
`’_
`
`t
`
`90
`
`Imp‘
`e'“‘
`
`L,
`
`'shjng 'd ‘xid "’ei‘o '
`laten s
`§i¢§.;Iuere3.wfipicle‘:n:J1i)stizi:|f)tI:pe‘li)‘i;hmgV §vnasomea:meE“:i1o:g0um
`
`measured at 0.5mm line,.(pitch 1.0mm)-
`
`(slurry A). Slurry flow rate and wafer
`(pitch 150mm) while erosion was
`
`€='\
`
`:im-.'‘' so‘.
`
`.1»-1.:».tlhr~-3 '-~.-- fir tl.;‘..~‘uT:‘. “ "":<‘
`
`Page 12 of 18
`
`qgulsgasmnmusmkamuehrflultliwmmcummlfl
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`

`
`3 4
`
`0
`
`1
`
`2
`
`5
`
`6 r
`
`7
`
`8
`
`R
`
`
`
`2NormalizedDishingandErosion B
`
`o
`
`Waferhesoure (poi)
`Figure 4. Dependence of copper dishing oxide erosion on wafer pressure (slurry A). Platcn speed and slurry
`flow rate were held constant. Dishing
`was measured on 50mm feature (pitch .150mm) while erosion was measured
`at 0.5mm line ‘(pitch 1.0mm).
`
`Data in Figure 2 show that copper dishing
`is somewhat higher at high slurry flow rates.
`This may be caused by continued chemical
`etching of copper. Also, the copper dishing is
`relatively high at higher platen speeds and higher
`
`wafier pressures. Both the oxide erosion and
`copper dishing appear to linearly increase with
`platen speed as well as
`the wafer pressure
`(Figures 3 and 4).
`
`a "A
`---A-.--SlunyB
`-—-O_%_S_lunyA
`---I-- SlurryB
`
`'
`
` 9 \
`
`5
`
`5
`
`To
`
`I-ineWidth_(u).
`2
`
`'
`
`_w
`
`Figure 5. Comparison of copper dishing and oxide erosion of single slurry process under identical experimental
`conditions (slurry A and slurry B). Copper dishing on slurry B is relatively smaller compared to that of slurry A.
`Both slurries have similar oxide erosion perfonnance.
`
`an ~
`
`.
`
`Page 13 of 18
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`

`
`
`
`5 S
`
`EE
`
`MID
`
`(Normalized)
`AmountEtched
`
`
`0
`
`p
`
`Q
`
`11)
`
`1” ,
`
`113318)
`
`II)
`
`Figure 6. Static copper etch rate at room temperature (slurry. A and Slurry B).
`
`In order to improvethe dishing in‘ a.
`single slurry process, another slurry formulation
`(slurry B) was evaluated.
`5 the
`extent of dishing and erosion observed, with
`single slurry processes (slur’ry——A,,and slurry»-B).
`under identical polishing cendifions.
`.It is seen
`that dishing and erosion
`'of's‘_lurry “B
`is somewhat improved "as to sliii3){~A.,_*’.
`Improved dishing in- s4lurry‘Bnfayberel;tiéd5to=a’ ~.
`.:(Fi‘“‘%5)" i*“,“°fi
`low static etchmte<ofslurry=ZB
`
`.4< ,
`
`.'
`
`r etch rate cf
`shown in Figure 6, static co
`that ofslurry
`‘.7 ~.s1ufryAis.considerably'hi_gl1er’
`Therefore, slurry B reduces static etching
`the barrier ‘removal and over-polish,
`'leadirig»_to lower copper dishing“ levels. _Because
`_
`_
`_
`_
`.j0ftI_1e<impr:oved dishing performance of_3slun-y B
`(comparedto slurry A), slurry B ‘was selected as
`— _fl1e first step slurry for the tvvoaislurry process
`,
`
`,
`
`._.
`
`g
`
`
`
`Ep 4- :1
`
`E21’ + :2
`
`Polish Time (3)
`
`d ad for one slurry (slurry A) process and two slurry
`b
`f 100
`‘
`'
`mung ° m “I P
`yh end-point and :1, :2, :3
`Figure 7. Comparison of copper
`In the case of one slurry process, EP is the time to re
`t2,_ and B are the over polish times with slurry
`(slurry B and slurry C) processes.
`are the over polish times.
`In the case of the two slurry process, tl,
`C.
`
`.a‘I
`
`_-v-
`
`‘e.
`
`V. M! ..—
`
`:3:
`
`" v" ‘W
`‘P
`
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`

`
`Loss
`NormalizedTotalCopper
`
`
`25].!
`
`35p
`
`751.1
`
`Line Width
`
`Figure 11. Comparison of total copper loss (dishing + erosion) for one slurry (slurry A) and two slurry (slurry B
`+ slurry C) processes in a variety of copper line sizes.
`
`the two slun'y process
`As seen in Figure 11,
`significantly reduces the amount of total copper
`loss
`(dishing + erosion)
`in
`copper
`lines
`compared to the single slurry process. The data
`presented in Figure 11 were derived from the
`
`resolution
`measurements made with a high
`profilometer. These data are in good agreement
`with the electrically measured copper thickness
`for single and two slurry processes (Figure 12)
`measured with a short loop test pattern.
`
`33
`
`E l
`
`0n
`
`_E_ new
`.
`n.
`
` ,, 0&1]
`
`(1400
`
`eU E
`
`2 0.200
`
`(mm
`
`Slurry A, 20%
`overpolish
`
`Slurry A, End-
`pointed
`
`Slurry B + C, End.
`pointed
`
`Figure 12. Comparison of electrically measured copper thickness for one slurry (slurry A) and two slurry (slurry
`B + slurry C) processes. Measurements were performed on a 10 m xl0m Van der Pauw structure.
`
`The data displayed in Figure 12 were measured
`on l0uxl0u Van der Pauw structures.
`As
`expected,
`the wafers processed with slurry A
`show heavy copper loss in the line structures.
`It
`can be seen that about 40% of additional copper
`is lost by performing 20% over-polish after end-
`point detection. However,
`in the case of two
`slurry process, only 10% copper is
`lost when
`polishing was stopped at end-point.
`
`ll
`
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`362
`
`1998 IEEEISEMI Advanced semiconductor Manufacturing Conference
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