1109905
`
`I,
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`of
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`VERIFICATION OF TRANSLATION
`
`Masako Taylor
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`1950 Roland Clarke Place
`Reston, VA 20191
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`declare that I am well acquainted with both the Japanese and English languages, and that
`the attached is an accurate translation, to the best of my knowledge and ability, of
`Japanese Unexamined Patent Application Publication No. Hl1-67686, published March
`9,7ggg.
`
`I further declare that all statements made herein of my own knowledge are true and that
`all statements made on information and belief are believed to be true; and further that
`these statements were made with the knowledge that willful false statements and the like
`so made are punishable by fine or imprisonment, or both, under Section 1001 of Title l8
`of the United States Code and that such willful false statements may jeopardize the
`validity of the above-captioned application or any patent issued thereon.
`
`3/ - / r-ot7
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`Date
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`Masako Taylor
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`{17 0990s 03037466.DOC}
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`Page 1 of 20
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`IP Bridge Exhibit 2031
`TSMC v. IP Bridge
`IPR2016-01249
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`IP Bridge Exhibit 2031
`TSMC v. IP Bridge
`IPR2016-01264
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`

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`(19) Japan Patent Office (JP)
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` (12) Patent Publication (A)
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`(11) Patent Publication No.
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`JP H11-67686
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`(14) Publication Date: March 09, 1999
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`(51) Intl. Cl.6
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`Identification Symbol.
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`H01L
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`21/28
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`21/3205
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`21/768
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`FI
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`H01L 21/28
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`21/88
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`21/90
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`301T
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`301R
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`Request for Examination Not Requested No. of Claims: 9
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`OL (8 pages total)
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`(21) Application No. Application H09-219564
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`(71) Applicant
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`000000295
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`(22) Application Date August 14, 1997
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`Oki Electric Industry Co., Ltd.
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`1-7-12 Toranomon,
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`Minato-ku, Tokyo
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`(72) Inventor
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`Kaori Tai
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`c/o Oki Electric Industry Co., Ltd.
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`1-7-12 Toranomon,
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`Minato-ku, Tokyo
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`(74) Representative Patent Agent Masayuki Koiwai
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`(and two others )
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`(54) [Title of Invention]
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`MANUFACTURING METHOD OF
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`SEMICONDUCTOR ELEMENT
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`(57) [Abstract]
`
`[Purpose] To provide a method capable of
`
`manufacturing a semiconductor element
`
`having an adhesive layer which does not
`
`increase a contact resistance and damage a
`
`diffusion layer at low cost in a short time
`
`even when a high-temperature heat
`
`treatment is performed.
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`[Solution] A titanium nitride layer
`
`constituting an adhesive layer is structured
`
`in a multilayer having a first titanium
`
`nitride layer 104 to a third titanium nitride
`
`layer 106, and by making a second
`
`deposition condition which is used to form
`
`a second titanium nitride layer 105 different
`
`from a first deposition condition used to
`
`form the first titanium nitride layer 104 and
`
`the third titanium nitride layer 106, grains
`
`of the second titanium nitride layer 105 are
`
`formed smaller than the grains of the first
`
`(and the third) titanium nitride layer 104.
`
`According to the manufacturing method,
`
`the titanium nitride layer with the grains
`
`discontinuously formed is deposited by
`
`simply changing the deposition condition
`
`temporarily. Therefore, the semiconductor
`
`element having above-noted characteristics
`
`can be manufactured at low cost in a short
`
`time.
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`{J709905 03023408.DOC}
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`[Scope of the Claims]
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`[Claim 1] A manufacturing method of a semiconductor element comprising: a titanium layer
`
`formation process forming a titanium layer having a portion of a diffusion layer contacting a
`
`semiconductor element substrate with an opened contact hole turns into silicide; a first titanium
`
`nitride layer formation process forming a first titanium nitride layer by a chemical vapor
`
`deposition method using a first deposition condition on the titanium layer formed by the titanium
`
`layer formation process; a second titanium nitride layer formation process forming a second
`
`titanium nitride layer having smaller grains than the first titanium nitride layer by the chemical
`
`vapor deposition method using the first deposition condition different from the first deposition
`
`condition on the first titanium nitride layer formed by the first titanium nitride layer formation
`
`process; a third titanium nitride layer formation process forming a third titanium nitride layer by
`
`the chemical vapor deposition method using the first deposition condition on the second titanium
`
`nitride layer formed by the second titanium nitride layer formation process; and a wire metal
`
`layer formation process forming a metal layer for a wire on the third titanium nitride layer
`
`formed by the third titanium nitride layer formation process.
`
`[Claim 2] The manufacturing method of the semiconductor element according to claim 1,
`
`wherein the first to the third titanium nitride film formation processes are the process forming the
`
`titanium nitride film by the chemical vapor deposition method used together with TiCl4, NH3,
`
`and N2 gas, and the second deposition condition is the same with the first deposition condition
`
`except for the TiCl4 gas flow, and the TiCl4 gas flow is less than the flow under the first
`
`deposition condition.
`
`[Claim 3] A manufacturing method of a semiconductor element comprising: a titanium layer
`
`formation process forming a titanium layer having a portion of a diffusion layer contacting a
`
`semiconductor element substrate with an opened contact hole turns into silicide; a first titanium
`
`nitride layer formation process forming a first titanium nitride layer by a chemical vapor
`
`deposition method using a first deposition condition on the titanium layer formed by the titanium
`
`layer formation process; a reformation process reforming a surface layer of the first titanium
`
`nitride film by performing a plasma treatment on the first titanium nitride layer formed by the
`
`first titanium nitride layer formation process; a second titanium nitride layer formation process
`
`forming a second titanium nitride layer by the chemical vapor deposition method using the first
`
`deposition condition on the first titanium nitride layer with the reformed surface layer using the
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`{J709905 03023408.DOC}
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`reformation process; and a wire metal layer formation process forming a metal layer for a wire
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`on the second titanium nitride layer formed by the second titanium nitride layer formation
`
`process.
`
`[Claim 4] The manufacturing method of the semiconductor element according to one of claims 3
`
`and 4, wherein the first titanium nitride layer formation process, the reformation process, and the
`
`second titanium nitride layer formation process are performed continuously in the same chamber.
`
`[Claim 5] The manufacturing method of the semiconductor element according to one of claims 3
`
`and 4, wherein the reformation process reforms the surface layer of the first titanium nitride
`
`layer using argon plasma.
`
`[Claim 6] The manufacturing method of the semiconductor element according to one of claims 3
`
`and 4, wherein the reformation process reforms the surface layer of the first titanium nitride layer
`
`using gas plasma containing nitrogen.
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`[Claim 7] The manufacturing method of the semiconductor element according to one of claims 3
`
`and 4, wherein the reformation process reforms the surface layer of the first titanium nitride layer
`
`using gas plasma containing oxygen.
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`[Claim 8] The manufacturing method of the semiconductor element according to claim 7,
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`comprising a second oxidation process reforming a surface layer of the second titanium nitride
`
`layer using plasma containing oxygen between the second titanium nitride layer formation
`
`process and the wire metal layer formation process.
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`[Claim 9] The manufacturing method of the semiconductor element according to any one of
`
`claims 1 to 8, wherein the wire metal layer formation process forms the metal layer composed of
`
`tungsten using the chemical vapor deposition method.
`
`[Detailed Description of the Invention]
`
`[0001]
`
`[Field of the invention] The present invention relates to a manufacturing method of a
`
`semiconductor element, and particularly relates to a manufacturing method of a semiconductor
`
`element using a CVD (Chemical Vapor Deposition) method to form a wire (such as a bit line).
`
`[0002]
`
`[Conventional technology] Currently, although polysilicon is widely used to form a bit line,
`
`when the bit line is formed using tungsten (W), contact resistance and wiring resistance are
`
`reduced. Therefore, the semiconductor element which operates at high speed can be
`
`{J709905 03023408.DOC}
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`manufactured. In addition, by using W, it becomes possible to connect an N type doped region
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`and a P type doped region, so forming the bit line using W is gathering attention.
`
`[0003] When the bit line is formed using W, the CVD method is used because a contact hole
`
`needs to be filled with W. However, W has a poor adhesion with an oxide film, and therefore
`
`when the bit line is formed using W, an adhesive layer is first formed and then W is deposited.
`
`[0004] As a formation method of the adhesive layer, a known example is to form a Ti (titanium)
`
`film and a TiN (titanium nitride) film by a sputtering method and then to heat with a lamp in N2
`
`and NH3 atmosphere. In addition, with recent advance of microminiaturization, an aspect ratio
`
`of the contact hole tends to increase. Therefore, by using the CVD method, a technique in which
`
`the adhesive layer made of the Ti film and TiN film with good coverage being formed inside the
`
`contact hole with the large aspect ratio is also developed.
`
`[0005] When manufacturing the semiconductor element, there is a case where a heat treatment
`
`with a temperature of about 800°C is required in order to form a capacitor or the like after
`
`forming the wire. When such a high-temperature heat treatment is performed, a wire metal may
`
`be diffused toward Si or Si may be diffused toward the wire metal in the adhesive layer, and
`
`therefore causing phenomena such as increasing the contact resistance and damaging the
`
`diffusion layer.
`
`[0006] In order to prevent such phenomena from occurring, the Patent Journal No. 2541657
`
`discloses the following technology. In the technology, the TiN layer having about 50 nm
`
`thickness is deposited by a reactive sputtering on a structure where the Ti layer is formed. Next,
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`an interface layer is formed by oxidation of a surface layer of the TiN layer, and the TiN layer
`
`having about 50 nm thickness is deposited on the interface layer by the reactive sputtering.
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`Then, the wire metal (Al) is deposited on the adhesive layer having a grain boundary
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`discontinuous in the interface layer which is formed in this procedure.
`
`[0007]
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`[Problems to be solved by the invention] The adhesive layer formed by the technology described
`
`in the above-noted Patent Journal does not have the continuous grain boundary, and thus the
`
`diffusion along the grain boundary is unlikely to occur. In other words, the semiconductor
`
`element having the adhesive layer formed in the above-noted procedure is unlikely to increase
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`the contact resistance and to damage the diffusion layer even when the high-temperature
`
`treatment is performed.
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`{J709905 03023408.DOC}
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`[0008] However, in the technology described in the above-noted Patent Journal, the interface
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`layer was formed by performing the heat treatment, while passing nitrogen gas, on a sample
`
`which forms the TiN layer inside a reaction tube configured such that a small amount of oxygen
`
`can enter. Therefore, the adhesive layer formation required too much time.
`
`[0009] The present invention provides a method capable of manufacturing the semiconductor
`
`element which is unlikely to increase the contact resistance and damage the diffusion layer at
`
`low cost in a short time even when the high-temperature heat treatment is performed, and the
`
`method capable of manufacturing the semiconductor element having a fine contact hole.
`
`[0010]
`
`[Means for solving the problems] In a manufacturing method of a first semiconductor element
`
`according to the present invention, the following processes are used: (A) a titanium layer
`
`formation process forming a titanium layer having a portion of a diffusion layer contacting a
`
`semiconductor element substrate with an opened contact hole turns into silicide; (B) a first
`
`titanium nitride layer formation process forming a first titanium nitride layer by a chemical vapor
`
`deposition method using a first deposition condition on the titanium layer formed by the titanium
`
`layer formation process; (C) a second titanium nitride layer formation process forming a second
`
`titanium nitride layer having smaller grains than the first titanium nitride layer by the chemical
`
`vapor deposition method using a second deposition condition different from the first deposition
`
`condition on the first titanium nitride layer formed by the first titanium nitride layer formation
`
`process; (D) a third titanium nitride layer formation process forming a third titanium nitride layer
`
`by the chemical vapor deposition method using the first deposition condition on the second
`
`titanium nitride layer formed by the second titanium nitride layer formation process; and (E) a
`
`wire metal layer formation process forming a metal layer for a wire on the third titanium nitride
`
`layer formed by the third titanium nitride layer formation process.
`
`[0011] In other words, in the manufacturing method of the first semiconductor element, the
`
`titanium nitride layer constituting the adhesive layer is structured in a multilayer having the first
`
`to the third titanium nitride layer, and the grains of the second titanium nitride layer are smaller
`
`than the grains of the first (and the third) titanium nitride layer by making the second deposition
`
`condition used to form the second titanium nitride layer different from the first deposition
`
`condition used to form the first and third titanium nitride layers. According to the manufacturing
`
`method, the titanium nitride layer with grains continuously formed can be formed by simply
`
`{J709905 03023408.DOC}
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`changing the deposition condition temporarily. Therefore, the semiconductor element having the
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`adhesive layer which does not increase the contact resistance and damage the diffusion layer can
`
`be manufactured at low cost in a short time even when the high-temperature heat treatment is
`
`performed.
`
`[0012] Further, when the first to the third titanium nitride film formation processes are the
`
`process forming the titanium nitride film by the chemical vapor deposition method used together
`
`with TiCl4, NH3, and N2 gas, for example, the condition is the same with the first deposition
`
`condition except for the TiCl4 gas flow. When using the second deposition condition with less
`
`flow than the TiCl4 gas flow of the first deposition condition, the grains of the second titanium
`
`nitride layer can be smaller than the grains of the first (and the third) titanium nitride layer.
`
`[0013] In a manufacturing method of a second semiconductor element according to the present
`
`invention, the following processes are used: (A) a titanium layer formation process forming a
`
`titanium layer having a portion of a diffusion layer contacting a semiconductor element substrate
`
`with an opened contact hole turns into silicide; (B) a first titanium nitride layer formation process
`
`forming a first titanium nitride layer by a chemical vapor deposition method using the first
`
`deposition condition on the titanium layer formed by the titanium layer formation process; (C) a
`
`reformation process reforming a surface layer of the first titanium nitride film by performing a
`
`plasma treatment on the first titanium nitride layer formed by the first titanium nitride layer
`
`formation process; (D) a second titanium nitride layer formation process forming a second
`
`titanium nitride layer by the chemical vapor deposition method using the first deposition
`
`condition on the first titanium nitride layer with the reformed surface layer using the reformation
`
`process; and (E) a wire metal layer formation process forming a metal layer for a wire on the
`
`second titanium nitride layer formed by the second titanium nitride layer formation process.
`
`[0014] In other words, in the manufacturing method of the second semiconductor element, when
`
`forming the titanium nitride layer constituting the adhesive layer, the first titanium nitride layer
`
`is formed and then the surface layer of the first titanium nitride layer is reformed by the
`
`treatment using plasma. The adhesive layer is completed by forming the second titanium nitride
`
`layer on the first titanium nitride layer having the surface layer reformed. According to the
`
`manufacturing method, because it only requires a short time to perform the reformation process,
`
`the titanium nitride layer with grains discontinuously formed can be formed in a short time.
`
`Therefore, according to the manufacturing method, even when the high-temperature heat
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`{J709905 03023408.DOC}
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`treatment is performed, the semiconductor element having the adhesive layer which does not
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`increase the contact resistance and damage the diffusion layer can be manufactured at low cost in
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`a short time.
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`[0015] In addition, when the first titanium nitride layer formation process, the reformation
`
`process, and the second titanium nitride layer formation process are performed continuously in
`
`the same chamber, the semiconductor element having the adhesive layer with the above
`
`characteristics can be manufactured at low cost in a short time.
`
`[0016] Further, in the manufacturing method of the second semiconductor element, a process
`
`reforming the surface layer of the first titanium nitride layer using argon plasma, the process
`
`reforming the surface layer of the first titanium nitride layer using gas plasma containing
`
`nitrogen, and the process reforming the surface layer of the first titanium nitride layer using gas
`
`plasma containing oxygen can be employed as the reformation process. When employing the
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`reformation process using gas plasma containing oxygen, a layer containing oxygen exists
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`between the first titanium nitride layer and the second titanium nitride layer. Accordingly, the
`
`diffusion of the wire metal is suppressed by oxygen, and therefore the semiconductor element
`
`having the adhesive layer, which is unlikely to increase the contact resistance and damage the
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`diffusion layer due to the high-temperature heat treatment, can be manufactured.
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`[0017] In addition, the wire metal layer formation process may be formed by a metal layer made
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`of any material in any method, however, from a point of a practical view, preferably, a process in
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`which the metal layer of tungsten is formed using the chemical vapor deposition method.
`
`[0018]
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`[Embodiments of the invention] Hereafter, embodiments of the present invention are described
`
`in detail with reference to the drawings.
`
`(Embodiment 1) In a first embodiment, as shown in Fig. 1(a), on a substrate 101 with the contact
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`hole being opened for conducting the diffusion layer, a Ti layer 102 is formed by the CVD
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`method at first. By forming the Ti layer 102, at a bottom of the contact hole (a boundary
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`between the Ti layer and the diffusion layer), Ti which is a component of the Ti layer 102 reacts
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`with Si which is the component of the diffusion layer, and as shown in the drawing, a TiSi2 layer
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`103 is formed.
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`[0019] After that, as shown in Fig. 1(b), three TiN layers are formed on the Ti layer 102 and
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`TiSi2 layer 103. Specifically, first of all, by the CVD method used with the TiCl4, NH3, and N2
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`{J709905 03023408.DOC}
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`gas, a TiN layer 104 having 5 to 30 nm thickness is formed under the first deposition condition
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`noted below.
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`[0020] The first deposition condition
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`Film deposition temperature: 630°C, Deposition pressure: 20 torr, TiCl4 flow: 40 sccm, NH3
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`flow: 60 sccm, N2 flow: 3000 sccm
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`Next, by the CVD method used with TiCl4, NH3, and N2 gas, a TiN layer 105 having 2 to 5 nm
`
`thickness is formed. However, at this time, a second deposition condition which differs from the
`
`condition used to form the TiN layer 104 is used.
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`[0021] The second deposition condition
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`Film deposition temperature: 630°C, Deposition pressure: 20 torr, TiCl4 flow: 4 sccm, NH3 flow:
`
`60 sccm, N2 flow: 3000 sccm
`
`In other words, the TiN layer 105 is the same condition with the first deposition condition except
`
`for the TiCl4 gas flow and is formed in the second deposition condition with the TiCl4 gas flow
`
`less than the flow of the first deposition condition.
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`[0022] Then, under the same condition when the TiN layer 104 is formed (namely, the first
`
`deposition condition), a CVD-TiN layer 106 having 5 to 30 nm thickness is formed. After the
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`TiN layers 104 to 106 are formed by this procedure, as shown in Fig. 1(c), a W layer 107 is
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`formed by the CVD method. Then, by performing photolitho and etching, a W wire is formed.
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`[0023] When the semiconductor element (wire) is formed with the above-noted procedure, the
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`TiN layer 105 has finer grains compared to the TiN layers 104 and 106. As the result, grains of
`
`the TiN layer 106 are discontinuous with the grains of the TiN layer 104. In other words, the
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`portion composed of the TiN layers 104 to 106 includes a structure where W or Si hardly
`
`diffuses inside. Therefore, the semiconductor element having the adhesive layer formed in the
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`above-noted procedure unlikely to increase the contact resistance or damage the diffusion layer
`
`even after the high-temperature heat treatment is performed in order to form the capacitor and
`
`the like.
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`[0024] Further, in the first embodiment, by setting the TiCl4 gas flow during the TiN layer 105
`
`formation different from the flow during the TiN layers 104 and 106 formation, the TiN layer
`
`105 having finer grains is formed compared to the Tin layers 104 and 106. However, such TiN
`
`layer 105 may be formed by changing other conditions such as the deposition pressure, NH3 gas
`
`flow, N2 gas flow or the like for example. In addition, the deposition condition of the TiN layers
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`{J709905 03023408.DOC}
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`104 and 106 can be different from the first deposition condition noted above. However,
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`according to the first embodiment, the condition revised during the TiN layers 104 to 106
`
`formation is only the TiCl4 gas flow, and therefore the semiconductor element can be formed
`
`without complicating the manufacturing process.
`
`[0025] In addition, in the first embodiment, the TiN layers are formed in three layers. However,
`
`the number of the TiN layers may be increased by further adding a deposition process using the
`
`second deposition condition and the deposition process using the first deposition condition.
`
`Furthermore, materials other than W can also be used as the wire metal.
`
`[0026] (Embodiment 2) In a second embodiment, argon plasma is used in order to form the
`
`adhesive layer having discontinuous grains.
`
`[0027] Specifically, as shown in Fig. 2(a), on a substrate 201 with the contact hole being opened
`
`for conducting the diffusion layer, a Ti layer 202 (and TiSi2 layer 203) and a TiN layer 204 are
`
`formed. Further, the formation procedure (deposition method, condition, and film thickness) of
`
`the Ti layer 202 and TiN layer 204 is the same with the first embodiment which was used to
`
`from the Ti layer 102 and TiN layer 104. Therefore, the TiS2 layer 203 is formed at the bottom
`
`of the contact hole.
`
`[0028] After that, as schematically shown in Fig. 2(b), a thin amorphous TiN layer 205 (about a
`
`few nm thickness) is formed on a surface layer of the TiN layer 204 by building argon plasma
`
`inside the chamber where the TiN layer 204 is formed and by firing argon ions (Ar+) on the
`
`surface layer of the TiN layer 204. Further, in this embodiment, the process is performed with
`
`the film deposition temperature at 630°C, deposition pressure at 1 torr, and Ar flow at 3000
`
`sccm, however, the condition for the process may be anything as long as the TiN layer 204 can
`
`be turned into amorphous.
`
`[0029] Then, under the same condition when the TiN layer 204 is formed (namely, the first
`
`deposition condition described in the first embodiment), a structure shown in Fig. 2(c) is
`
`obtained by forming a W layer 207 using the CVD method after the TiN layer 206 having 5 to 30
`
`nm thickness being formed. Then, by performing photolitho and etching, the W wire is formed.
`
`[0030] When the semiconductor element (wire) is formed in the above-noted procedure, the
`
`grains of the TiN layer 206 are discontinuous with the grains of the TiN layer 204 since the TiN
`
`layer 206 is deposited on the TiN layer 205 in amorphous state. In other words, the portion
`
`composed of the TiN layer 204, the amorphous-TiN layer 205, and the TiN layer 206 includes
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`the structure where W or Si hardly diffuses inside. Accordingly, the semiconductor element
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`having the adhesive layer formed in the above-noted procedure unlikely to increase the contact
`
`resistance and damage the diffusion layer even after the high-temperature heat treatment is
`
`performed in order to form the capacitor and the like. By using the procedure, the adhesive layer
`
`can be formed in the continuous process inside the identical chamber, and therefore the
`
`semiconductor element having the adhesive layer, which does not increase the contact resistance
`
`and damage the diffusion layer, can be manufactured at low cost in a short time even when the
`
`high-temperature heat treatment is performed.
`
`[0031] (Embodiment 3) In a third embodiment, NH3 plasma is used in order to form the adhesive
`
`layer having the discontinuous grains.
`
`[0032] Specifically, as shown in Fig. 3(a), on a substrate 301 with the contact hole being opened
`
`for conducting the diffusion layer, a Ti layer 302 (and TiSi2 layer 303) and a TiN layer 304 are
`
`formed. Further, the formation procedure (deposition method, condition, and film thickness) of
`
`the Ti layer 302 and TiN layer 304 is the same with the first embodiment which was used to
`
`from the Ti layer 102 and TiN layer 104.
`
`[0033] Then, as schematically shown in Fig. 3(b), by building NH3 plasma inside the chamber
`
`where the TiN layer 304 is formed, a surface layer of the TiN layer 304 is reformed into a nitride
`
`TiN layer 305 which is a TiN layer containing more N. Further, in this embodiment, the process
`
`is performed with the film deposition temperature at 630°C, deposition pressure at 5 torr, and
`
`NH3 flow at 500 sccm, however, the condition for the process may be anything as long as a
`
`microstructure of the surface layer of the TiN layer 304 can be changed.
`
`[0034]
`
`Then, under the same condition when the TiN layer 304 is formed (namely, the first deposition
`
`condition described in the first embodiment), a structure shown in Fig. 3(c) is obtained by
`
`forming a W layer 307 using the CVD method after the TiN layer having 5 to 30 nm thickness
`
`being formed. Then, by performing photolitho and etching, the W wire is formed.
`
`[0035] When the semiconductor element (wire) is formed in the above-noted procedure, the
`
`grains of the TiN layer 306 are discontinuous with the grains of the TiN layer 304 since the TiN
`
`layer 306 is deposited on the nitride TiN layer 305 having a different surface condition from the
`
`TiN layer 304. In other words, the portion composed of the TiN layer 304, nitride TiN layer 305,
`
`and TiN layer 306 includes the structure where W or Si hardly diffuses inside. Accordingly, the
`
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`semiconductor element having the adhesive layer formed in the above-noted procedure unlikely
`
`to increase the contact resistance and damage the diffusion layer even after the high-temperature
`
`heat treatment is performed in order to form the capacitor and the like. By using the procedure,
`
`the adhesive layer can be formed in the continuous process inside the identical chamber, and
`
`therefore the semiconductor element having the adhesive layer, which does not increase the
`
`contact resistance and damage the diffusion layer, can be manufactured at low cost in a short
`
`time even when the high-temperature heat treatment is performed
`
`[0036] (Embodiment 4) In a fourth embodiment, O2 plasma is used in order to form the adhesive
`
`layer having discontinuous grains.
`
`[0037] Specifically, as shown in Fig. 4(a), on a substrate 401 with the contact hole being opened
`
`for conducting the diffusion layer, a Ti layer 402 (and TiSi2 layer 403) and a TiN layer 404 are
`
`formed in the same procedure used to form the Ti layer 102 and TiN layer 104 in the first
`
`embodiment respectively.
`
`[0038] Then, as schematically shown in Fig. 4(b), by building O2 plasma inside the chamber
`
`where the TiN layer 404 is formed, a surface layer of the TiN layer 404 is oxidized and a thin Ti-
`
`O-N layer 405 (about a few nm thickness) composed of titanium, oxygen, and nitride is formed.
`
`Further, in this embodiment, the process is performed with the film deposition temperature at
`
`630°C, deposition pressure at 5 torr, and O2 flow at 500 sccm, however, the condition for this
`
`process may be anything as long as the surface layer of the TiN layer 404 can be changed to a Ti-
`
`O-N layer by oxidation.
`
`[0039] Then, under the same condition when the TiN layer 404 is formed (namely, the first
`
`deposition condition described in the first embodiment), the TiN layer 406 having 5 to 30 nm
`
`thickness is formed, and further by performing a plasma oxidation on the surface layer, under the
`
`same condition when the Ti-O-N layer 405 is formed, a Ti-O-N layer 407 is formed. After that,
`
`a structure as shown in Fig. 4(c) is obtained by forming a W layer 408 using the CVD method.
`
`Then, by performing photolitho and etching, the W wire is formed
`
`[0040] When the semiconductor element (wire) is formed in the above-noted procedure, the
`
`grains of the TiN layer 406 are discontinuous with the grains of the TiN layer 404 since the TiN
`
`layer 406 is deposited on the Ti-O-N layer 405 having the different surface condition from the
`
`TiN layer 404. In other words, the portion composed of the TiN layer 404, Ti-O-N layer 405,
`
`TiN layer 406, and Ti-O-N layer 407 includes the structure where W or Si hardly diffuses inside.
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`Accordingly, the semiconductor element having the adhesive layer formed in the above-noted
`
`procedure unlikely to increase the contact resistance and damage the diffusion layer even after
`
`the high-temperature heat treatment is performed in order to form the capacitor and the like.
`
`[0041] In addition, the semiconductor element formed in the procedure includes a layer
`
`containing oxygen such as the Ti-O-N layer 405 and Ti-O-N layer 407 between W and the
`
`substrate (Si). Accordingly, the diffusion of W (or Si) is suppressed by oxygen, and therefore,
`
`with the present manufacturing method, the semiconductor element, which is unlikely to increase
`
`the contact resistance and damage the diffusion layer due to the high-temperature heat treatment,
`
`can be manufactured compared to the manufacturing procedures described in the first to the third
`
`embodiments. By using the present procedure, the adhesive layer can be formed in the
`
`continuous process inside the identical chamber, and therefore the semiconductor element having
`
`the adhesive layer, does not increase the contact resistance and damage the diffusion layer, can
`
`be manufactured at low cost in a short time even when the high-temperature heat treatment is
`
`performed.
`
`[0042]
`
`[Effects of the invention] As described above, according to the present invention, the
`
`semiconductor element having the adhesive layer, which does not increase the contact resistance
`
`and damage the diffusion layer, can be manufactured at low cost in a short time even when the
`
`high temperature heat treatment is performed.
`
`[Brief Description of Drawings]
`
`[Fig. 1] is a process chart illustrating a first embodiment according to the present invention.
`
`[Fig. 2] is a process chart illustrating a second embodiment according to the present invention.
`
`[Fig. 3] is a process chart illustrating a third embo