J70990s
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`I,
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`of
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`VERIFICATION OF TRANSLATION
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`Karen McGillicuddy
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`6144 Brook Drive
`Falls Church, VA 22044
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`declare that I am well acquainted with both the Japanese and English languages, and that
`the attached is an accurate translation, to the best of my knowledge and ability, of
`Japanese Unexamined Patent Application Publication No. H08-139092, published May
`31, t996.
`
`I further declare that all statements made herein of my own knowledge are true and that
`all statements made on information and belief are believed to be true; and further that
`these statements were made with the knowledge that willful false statements and the like
`so made are punishable by fine or imprisonment, or both, under Section 1001 of Title 18
`of the United States Code and that such willful false statemenls may jeopardize the
`validity of the above-captioned application or any patent issued thereon.
`
`Karen
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`{J70990s 03037549.DOC}
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`(19) Japan Patent Office (JP)
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`(12) Patent Publication (A)
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`(11) Patent Publication No.
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`JP H08-139092
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`(14) Publication Date: May 31, 1996
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`(51) Intl. Cl.6
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`H01L
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`21/3205
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`ID No.
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`PTO Ref. No.
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`F1
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`Technology Indication Area
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`21/28
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`301 R
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`H01L 21/88
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`Request for Examination Not Requested
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`No. of Claims: 11
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`FD (31 pages total)
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`(21) Application No. Application H07-42612
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`(71) Applicant
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`000003078
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`(22) Application Date February 8, 1995
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`(31) Claimed Priority No. Application H6-22490
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`Toshiba Corporation
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`72 Horikawa-cho, Saiwai-ku,
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`Kawasaki-shi, Kanagawa-ken
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`(32) Priority Date
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` February 21, 1994
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`(72) Inventor
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`Tadashi IIJIMA
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`(33) Claimed Priority Country Japan (JP)
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`(31) Claimed Priority No. Application H6-222017
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`(32) Priority Date
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` September 16, 1994
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`c/o Toshiba Corporation R&D Center
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`1 Komukai Toshiba-cho, Saiwai-ku,
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`Kawasaki-shi, Kanagawa-ken
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`(33) Claimed Priority Country Japan (JP)
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`(72) Inventor
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`Kyoichi SUGURO
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`c/o Toshiba Corporation R&D Center
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`1 Komukai Toshiba-cho, Saiwai-ku,
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`Kawasaki-shi, Kanagawa-ken
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`(72) Inventor
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`Toshiko ONO
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`c/o Toshiba Corporation R&D Center
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`1 Komukai Toshiba-cho, Saiwai-ku,
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`Kawasaki-shi, Kanagawa-ken
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`(74) Representative Patent Agent Takehiko SUZUE
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`Cont’d on last page
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`(54) [Title of Invention] SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
`
`(57) [Abstract]
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`PURPOSE: To provide a semiconductor device capable of improving barrier properties of a barrier
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`metal layer, and which is aimed at improving characteristics of a component, improving reliability of
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`wiring, and the like.
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`{J709905 03020009.DOC}
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`CONFIGURATION: In a semiconductor device wherein a Cu embedded wiring 15 is formed in a
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`groove provided in an SiO2 film 12 formed on a semiconductor substrate 11, a barrier metal layer 14
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`consisting of a ternary compound, which consists of Ti, Si, and N, is formed on bottom and side surfaces
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`of the Cu wiring 15 and a composition ratio of the Si in the barrier metal layer 14 is made higher than
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`that of the Ti in the barrier metal layer 14.
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`[Scope of the Claims]
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`[Claim 1] A semiconductor device having a barrier metal layer provided to at least a bottom surface of
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`an electrode or a wiring layer, the barrier metal layer consisting of a ternary compound which consists of
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`a high melting point metal, silicon, and nitrogen, and wherein a composition ratio of the silicon in the
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`barrier metal layer is larger than the composition ratio of the high melting point metal.
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`[Claim 2] The semiconductor device according to claim 1, wherein titanium is used as the high melting
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`point metal configuring the barrier metal layer.
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`[Claim 3] A semiconductor device having a barrier metal layer and an oxide layer of a metal configuring
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`the barrier metal layer provided to at least a bottom surface of an electrode or a wiring layer.
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`[Claim 4] The semiconductor device according to claim 3, wherein the barrier metal layer is titanium
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`nitride and the oxide layer is titanium oxide.
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`[Claim 5] A semiconductor device having a barrier metal layer provided to at least a bottom surface of
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`an electrode or a wiring layer, the barrier metal layer consisting of a high melting point metal, a
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`semiconductor, and nitrogen, and wherein the high melting point metal configuring the barrier metal
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`layer is one metal selected from among Ti, Zr, Hf, W, and Mo.
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`[Claim 6] A semiconductor device having an electrode or wiring with a three-layer structure in which a
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`barrier metal layer, which consists of a high melting point metal and nitrogen, or a high melting point
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`metal, silicon, and nitrogen, is formed on a polycrystalline silicon layer, and a high melting point metal
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`silicide layer is formed on the barrier metal layer.
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`[Claim 7] A method of manufacturing a semiconductor device comprising:
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`
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`a step of depositing a polycrystalline silicon layer on a substrate;
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`a step of forming a barrier metal layer on the polycrystalline silicon layer, the barrier metal
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`layer consisting of a high melting point metal and nitrogen, or a high melting point metal, silicon, and
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`nitrogen;
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`
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`a step of depositing a high melting point metal silicide layer on the barrier metal layer; and
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`a step of forming a three-layer structure consisting of the polycrystalline silicon layer, the
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`barrier metal layer, and the high melting point metal silicide layer into an electrode or wiring pattern.
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`[Claim 8] A method of manufacturing a semiconductor device comprising:
`
`
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`a step of forming, on a polycrystalline silicon layer, a high melting point metal silicide layer to
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`which nitrogen is added; and
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`
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`a step of forming, on an interface between the high melting point metal silicide layer and the
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`polycrystalline silicon layer, a layer having a higher nitrogen concentration than the high melting point
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`metal silicide layer by performing a heat treatment.
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`[Claim 9] A semiconductor device having a barrier metal layer provided to at least a bottom surface of
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`an electrode or a wiring layer, the barrier metal layer consisting of a ternary compound which consists of
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`a high melting point metal, silicon, and nitrogen, and wherein a composition ratio of the silicon in the
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`barrier metal layer is at least 0.7 relative to the composition ratio of the high melting point metal.
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`[Claim 10] A semiconductor device having a structure where an amorphous alloy layer is formed on at
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`least a bottom surface of an electrode or wiring layer, and microcrystals having a diameter smaller than a
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`film thickness of the alloy layer are contained inside the alloy layer.
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`[Claim 11] A semiconductor device having a structure where an amorphous alloy layer of Ti-Si-N is
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`formed on at least a bottom surface of an electrode or wiring layer, and TiN microcrystals having a
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`diameter smaller than a film thickness of the alloy layer are contained inside the alloy layer.
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`[Detailed Description of the Invention]
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`[0001]
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`[Field of Industrial Application] The present invention relates to a semiconductor device, and in
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`particular relates to a semiconductor device aimed at improving a barrier metal layer in an electrode or
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`wiring. The present invention also relates to a semiconductor device which has an electrode or wiring
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`having a polycide structure, in which a high melting point metal silicide is laminated onto
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`polycrystalline silicon, and to a manufacturing method for the same.
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`[0002]
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`[Description of the Prior Art] Conventionally, a method has been adopted of producing contact in a
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`portion where a wiring layer makes electrical contact with another wiring layer or a component by
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`interposing a layer referred to as a barrier metal. This is aimed at preventing a reaction between the
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`wirings, or between the component and the wiring, preventing diffusion, and obtaining favorable and
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`highly reliable contact. The barrier metal layer is used not only in contact portions, but also when
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`forming wiring or an electrode on a dielectric film.
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`[0003] At present, TiN, TiW, and the like are used as a barrier metal material. Such materials are
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`formed into a film by a sputtering process or the like, and the film produced is a polycrystal and is a
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`columnar crystal in which a grain boundary is at right angles to a ground film. Therefore, the film has a
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`grain boundary which is likely to produce diffusion in a direction in which diffusion is to be prevented,
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`and the film has an unsuitable structure for ensuring barrier properties.
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`[0004] Making a wiring layer low resistance is desired in order to increase performance of a component.
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`In order to do this, a future barrier metal layer must achieve lowered resistance by still further reduction
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`in film thickness. The barrier properties of a reduced thickness barrier metal layer deteriorate more than
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`those of a thick film. Therefore, it is expected that barrier properties are insufficient in the barrier metal
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`layer formation method currently in use. Moreover, in order to obtain perfect barrier properties, a thin
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`film of a monocrystalline body must be used. However, creating a thin film of a monocrystalline body
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`without any defects is extremely difficult and cannot be achieved with present technology.
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`[0005] Although polycrystalline silicon is used in a conventional gate electrode, since the electric
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`resistance of the polycrystalline silicon is high, parasitic resistance of the component is increased,
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`leading to degradation of the component properties. Therefore, use of a metal or a silicide as a low
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`resistance material has been tried. However, in a case where a metal film is formed on a gate dielectric
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`film, during the typical film formation using sputtering and the like the metal film becomes a
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`polycrystal, and therefore a crystal face is not singular, and differences in work function arise for each
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`crystal face. For this reason, work relation differences affecting a semiconductor below the gate
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`dielectric film are no longer constant, threshold voltage is not stable, and it cannot be used as a
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`component.
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`[0006] For example, when using a W film as a gate electrode, a work function changes to 5.25 eV, 4.63
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`eV, and 4.47 eV relative to face orientations (110), (100), and (111) of W. Therefore, it is important
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`for a bottom surface of the W film in contact with the gate dielectric film to be in the same face
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`orientation for control of a threshold value of a transistor.
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`[0007] These days, a polycide structure has come to be generally used in which a high melting point
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`metal silicide (such as MoSix, WSix, and the like) having lower resistance and comparatively excellent
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`heat resistance is laminated onto polycrystalline silicon as a gate structure. These high melting point
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`metal silicides respond well to a process using polycrystalline silicon, and are also dramatically superior
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`in not requiring many changes even when a polycide structure is introduced.
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`[0008] For example, it is well known that gate pressure-proofing and long-term reliability are improved
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`by oxidizing the polycrystalline silicon after working the polycrystalline silicon into the form of a gate
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`electrode, and by increasing the thickness of an oxide film of a gate terminal. Even when a high melting
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`point metal silicide is oxidized simultaneously with polycrystalline silicon at this stage, if the
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`composition contains Si in excess of a stoichiometric composition, SiO2 is formed on the surface instead
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`of a metallic oxide.
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`[0009] However, in order for this to occur, the high melting point metal silicide composition must
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`maintain Si in excess of the stoichiometric composition as described above. Si is consumed by
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`oxidation and the composition becomes still more overmetallic. This change in composition increases
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`the thinner a wiring width of a polycide becomes. In Fig. 33, an average composition of a WSix film
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`when 85 nm of SiO2 is formed on the surface using a 300 nm WSix film having an initial composition of
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`WSi2.50 and WSi2.65 is plotted relative to a wire width.
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`[0010] When the wiring width is set to 0.8 µm or less, the composition approaches a stoichiometric
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`composition WSi, and W becomes still more excessive. The reason for this is that a surface area ratio of
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`surfaces (top and side surfaces) per unit volume increases as the wire width narrows, and therefore a
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`ratio of Si consumed by oxidation increases. In other words, when an amount of oxidation increases, in
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`an effort to hold to a stoichiometric composition, Si is supplied from the polycrystalline silicon on a
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`lower layer in the polycide structure, and therefore intrusion of the high melting point metal silicide into
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`the polycrystalline silicon occurs and, as shown in Fig. 34(a), gate pressure-proofing deteriorates.
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`[0011]
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`[Problem to Be Solved by the Invention] Thus, the barrier properties of the barrier metal layer used for
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`an electrode or wiring cannot be said to be sufficient in the conventional semiconductor device; rather,
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`this is a factor causing deterioration of component characteristics, decreased wiring reliability, and the
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`like. Since the work relations of the metal electrode on the gate dielectric film cannot be controlled,
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`using a metal film as a gate electrode is difficult, which is a problem.
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`[0012] In a polycide structure, when an amount of oxidation increases relative to an amount of high
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`melting point metal silicide, Si is supplied from the lower layer polycrystalline silicon, and gate
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`pressure-proofing deteriorates. This phenomenon is strikingly apparent because the narrower a wire
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`width becomes, the larger a proportion of Si consumption the consumption on the side surface makes up.
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`{J709905 03020009.DOC}
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`Furthermore, the deterioration of pressure-proofing does not take place uniformly over an entire surface
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`of a gate electrode, and originates in localized intrusion of the high melting point metal silicide. In other
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`words, it is thought that the phenomenon occurs as a reflection of non-uniformity of a concentration of
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`high melting point metal silicide and rapid diffusion of silicon at the grain boundary.
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`[0013] The present invention has been conceived in light of the above-noted circumstances, and has as
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`its object to provide a semiconductor device capable of improving barrier properties of a barrier metal
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`layer, and which is aimed at improving characteristics of a component, improving reliability of wiring,
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`and the like.
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`[0014] Another purpose of the present invention is to provide a semiconductor device capable of
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`improving barrier properties of a barrier metal layer, and which is aimed at improving characteristics of
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`a component, improving reliability of wiring, and the like by forming a metal film on a gate dielectric
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`film.
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`[0015] Yet another object of the present invention is to provide a semiconductor device and method of
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`manufacturing the same in which, even in a case where a surface of an electrode or wiring having a
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`polycide structure is oxidized, a reaction between a high melting point metal and polycrystalline silicon
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`can be prevented; no localized intrusion of high melting point metal silicide occurs; and reliability can
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`be improved.
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`[0016]
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`[Means for Solving the Problems] The present invention adopts the following configurations in order to
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`solve the aforementioned problems.
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`[0017] Specifically, the present invention (Claim 1) is a semiconductor device having a barrier metal
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`layer formed on at least a bottom surface of an electrode or a wiring layer. The barrier metal layer is
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`formed with a ternary compound which consists of a high melting point metal, silicon, and nitrogen, and
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`a composition ratio of the silicon in the barrier metal layer is larger than the composition ratio of the
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`high melting point metal.
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`[0018] Here, the following are given as desirable embodiments of the present invention.
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`(1) An electrode or a wiring layer is formed embedded in a groove provided on a surface of a dielectric
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`film, and the barrier metal layer is formed on the bottom surface and side surface of an electrode or a
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`wiring layer.
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`(2) The high melting point metal which constitutes the barrier metal layer is one metal chosen from
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`among Ti, Zr, Hf, Mo, and W.
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`(3) The barrier metal layer is an alloy without a grain boundary.
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`(4) The electrode or the wiring layer is Al, Cu, Ag, W, or an alloy of these metals.
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`[0019] In addition, the present invention (Claim 3) is a semiconductor device having a barrier metal
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`layer formed on at least a bottom surface of an electrode or a wiring layer. An oxide layer of a metal
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`configuring the barrier metal layer is provided between the electrode or wiring layer and the barrier
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`metal layer.
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`[0020] Here, the following are given as desirable embodiments of the present invention.
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`(1) The barrier metal layer is TiN and the metal oxide layer is TiO2.
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`(2) The film thickness of TiO2 as the metal oxide layer is 2 nm or less.
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`(3) TiN is used as a diffusion barrier layer of the wiring layer and has a composition ratio of Ti:N in a
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`range of from 0.95:1.05 to 1.05:0.95.
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`(4) TiN is used as the diffusion barrier layer of the wiring layer and a surface layer is oxidized at a low
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`temperature of 450°C or less by performing an oxygen plasma treatment or ozonation of TiN.
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`(5) The surface is smoothed before forming the diffusion barrier layer of the wiring layer.
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`(6) An average roughness of a smoothed layer is 1 nm or less.
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`[0021] In addition, the present invention (Claim 5) is a semiconductor device having a barrier metal
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`layer formed on at least a bottom surface of an electrode or a wiring layer. The barrier metal layer is
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`formed with a ternary compound which consists of a high melting point metal, a semiconductor, and
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`nitrogen, and the high melting point metal configuring the barrier metal layer is one metal selected from
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`among Ti, Zr, Hf, W, and Mo.
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`[0022] Here, the following are given as desirable embodiments of the present invention in addition to
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`those given as embodiments of Claim 1.
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`(1) The barrier metal layer is formed on the bottom surface and side surface in the case of an electrode,
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`and is formed on the bottom surface, side surface, and top surface in the case of a wiring layer.
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`(2) A semiconductor configuring the barrier metal layer is one selected from among group IV Si, Ge, C,
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`and the like; group III-V compound semiconductors GaAs, InP, InSb, BN, GaP, and the like; group II-
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`VI semiconductors ZnSe, ZnS, CdS, CdTe, and the like; and ternary compound semiconductors of
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`groups II-IV-V, groups I-III-VI, and groups II-V-VII semiconductors, and the like.
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`(3) A composition ratio of the semiconductor in the barrier layer is 0.7 or more of the composition ratio
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`of the high melting point metal.
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`[0023] In addition, the present invention (Claim 6) is a semiconductor device which has an electrode or
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`wiring with a polycide structure. The barrier metal layer, which consists of a high melting point metal
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`and nitrogen, or a high melting point metal, silicon, and nitrogen, is formed on a polycrystalline silicon
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`layer, and a high melting point metal silicide layer is formed on the barrier metal layer.
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`[0024] Here, the following are given as desirable embodiments of the present invention.
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`(1) The high melting point metal configuring the barrier metal layer has at least one of Mo, W, V, Nb,
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`Ta, Ti, and Co as a main component.
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`(2) The metal contained in the high melting point metal silicide layer has at least one of Mo, W, V, Nb,
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`Ta, Ti, and Co as a main component.
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`[0025] In addition, the present invention (Claim 8) is method of manufacturing a semiconductor device
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`which has an electrode or wiring with a polycide structure. The method includes a step of forming, on a
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`polycrystalline silicon layer, a high melting point metal silicide layer to which nitrogen is added; and a
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`step of forming, on an interface between the high melting point metal silicide layer and the
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`polycrystalline silicon layer, a layer having a higher nitrogen concentration than the high melting point
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`metal silicide layer by performing a heat treatment.
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`[0026] In addition, the present invention (Claim 10) is a semiconductor device having an amorphous
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`alloy layer formed on at least a bottom surface of an electrode or wiring layer. The semiconductor
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`device has a structure where microcrystals having a diameter smaller than a film thickness of the alloy
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`layer are contained inside the alloy layer.
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`[0027] Here, the following are given as desirable embodiments of the present invention.
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`(1) The element configuring the amorphous alloy layer contains a high melting point metal Ti, Zr, Hf, V,
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`Nb, Ta, Cr, W, or Mo.
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`(2) An element configuring the amorphous alloy layer is one semiconductor selected from among group
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`IV Si, Ge, and C; group III-V compound semiconductors GaAs, InP, InSb, BN, and GaP; group II-VI
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`semiconductors ZnSe, ZnS, CdS, and CdTe; and ternary compound semiconductors of groups II-IV-VI,
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`groups II-IV-V, groups III-IV-VI, groups I-III-VI, and groups II-V-VII semiconductors.
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`(3) The element configuring the microcrystals is a nitrogen compound of a high melting point metal.
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`(4) The microcrystals are 2 nm or less.
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`(5) The amorphous alloy layer is Ti-Si-N, and the microcrystals are TiN.
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`(6) The alloy layer is W-Si-N and the microcrystals are W or WxNy.
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`[0028]
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`[Effect] According to the present invention, a barrier metal layer is formed with a ternary compound of a
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`high melting point metal, Si, and N, and preferably a metal composition is 70% or more, and in
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`particular the barrier metal layer is preferably Si rich relative to the metal. The barrier metal layer
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`becomes amorphous at high temperatures. For this reason, there is no diffusion which passes through
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`the grain boundary as when TiN is used, and barrier properties can be improved. Moreover, film stress
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`can be minimized and the barrier metal layer is effective in improving component characteristics.
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`[0029] Also, since Ti is readily reduced to an oxide film (natural oxide film), in a case where Ti is used
`
`as the high melting point metal, adhesion of the barrier metal layer is favorable and readily takes
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`contact. Moreover, since bonding strength of Ti with N is high, the composition of the barrier metal
`
`layer is stabilized. Since the standard free energy of formation of Ti, Zr, or Hf with N is more greatly
`
`negative as compared to Ta or the like, when Ti, Zr, or Hf are used as the high melting point metal, Ti,
`
`Zr, and Hf have a film structure that is stable with respect to heating, and improvement in barrier
`
`properties can be targeted. Implementation of the present invention makes it clear that the present
`
`invention has superior adhesion with a ground dielectric film, and low contact resistance with a ground
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`or upper electrode.
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`[0030] According to the present invention, a metal oxide layer is formed on the surface of the barrier
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`metal layer. Therefore, the oxide layer inhibits diffusion through the grain boundary. Moreover, when
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`the film thickness of the oxide layer is defined as 2 nm or less, contact resistivity between upper layer
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`and lower layer wirings can also be sufficiently lowered, and no increase in contact resistance is caused.
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`[0031] Thus, according to the present invention, the barrier properties of a barrier metal layer can be
`
`improved, diffusion of impurities can be inhibited, and the reliability of wiring can be improved.
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`[0032] In addition, according to the present invention, by forming a layer of three elements or of four
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`elements consisting of metal-Si-nitrogen or metal-Si-nitrogen-oxygen as a high melting point metal
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`silicide / polycrystalline silicon reaction inhibiting layer in a polycide structure, the polycide structure is
`
`stable and does not cause degradation of gate pressure-proofing even when subjected to a heat process.
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`[0033] Also, according to the present invention and as shown in Figs. 35(a) and (b), an alloy is used
`
`which has the structure where microcrystals equal to or less than the film thickness are contained inside
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`the amorphous structure. Therefore, there is no diffusion by grain boundary diffusion, such as when
`
`using TiN, and improvement in barrier properties can be targeted. Moreover, by using an alloy having
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`the above-noted structure on the gate dielectric film, work functions can be controlled individually and
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`the reliability and performance of a component can be improved.
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`[0034]
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`[Embodiments] Hereinafter, the details of the present invention are described according to an
`
`embodiment shown in the drawings.
`
`(Embodiment 1) Figs. 1 describe a semiconductor device according to a first embodiment of the present
`
`invention, and are cross-sectional views showing an embedded wiring formation process.
`
`[0035] First, as shown in Fig. 1(a), an SiO2 film 12 is deposited as a dielectric film on a semiconductor
`
`substrate 11 using a CVD method or the like, and a groove 13 is formed in a surface of the SiO2 film 12
`
`by an RIE method or the like. In this example, although SiO2 is used as the dielectric film, polyimide or
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`the like may be used instead. In addition, the surface of the groove 13 is preferably smoothed by a
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`method such as CDE, polishing, and the like. In this case, a preferred degree of smoothness is an
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`average roughness of 1 nm or less.
`
`[0036] Next, as shown in Fig. 1(b), 25 nm of a TiSiN film (barrier metal layer) 14, which is a ternary
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`compound of Ti, Si, and N, is formed as a diffusion barrier film and an adhesion layer. A formation
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`method uses a DC magnetron sputtering device and, using a Ti silicide target, forms the TiSiN film by
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`reactive sputtering with argon and N2 flow rates in a range from 10 and 30 sccm to 30 and 100 sccm,
`
`pressure at 0.3 Pa, and power at about 1 kW. The sputtered film is checked as being amorphous using
`
`XRD analysis.
`
`[0037] The formation method of the TiSiN film 14 and the conditions of the method are not restricted to
`
`the above, and can be changed as appropriate according to specifications. For example, a sputtering
`
`method is known using a target in which Ti, Si, and N are arrayed in a mosaic shape.
`
`[0038] In this example, a composition ratio of Ti and Si in the TiSiN film 14 has a significant influence
`
`on film stress. A composition ratio X of Ti and Si (Si/Ti) was changed in various ways to form a TiSiN
`
`film, and compression stress in each case was measured. The results shown in Fig. 2 were obtained.
`
`This figure shows that compression stress decreases rapidly when the composition ratio X of Si and Ti is
`
`1 or more. When compression stress is high, problems are encountered such as component
`
`characteristics being degraded (component characteristics: component speed, electrical reliability, and
`
`the like), a film peeling off and being impossible to laminate, and the like. Under these circumstances,
`
`the composition ratio X of Si and Ti is preferably larger than 1.
`
`[0039] Although there is a tendency for resistance to be lower for a composition ratio of Ti, Si, and N
`
`having a high ratio of Ti, when a thin film is formed, there is no effect on wiring resistance even when
`
`resistance is somewhat high, and therefore there are no such problems even when the composition is Si,
`
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`as mentioned above. Also, in order to improve adhesion, a thin film of Ti or the like may be formed
`
`ahead of time.
`
`[0040] As described previously also, since the ternary compound of Ti, Si, and N is noncrystalline, film
`
`stress is low (for example, 1.7 x109 dyn/cm2) and a possibility that there will be adverse effects on a
`
`component is low. Also, there is no grain boundary, as the word "noncrystalline" implies (as in glass,
`
`for example). For this reason, diffusion of impurities due to grain boundary diffusion, which was a
`
`problem with the thin film having the polycrystalline structure of TiN or TiW, which is used
`
`conventionally, can be prevented and ideal barrier properties can be obtained.
`
`[0041] For reference, characteristics of the thin films formed when the composition ratio of TiSiN is
`
`changed are shown in the following (Table 1).
`
`[0042]
`
`[Table 1]
`
`Orientation (X-ray
`
`Composition
`
`intensity ratio)
`
`I (111)/I (200)
`
`Stress
`
`109 dyn/cm2
`
`Crystallinity
`
`TiSi2.2N3.7
`
`TiSi3.5N4.6
`
`TiSi3.2N4.2
`
`TiN
`
`56.57
`
`41.22
`
`183.1
`
`7.58
`
`4.72
`
`1.37
`
`Amorphous
`
`and stable
`
`ρ
`
`mΩcm
`
`1.5
`
`1.1
`
`1.4
`
`(comparative
`
`8.88
`
`14.8
`
`Polycrystalline
`
`0.07
`
`example)
`
`
`
`Next, as shown in Fig. 1(c), a 400 nm Cu film 15 (main wiring layer) is deposited by a sputtering
`
`method. At this point, the Cu film 15 and the TiSiN film 14 may also be deposited in succession,
`
`without exposure to the atmosphere. Then, as shown in Fig. 1(d), by performing annealing at about 200
`
`to 700°C during or after sputtering, the Cu is reflowed and is embedded so as to be flat. In this case, an
`
`annealing atmosphere can be an atmosphere having oxidizing gases (for example, oxygen, water)
`
`removed (1 ppm or less) or an atmosphere having reducible gases (for example, hydrogen) added, for
`
`example.
`
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`[0043] Next, as shown in Fig. 1(e), portions other than the groove 13 are etched and an embedded
`
`wiring layer which consists of Cu is formed. The etching is performed by RIE, ion milling, polishing,
`
`and the like. Thereby, highly reliable wiring is formed.
`
`[0044] According to the present embodiment, the ternary compound of Ti, Si, and N (the TiSiN film 14)
`
`is used as the barrier metal layer and is Si rich as compared to Ti. Therefore, the barrier metal layer
`
`remains amorphous up to high temperatures. In experiments by the inventors, the ternary compound of
`
`Ti, Si, and N was thermally stable and remained amorphous even when undergoing annealing at 750°C
`
`for 30 minutes, and did not crystallize. For this reason, there is no diffusion which passes through the
`
`grain boundary as when TiN is used, and barrier properties can be improved. Moreover, since the
`
`compound is considered Si rich in comparison to metal, film stress can be sufficiently minimized and
`
`the compound is effective in improving component characteristics.
`
`(Embodiment 2) Figs. 3 describe a semiconductor device according to a second embodiment of the
`
`present invention, and are cross-sectional views showing a wiring formation process.
`
`[0045] First, as shown in Fig. 3(a), an SiO2 film 32 (dielectric film) is formed on a semiconductor
`
`substrate 31, and onto this a 10 to 25 nm TiSiN film (barrier metal layer) 34 is formed by a sputtering
`
`method as a barrier metal layer and an adhesion layer, the TiSiN film 34 being a ternary compound of
`
`Ti, Si, and N. Then, 400 nm of a Cu film 35 is formed as a main wiring layer. In this embodiment also,
`
`the composition of the TiSiN film 34 was made Si rich.
`
`[0046] Next, as shown in Fig. 3(b), a pattern of a resist 36 is formed on the Cu film 35 using
`
`photolithography. Then, as shown in Fig. 3(c), selective etching of the Cu film 35 and the TiSiN film 34
`
`is performed using RIE, which uses a chlorine-based gas, or an ion milling method, a wet etching
`
`method using acid, or the like, with the resist 36 as a mask.
`
`[0047] Next, as shown in Fig. 3(d), the resist 36 is stripped by downflow ashing using an organic solvent
`
`or a mixed oxygen and fluoride-based gas, or by an RIE method using oxygen gas. Thereby, the wiring
`
`using TiSiN as the barrier metal layer is formed.
`
`[0048] Thus, in this embodiment also, wiring using the ternary compound of Ti, Si, and N as the barrier
`
`metal layer 34 can be formed, and the same beneficial effects as the first embodiment above are
`
`achieved.
`
`(Embodiment 3) Figs. 4 describe a semiconductor device according to a third embodiment of the present
`
`invention, and are cross-sectional views showi