Case IPR2016-01247
`U.S. Patent No. 7,126,174
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`Filed on behalf of Godo Kaisha IP Bridge 1
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`By: Neil F. Greenblum (ngreenblum@gbpatent.com)
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`Greenblum & Bernstein, P.L.C.
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`1950 Roland Clarke Place
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`Reston, VA 20191
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`Tel: 703-716-1191
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`Fax: 703-716-1180
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________
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`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED,
`Petitioner,
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`v.
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`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
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`Case IPR2016-01247
`U.S. Patent No. 7,126,174
`____________
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`PATENT OWNER’S PRELIMINARY RESPONSE
`PURSUANT TO 37 C.F.R. §42.107
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`Mail Stop PATENT BOARD, PTAB
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`I.
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`II.
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`Case IPR2016-01247
`U.S. Patent No. 7,126,174
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`TABLE OF CONTENTS
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`REQUESTED RELIEF ................................................................................ 1
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`INTRODUCTION ....................................................................................... 1
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`A. Dispositive Issue In IPR2016-01246 And IPR2016-01247 ................ 2
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`B.
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`C.
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`Background........................................................................................ 3
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`The Premise Of The Petitioner’s Argument Is Legally Insufficient ...10
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`III. RELEVANT CASE LAW ..........................................................................15
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`A.
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`B.
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`C.
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`There Must Be A Likelihood Of Invalidity .......................................15
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`The Burden Of Persuasion ................................................................15
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`The Petitioner Bears The Burden Of Establishing A Rationale For
`Combining The Prior Art ..................................................................16
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`D.
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`The PTO Is Bound By Record Arguments Petitioner Has Made .......17
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`IV. THE CLAIMED INVENTION OF THE ‘174 PATENT.............................18
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`V.
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`LEVEL OF ORDINARY SKILL ................................................................20
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`VI. CLAIM CONSTRUCTION ........................................................................20
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`VII. THE ‘174 PATENT – RIGHT OF PRIORITY ...........................................22
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`VIII. PRIOR ART ...............................................................................................22
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`A. U.S. Patent No. 5,021,353 (“Lowrey”) ..............................................23
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`B. U.S. Patent No. 5,539,229 (“Noble”) ................................................24
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`C. U.S. Patent No. 4,506,434 (“Ogawa”) ..............................................25
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`IX. ARGUMENT: LOWREY & NOBLE ...........................................................27
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`A. Claim 1 Of The ‘174 Patent ..............................................................27
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`B.
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`C.
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`Lowrey Is Not Compatible With Trench Isolation .............................28
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`The Initial Processing Sequence Of Lowrey ......................................29
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`D. As A General Matter Trench Isolation Is Incompatible With
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`Lowrey ..............................................................................................34
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`E.
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`Substituting STI in Lowrey Would Cause A Doping Problem ...........40
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`F.
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`Conclusions Regarding The Lowrey-Noble Combination ..................42
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`X. ARGUMENT: LOWREY & OGAWA ..........................................................43
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`A.
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`Initial Processing Sequence Of Ogawa .............................................44
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`B.
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`The Petition Fails To Describe How Lowrey Could Be Combined
`With Ogawa To Render The Challenged Claims Unpatentable .........46
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`C. Conclusions Regarding The Lowrey-Ogawa Combination ................48
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`XI. CONCLUSION ..........................................................................................49
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`Cases
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`Case IPR2016-01247
`U.S. Patent No. 7,126,174
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`TABLE OF AUTHORITIES
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`Allied Erecting and Dismantling Co., Inc. v. Genesis Attachments, LLC,
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` 825 F.3d 1373, 1381 (Fed. Cir. 2016). ...............................................................16
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`Arendi S.A.R.L. v. Apple Inc.,
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` No. 2015-2073, 2016 WL 4205964, at *9 (Fed. Cir. Aug. 10, 2016) .................17
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`Dynamic Drinkware, LLC v. Nat'l Graphics, Inc.,
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` 800 F.3d 1375, 1378 (Fed. Cir. 2015). ...............................................................15
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`In re Giannelli,
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` 739 F. 3d 1375, 1380 (Fed. Cir. 2014) ...............................................................17
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`In re Lee,
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` 277 F.3d 1338, 1345 (Fed. Cir. 2002) ................................................................16
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`In re Warsaw Orthopedic, Inc.,
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` 2016 U.S. App. LEXIS 14560, *18 (Fed. Cir. 2016) ..........................................16
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`In re: Lemay,
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` 2016 U.S. App. LEXIS 17041, *5 (Fed. Cir. 2016). ...........................................17
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`In Re: Magnum Oil Tools International, Ltd.,
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` 119 U.S.P.Q.2D 1541, 1548, 1552, 1553 (Fed. Cir. 2016). .................... 15, 16, 17
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`Pfizer, Inc. v. Apotex, Inc.,
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` 480 F.3d 1348, 1361 (Fed. Cir. 2007) ................................................................16
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`Phillips v. AWH Corp.,
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` 415 F.3d 1303 (Fed. Cir. 2005) ..........................................................................20
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`Synopsys, Inc. v. Mentor Graphics Corp.,
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` 814 F.3d 1309, 1322 (Fed. Cir. 2016) ................................................................16
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`STATUTES
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`Case IPR2016-01247
`U.S. Patent No. 7,126,174
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`35 U.S.C. §103 ............................................................................................... 43, 48
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`35 U.S.C. §313 ...................................................................................................... 1
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`35 U.S.C. §314 ...................................................................................................... 1
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`35 U.S.C. §316(e) .................................................................................................15
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`REGULATIONS
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`37 C.F.R. §42.100 et seq. ....................................................................................... 1
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`37 C.F.R. §42.100(b) ............................................................................................20
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`37 C.F.R. §42.107 .................................................................................................. 1
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`37 C.F.R. §42.108. ................................................................................ 1, 15, 43, 49
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`EXHIBIT LIST
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`Exhibit 2001:
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`Declaration of Dr. E. Fred Schubert, Ph.D. in support of
`Patent Owner’s Preliminary Response
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`Exhibit 2002:
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`Exhibit 2003:
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`Exhibit 2004:
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`Schematic illustration of the Chemical Mechanical Polishing
`process from Steigerwald, Murarka, and Gutmann, Chemical
`Mechanical Planarization of Microelectronic Materials (1997).
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`Schematic illustration of the Chemical Mechanical Polishing
`process from the Motorola Company. SCSolutions.com.
`Accessed September 30, 2016.
`http://www.scsolutions.com/chemical-mechanical-
`planarization-cmp-controllers-0
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`Photograph of a Chemical Mechanical Polishing Tool from the
`Applied Materials Company. BusinessWire.com. Accessed
`October 5, 2016.
`http://www.businesswire.com/news/home/20040711005007/en/
`Applied-Materials-Revolutionizes-Planarization-Technology-
`Breakthrough-Reflexion
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`Exhibit 2005:
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`Troxel, Boning, McIlrath “Semiconductor Process
`Representation.” Wiley Encyclopedia of Electrical and
`Electronics, pp.139 –147 (1999).
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`Exhibit 2006:
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`U.S. Patent No. 6,052,319 to Jacobs
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`Exhibit 2007:
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`U.S. Patent No. 6,952,656 to Cordova et al.
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`Exhibit 2008:
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`Hunt, “Low Budget Undergraduate Microelectronics
`Laboratory.” University Government Industry Microelectronics
`Symposium, pp.81-87 (2006).
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`Exhibit 2009:
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`U.S. Patent No. 7,074,709 to Young
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`Exhibit 2010:
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`Burckel, “3D-ICs created using oblique processing.” Advanced
`in Patterning Materials and Processes XXXIII, pp. 1–12 (2016).
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`I.
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`REQUESTED RELIEF
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`Case IPR2016-01247
`U.S. Patent No. 7,126,174
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`Pursuant to 35 U.S.C. §313 and 37 C.F.R. §42.107, Patent Owner Godo
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`Kaisha IP Bridge 1 (“Patent Owner”) respectfully requests that the Patent Trial and
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`Appeal Board (“PTAB”) decline to institute an inter partes review under 35 U.S.C.
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`§314 based on the Petition for Inter Partes Review of U.S. Patent No. 7,126,174
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`pursuant to 37 C.F.R. §42.100 et seq. (IPR2016-01247, “Petition”) filed by Taiwan
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`Semiconductor Manufacturing Company, Ltd. (“Petitioner”) on June 24, 2016.
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`II.
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`INTRODUCTION
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`The Petition requests review of Claims 1, 4, 5, 8-12, 14, and 16 (“challenged
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`claims”) of U.S. Patent No. 7,126,174 (“the ‘174 Patent”) (Exhibit 1001)(Petition,
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`p. 17). Claim 1 is the only challenged independent claim. The Petition asserts that
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`the challenged claims are unpatentable for obviousness over (1) U.S. Patent No.
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`5,021,353 (“Lowrey”)(Exhibit 1017) in view of U.S. Patent No. 5,539,229
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`(“Noble”)(Exhibit 1015), or (2) Lowrey in view of U.S. Patent No. 4,506,434
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`(“Ogawa”)(Exhibit 1010). The ‘174 patent expired on July 24, 2016.
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`As explained herein, the Petition fails to demonstrate that there is a
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`reasonable likelihood that at least one of the claims challenged in the Petition is
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`unpatentable. 37 C.F.R. §42.108. Specifically, the Petition fails to establish that it
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`would have been obvious to a person of ordinary skill in the art (“POSITA”) to
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`modify the semiconductor device formed by LOCOS (Local Oxidation of Silicon)
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`disclosed in Lowrey with the semiconductor device formed by shallow trench
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`isolation (STI) disclosed in Noble or Ogawa, to arrive at the invention recited in
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`the challenged claims. The Petition’s obviousness arguments of Lowrey in view of
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`Noble and Lowrey in view of Ogawa fail to demonstrate that there is a reasonable
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`likelihood that at least one of the claims challenged in the petition is unpatentable.
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`Thus, for at least the reasons set forth herein, the PTAB should deny institution of
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`this IPR proceeding.
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`A. Dispositive Issue In IPR2016-01246 And IPR2016-01247
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`Petitioner has concurrently filed two IPR Petitions challenging the ‘174
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`patent: IPR2016-01246 and IPR2016-01247.
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`In IPR2016-01246, the Petition asserts that the challenged claims are
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`unpatentable over Lee in combination with Noble or Ogawa, and in IPR2016-
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`01247, the Petition asserts that the challenged claims are unpatentable over Lowrey
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`in combination with Noble or Ogawa.
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`There are various reasons why each of the proposed rejections is
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`insufficient, however, there is at least one dispositive issue applicable to all four of
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`the proposed rejections.
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`The four proposed rejections are needlessly redundant of one another. In
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`each of the four proposed rejections, the Petition asserts that the primary reference
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`(Lee or Lowrey) teaches every limitation of the challenged claims except trench
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`isolation. The Petitions then both assert that Noble or Ogawa discloses trench
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`isolation, and that as a general proposition it would have been obvious to substitute
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`trench isolation for the LOCOS isolation disclosed in the primary references.
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`Neither the Petition in IPR2016-01246 nor the Petition in IPR2016-01247
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`describes how the fabrication processes disclosed in the prior art references could
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`be combined to form the subject matter recited in the challenged claims. For
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`example, neither Petition addresses the fact that to form a trench isolation,
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`“planarization” of the substrate is necessary. Planarization removes material and
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`evens out any irregular topography, making the wafer flat or planar. The primary
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`references (Lee and Lowrey) each have structural features that will be disrupted
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`and/or removed by planarization if a trench isolation is attempted to be formed,
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`and the Petitions fail to describe how such a substitution would even be possible,
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`let alone have been obvious. For at least this reason, neither Petition establishes a
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`reasonable likelihood of unpatentability of any of the challenged claims. As such,
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`both Petitions should be denied.
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`B.
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`Background
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`Integrated circuits (ICs) are highly complex electrical systems located on a
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`small microstructured silicon chip (Si chip). An integrated circuit can have
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`millions of transistors that serve to process, store, and transport information. The
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`core element of an integrated circuit is the transistor, specifically the field-effect
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`transistor (FET) that uses an electric field (“field effect”) in order to create charge
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`carriers in the transistor’s channel region. Exhibit 2001, ¶¶33-34. The channel
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`region connects the transistor’s source (S) with the transistor’s drain (D). The
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`source and drain are separated by the gate (G) that controls the flow of charge in
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`the channel between the source and drain. Exhibit 2001, ¶34.
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` The transistor’s gate typically has a three-layer stack consisting of (top to
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`bottom) a gate metal or metal-like material (M), a gate dielectric or oxide (O), and
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`a semiconductor (S), thereby forming the MOS layer stack or gate layer stack.
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`Accordingly, transistors based on the MOS layer stack are called MOSFETs.
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`Exhibit 2001, ¶35. The circuit layout is the result of (i) the circuit functionality
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`designed by design engineers and (ii) the designed circuit’s implementation on a Si
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`IC chip fabricated by a processing sequence devised by process engineers. Exhibit
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`2001, ¶37.
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`The processing sequence takes place in a fabrication facility, also
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`abbreviated as “fab” or “IC fab”, including a first group of fabrication processes
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`called front end of line (FEOL) processes, and a second group of fabrication
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`processes called back end of line (BEOL) processes. The FEOL processes include
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`the fabrication of the transistors (MOSFETS) including the salicidation1 of source,
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`gate, and drain. The BEOL processes include the fabrication of metal-based
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`interconnect lines and associated dielectric layers (interlayer dielectrics or ILDs)
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`that electrically insulate the metal interconnects from each other. Exhibit 2001,
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`¶38.
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`IC processing requires (i) high spatial precision during lithography (to attain
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`very small patterns) and (ii) cleanliness (to avoid contaminations). The processing
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`of Si wafers proceeds in a strict sequence of processing steps (or processing
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`modules) that are carefully chosen in sequence and content. Exhibit 2001, ¶¶39-40.
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`For example, the gate stack of a transistor requires the availability of an Si
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`substrate, followed by the deposition or growth of the gate dielectric (commonly an
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`oxide), and concluded by the deposition of the gate conductor. This processing
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`sequence is mandatory, and it would become ineffectual if it were altered. That is,
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`certain elements of an IC may require the preexistence of other elements and rely
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`on their presence for the proper functioning of the ensemble of elements. Exhibit
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`2001, ¶¶40-41. For example, the source/drain dopant implant requires the presence
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`1 Silicidation is the process of forming a metal silicide from a metal deposited on
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`silicon. Salicidation is the process when performed in a self-aligned manner. That
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`is “self-aligned silicidation” is abbreviated as salicidation.
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`of the gate so that the gate can mask the channel region from the implantation ion
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`beam. That is, the gate enables the proper definition of the source/drain implanted
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`regions. Such an implantation in which the source/drain regions are automatically
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`aligned with the gate electrode is referred to as a “self-aligned implantation
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`process.” Exhibit 2001, ¶41.
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`A series of individual processing steps constitute a “processing module”. It
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`is generally not possible to reverse the sequence of processing steps within a
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`module. Exhibit 2001, ¶42. For example, the formation of shallow trench isolation
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`(STI) constitutes a processing module that involves the following processing steps:
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`(i) trench etching, (ii) trench refill with silicon dioxide, and (iii) planarization.
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`These steps are the major steps of the trench isolation module.2 Exhibit 2001, ¶43.
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`2 In addition to the major steps of trench formation, there are minor steps not listed
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`above. A more complete series of steps employed for trench formation may
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`include: oxide pad deposition; nitride pad deposition; resist coating; photo
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`lithography; nitride etching; oxide etching; trench etching by means of a dry etch;
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`resist strip; liner-oxide growth; trench refill with CVD silicon dioxide; annealing
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`to improve quality of oxide; planarization by CMP (chemical mechanical
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`planarization); various cleaning steps and rinsing steps are used throughout the
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`module (major steps emphasized). Exhibit 2001, ¶43.
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`Planarization is a process by which the top surface of the wafer is made flat
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`or planarized. It can occur at various stages of the fabrication, and as is relevant
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`here, it occurs after formation of the trench refill process. Exhibit 2001, ¶52.
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`Each processing step (or processing module) is intended and is implemented
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`for a specific initial configuration of the Si wafer. Each processing step (or
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`processing module including a plurality of steps) transforms the Si wafer from an
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`initial configuration to a final configuration associated with this specific
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`processing step. Similarly, each processing module (with each processing module
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`consisting of a sequence of multiple processing steps) transforms the Si wafer
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`from an initial configuration to a final configuration associated with this specific
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`processing module. Exhibit 2001, ¶¶45-46.
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`When taking a specific processing step (within one processing module) out
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`of its intended sequence and inserting it at another point in the sequence of
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`processing steps, one must ensure the following:
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`First, the sequence of processing steps preceding a specific processing step
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`that is being inserted must provide an initial configuration compatible with the
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`specific processing step. Id. Second, the final configuration resulting from the
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`specific processing step must be compatible with the subsequent processing step
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`and beyond. Exhibit 2001, ¶47.
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` Given the initial and final configuration of a Si wafer, a specific processing
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`step must be compatible with the overall fabrication process. As would be
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`understood by a POSITA (as well as by an unskilled person with common sense), a
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`random change in the sequence in processing steps may well not lead to the desired
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`result. If such random change is implemented nonetheless, it would likely lead to a
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`non-functioning IC device. Exhibit 2001, ¶48. Changing the sequence of
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`processing steps requires that the fabrication process be re-engineered, e.g., the
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`entire front-end-of-line (FEOL) fabrication process may need to be re-engineered,
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`which may lead to substantial changes in the fabrication of the Si IC device. Id.
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` The same tenet discussed above for processing steps also applies to the
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`sequence of processing modules: When taking a specific processing module out of
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`its intended sequence and inserting it at another point in the sequence of processing
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`modules, one must ensure the following:
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` First, the sequence of processing modules preceding a specific processing
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`module that is being inserted must provide an initial configuration compatible with
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`the specific processing module. Exhibit 2001, ¶49. Second, the final configuration
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`resulting from the specific processing module must be compatible with the
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`subsequent processing module and beyond. Id.
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` The same conclusion that was drawn above for a specific processing step
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`can be drawn for a specific processing module: As would be understood by a
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`POSITA (as well as by an unskilled person having common sense), a random
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`change in the sequence of processing modules would not lead to the desired result;
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`if such a change were implemented nonetheless, it would in all likelihood lead to a
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`non-functioning IC device. Exhibit 2001, ¶50.
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` Planarization must be performed at a specific point in the sequence of the
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`trench fabrication process. Dr. Banerjee’s declaration (Exhibit 1004) never
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`addresses the planarization process (e.g., the CMP process) that is inextricably
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`associated with STI. Exhibit 2001, ¶63. He never once acknowledges the process
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`re-design and re-engineering which would be necessary when combining the pairs
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`of prior art references to create a trench isolation involving planarization. Dr.
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`Banerjee’s declaration gives no consideration how and whether the planarization
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`process could be made to work on a non-planar surface topology of a wafer. The
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`implementation of the STI process on a wafer having a non-planar surface
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`topology will generally result in a non-functioning IC device unless the fabrication
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`process is comprehensively re-engineered. Exhibit 2001, ¶¶67-69. Dr. Banerjee
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`never says how this could be done while still achieving the final structure recited in
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`the challenged claims of the ’174 patent. Exhibit 2001, ¶70.
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` Dr. Banerjee’s declaration never addresses whether it would even be
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`possible to fabricate the combinations of the elements that he proposes would be
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`obvious to combine. He asserts in a conclusory fashion that such fabrication
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`would be obvious without providing an appropriate analysis of how the fabrication
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`could be accomplished, if it could be accomplished at all. Exhibit 2001, ¶¶54-55,
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`70.
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`It is certainly no coincidence that every prior art reference upon which
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`Petitioner relies, as well as the ‘174 patent itself, provides an extensive sequence of
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`detailed fabrication process steps including relevant engineering details. It is
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`precisely this type of information which would be needed to establish
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`obviousness and which Petitioner has elected not to provide to show how and
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`whether his proposed combinations could ever be achieved. As a matter of law
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`the Petition is insufficient.
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`C. The Premise Of The Petitioner’s Argument Is Legally Insufficient
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`Petitioner asserts that “Lowrey teaches every limitation of the challenged
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`claims except trench isolation.” Petition, p. 21. Petitioner devotes a great deal of
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`effort attempting to explain that although Lowrey does not teach or disclose STI, a
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`POSITA would have understood that Noble’s or Ogawa’s STI was a known
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`substitute for Lowrey’s LOCOS isolation. Petition, pp. 21, 63.
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`LOCOS isolation refers to the selective local oxidation of a silicon substrate
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`to form an isolation region. Exhibit 2001, ¶58. Trench isolation, such as shallow
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`trench isolation (STI) involves selectively etching a substrate to form trenches
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`which are subsequently filled with an insulating material followed by planarization
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`of the wafer. Exhibit 2001, ¶59.
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`The Petition fails to address the fact that when combining references relating
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`to semiconductor devices, the process (“process sequence”) by which the
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`integrated circuit (IC) devices are formed is inseparable from their final structure
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`as claimed. Exhibit 2001, ¶¶80-81. As such, simply substituting a component from
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`one device, e.g., STI, for a different component in another device, e.g., LOCOS
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`isolation, can provide unworkable results, both in terms of how the substituted
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`component cooperates with other components, and how the changed
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`manufacturing sequence, which is required to effectuate such substitution, can be
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`implemented. Id. This is particularly true for Si ICs where a single film can serve
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`multiple purposes, and where a multitude of different functional features are
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`condensed into a minimum number of layers and processing steps. Id.
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`Petitioner’s obviousness arguments simply swap out the LOCOS isolation
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`(Lowrey) for the STI (Noble and Ogawa) without describing how such a
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`substitution could be accomplished and without giving due consideration to the
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`strong interconnectedness and interdependency of the Si IC fabrication process. A
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`LOCOS isolation is formed using a very different process sequence than the
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`process sequence used to form an STI. Exhibit 2001, ¶81. To produce an operative
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`device, their very different respective fabrication processes must be merged,
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`integrated, and made compatible with their respective fabrication processes. If this
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`is not possible, a merged structure will not be possible. Id.
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`Petitioner never once addresses how and when Noble’s and Ogawa’s STI
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`can be substituted in for Lowrey’s LOCOS isolation. Indeed, it would have been
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`apparent to a POSITA at the time of invention that the incompatible process
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`sequences for forming the STI disclosed in Noble or Ogawa would not have been
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`substitutable for the LOCOS isolation of Lowrey, and as such, there would have
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`been no motivation for the POSITA to substitute the LOCOS isolation of Lowrey
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`with the STI of Noble or Ogawa. Exhibit 2001, ¶81.
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`The Petition does not explain how and at what stage of the fabrication of
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`Lowrey either the trench of Noble or Ogawa should be formed. Petitioner’s expert
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`Dr. Banerjee barely addresses the issue. For example, Dr. Banerjee concludes:
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`As a person of ordinary skill in the art would have recognized,
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`Noble’s raised STI structure also enables device density to
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`increase beyond what Lowrey’s LOCOS would allow by
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`eliminating the bird’s beak. Schuegraf and Ogawa show this.
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`(Schuegraf at 1:47–55, 2:22–24; Ogawa at 1:17–21, 1:40–42,
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`1:58–60, Fig. 1.) Moreover, a person of ordinary skill in the art
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`would have understood that replacing Lowrey’s LOCOS with
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`Noble’s STI would have been entirely compatible and had no
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`impact on the processes used for gate formation, source/drain
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`formation, L-shaped sidewall formation, silicide formation, or
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`any other aspect of the claims. LOCOS and STI are both
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`methods for forming insulating materials in the same locations
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`of the substrate to perform the same function. They are both
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`performed near the very beginning in device processing,
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`and how the isolation regions are formed would not affect
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`Lowrey’s processes or the resultant device structures.
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`Exhibit 1004, ¶93.
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`Dr. Banerjee similarly concludes:
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`To address the problems of LOCOS, Ogawa discloses “an
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`improvement applicable to methods for production of buried
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`insulating layers.” (Ogawa at 1:8–15.) A person of ordinary
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`skill in the art would have understood that combining the
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`processes of Lowrey and Ogawa would have been a simple
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`matter of replacing the LOCOS oxidation in Lowrey with the
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`trench isolation of Ogawa. (Schuegraf at 2:20-22.) A person of
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`ordinary skill in the art would have understood that replacing
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`Lowrey’s LOCOS with Ogawa’s STI would have been entirely
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`compatible and had no impact on the processes used for gate
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`formation, source/drain formation, L-shaped sidewall
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`formation, silicide formation, or any other aspect of the claims.
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`LOCOS and STI are both methods for forming insulating
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`materials in the same locations of the substrate to perform the
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`same function. They are both performed near the very
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`beginning in device processing, and how the isolation regions
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`are formed would not affect Lowrey’s processes or the resultant
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`device structures.
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`Exhibit 1004, ¶173.
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`Petitioner cites to Schuegraf, which merely discloses that Shallow Trench
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`Isolation (STI) is used primarily for isolating devices of the same type and “is
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`often considered an alternative to LOCOS isolation.” Exhibit 1009, 2:20-22;
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`Petition, pp. 23-24. Merely asserting that STI is an alternative to LOCOS does not
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`provide any guidance on the difficulties and challenges making the substitution
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`into a pre-existing fabrication process, in this case Lowrey. As for the remainder of
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`the paragraphs, no support is provided for the conclusions. Dr. Banerjee’s mistaken
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`and unsupported assertion seems to be the entire basis for the asserted
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`combination.
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`This incompatibility and unworkability negates any motivation to modify
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`Lowrey by replacing Lowrey’s LOCOS isolation with Noble’s or Ogawa’s trench
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`isolation. This lack of motivation renders Lowrey ineffective as the starting point
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`of a validity challenge of the claims of the ‘174 patent, and any resulting
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`combination of references is legally insufficient to justify initiating inter partes
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`review of the ‘174 patent.
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`III.
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`RELEVANT CASE LAW
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`Case IPR2016-01247
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`A.
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`There Must Be A Likelihood Of Invalidity
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`Inter partes review shall not be instituted for a ground of unpatentability
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`unless the Board decides that the petition supporting the ground would demonstrate
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`that there is a reasonable likelihood that at least one of the claims challenged in the
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`petition is unpatentable. 37 C.F.R. §42.108. The Board's decision will take into
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`account a patent owner preliminary response where such a response is filed,
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`including any testimonial evidence, but a genuine issue of material fact created by
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`such testimonial evidence will be viewed in the light most favorable to the
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`petitioner solely for purposes of deciding whether to institute an inter partes
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`review. Id.
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`B.
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`The Burden Of Persuasion
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`The Petition must demonstrate that there is a reasonable likelihood that at
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`least one of the claims challenged in the petition is unpatentable. 37 C.F.R.
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`§42.108. “The burden of persuasion is on the Petitioner to establish the
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`unpatentability of the claims, and that burden never shifts.” In Re: Magnum Oil
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`Tools International, Ltd., 119 U.S.P.Q.2D 1541, 1548 (Fed. Cir. 2016).
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`“In an inter partes review, the burden of persuasion is on the petitioner to
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`prove ‘unpatentability by a preponderance of the evidence,’ 35 U.S.C. §316(e), and
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`that burden never shifts to the patentee.” Dynamic Drinkware, LLC v. Nat'l
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`Graphics, Inc., 800 F.3d 1375, 1378 (Fed. Cir. 2015). Indeed, “the Supreme Court
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`has never imposed nor even contemplated a formal burden- shifting framework in
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`the patent litigation context.” In Re: Magnum Oil Tools International, Ltd., 119
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`U.S.P.Q.2D 1541, 1548 (Fed. Cir. 2016).
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`C. The Petitioner Bears The Burden Of Establishing A Rationale For
`Combining The Prior Art
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`“The test is whether ‘a skilled artisan would have been motivated to
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`combine the teachings of the prior art references to achieve the claimed
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`invention.’” Pfizer, Inc. v. Apotex, Inc., 480 F.3d 1348, 1361 (Fed. Cir. 2007);
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`Allied Erecting and Dismantling Co., Inc. v. Genesis Attachments, LLC, 825 F.3d
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`1373, 1381 (Fed. Cir. 2016).
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`“To satisfy its burden of proving obviousness, a petitioner cannot employ
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`mere conclusory statements. The petitioner must instead articulate specific
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`reasoning, based on evidence of record, to support the legal conclusion of
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`obviousness.” In Re: Magnum Oil Tools International, Ltd., 119 U.S.P.Q.2D 1541,
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`1552 (Fed. Cir. 2016). (emphasis added).
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` “The PTAB’s conclusory assertion that Figure 5 of Jacobson ‘appears to’
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`support its finding does not equate to the reasoned explanation needed to support it
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`conclusion.” Synopsys, Inc. v. Mentor Graphics Corp., 814 F.3d 1309, 1322 (Fed.
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`Cir. 2016); see also In re Lee, 277 F.3d 1338, 1345 (Fed. Cir. 2002) (“The [PTAB]
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`cannot rely on conclusory statements when dealing with…prior art and specific
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`claims, but must set forth the