`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`Taiwan Semiconductor Manufacturing Company, Ltd.
`
`Petitioner
`
`v.
`
`Godo Kaisha IP Bridge 1
`
`
`
`Patent Owner
`
`
`
`Patent No. 7,126,174
`Filing Date: November 24, 2004
`Issue Date: October 24, 2006
`
`Title: SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING
`THE SAME
`
`
`
`Inter Partes Review No. IPR2016-01247
`
`
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 ET SEQ.
`
`
`
`
`
`Table of Contents
`
`I.
`
`PRELIMINARY STATEMENT ................................................................... 1
`
`II. TECHNOLOGICAL BACKGROUND ....................................................... 1
`
`A.
`
`B.
`
`Integrated Circuits ................................................................................. 1
`
`Isolation Structures ................................................................................ 4
`
`1.
`
`2.
`
`LOCOS ........................................................................................ 4
`
`Shallow Trench Isolation ............................................................ 5
`
`C.
`
`Insulating Sidewalls .............................................................................. 7
`
`III. THE ’174 PATENT ......................................................................................10
`
`A. Admitted Prior Art...............................................................................10
`
`B.
`
`C.
`
`D.
`
`Challenged Claims ..............................................................................11
`
`Representative Embodiment ...............................................................12
`
`The ’174 Patent Is Not Entitled to the Benefit of Foreign
`Priority Before December 19, 1995 ....................................................14
`
`IV. Statement of Precise Relief Requested for Each Claim Challenged .......15
`
`A.
`
`B.
`
`C.
`
`D.
`
`Claims for Which Review is Requested ..............................................15
`
`Statutory Grounds of Challenge ..........................................................16
`
`Level of Ordinary Skill .......................................................................16
`
`Claim Construction..............................................................................16
`
`V. Claims 1, 4, 5, 8–12, 14, and 16 of the ’174 Patent Are
`Unpatentable ................................................................................................17
`
`A. Disclosures of the Prior Art .................................................................17
`
`1.
`
`2.
`
`Lowrey (U.S. Patent No. 5,021,353) .........................................18
`
`Noble (U.S. Patent No. 5,539,229) ...........................................19
`
`
`
`3.
`
`Ogawa (U.S. Patent No. 4,506,434) .........................................20
`
`B.
`
`The Lowrey-Noble combination renders claims 1, 4, 5, 8–12,
`14, and 16 obvious...............................................................................21
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`A POSITA would have found it obvious and even
`desirable to have combined the teachings of Lowrey and
`Noble .........................................................................................21
`
`Claim 1 is obvious over Lowrey and Noble ..............................30
`
`Claim 4 is obvious over Lowrey and Noble ..............................44
`
`Claim 5 is obvious over Lowrey and Noble ..............................46
`
`Claim 8 is obvious over Lowrey and Noble ..............................48
`
`Claim 9 is obvious over Lowrey and Noble ..............................50
`
`Claim 10 is obvious over Lowrey and Noble ............................52
`
`Claim 11 is obvious over Lowrey and Noble ............................55
`
`Claim 12 is obvious over Lowrey and Noble ............................56
`
`10. Claim 14 is obvious over Lowrey and Noble ............................58
`
`11. Claim 16 is obvious over Lowrey and Noble ............................59
`
`C.
`
`The Lowrey-Ogawa combination renders claims 1, 4, 5, 8–12,
`14, and 16 obvious...............................................................................62
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`A POSITA would have combined the teachings of
`Lowrey and Ogawa ...................................................................63
`
`Claim 1 is obvious over Lowrey and Ogawa ............................68
`
`Claim 4 is obvious over Lowrey and Ogawa ............................71
`
`Claim 5 is obvious over Lowrey and Ogawa ............................72
`
`Claim 8 is obvious over Lowrey and Ogawa ............................72
`
`Claim 9 is obvious over Lowrey and Ogawa ............................72
`
`
`
`ii
`
`
`
`7.
`7.
`
`8.
`8.
`
`9.
`9.
`
`Claim 10 is obvious over Lowrey and Ogawa ..........................73
`Claim 10 is obvious over Lowrey and Ogawa ........................ ..73
`
`Claim 11 is obvious over Lowrey and Ogawa ..........................74
`Claim 11 is obvious over Lowrey and Ogawa ........................ ..74
`
`Claim 12 is obvious over Lowrey and Ogawa ..........................75
`Claim 12 is obvious over Lowrey and Ogawa ........................ ..75
`
`10. Claim 14 is obvious over Lowrey and Ogawa ..........................75
`10.
`Claim 14 is obvious over Lowrey and Ogawa ........................ ..75
`
`11. Claim 16 is obvious over Lowrey and Ogawa ..........................75
`11.
`Claim 16 is obvious over Lowrey and Ogawa ........................ ..75
`
`VI. Trial Should Be Instituted on Both Grounds ............................................76
`
`Trial Should Be Instituted on Both Grounds .......................................... ..76
`
`VI.
`
`VII. Mandatory Notices Under 37 C.F.R. §42.8 ...............................................76
`Mandatory Notices Under 37 C.F.R. §42.8 ...............................................76
`
`VII.
`
`A.
`
`A.
`
`B.
`
`B.
`
`C.
`C.
`
`D.
`
`D.
`
`Real Parties-In-Interest ........................................................................76
`
`Real Parties—In—Interest ...................................................................... ..76
`
`Related Matters ....................................................................................76
`
`Related Matters .................................................................................. ..76
`
`Lead and Back-Up Counsel .................................................................77
`Lead and Back—Up Counsel ............................................................... ..77
`
`Service Information .............................................................................78
`
`Service Information ........................................................................... ..78
`
`VIII. Certification Under 37 C.F.R. §42.24(d) ...................................................78
`Certification Under 37 C.F.R. §42.24(d) ...................................................78
`
`VIII.
`
`IX. Payment of Fees ...........................................................................................78
`Payment of Fees ...........................................................................................78
`
`IX.
`
`X.
`
`Time for Filing Petition ...............................................................................78
`Time for Filing Petition ...............................................................................78
`
`XI. Grounds for Standing ..................................................................................79
`Grounds for Standing ..................................................................................79
`
`XI.
`
`XII. Conclusion ....................................................................................................79
`
`Conclusion ....................................................................................................79
`
`XII.
`
`
`
`
`
`iii
`
`iii
`
`
`
`
`
`Table of Authorities
`
`Cases
`
`Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc) .........................16
`
`Statutes
`
`35 U.S.C. §103 .........................................................................................................16
`
`35 U.S.C. §321 .........................................................................................................15
`
`Other Authorities
`
`Liberty Mutual Inc. Co. v. Progressive Casualty Ins. Co., CMB2012-00003,
`Paper 7 (Oct. 25, 2012) .......................................................................................76
`
`Rules
`
`37 C.F.R. §42.1(b) ...................................................................................................76
`
`37 C.F.R. §42.100(b) ...............................................................................................16
`
`37 C.F.R. §42.101(b) ...............................................................................................78
`
`37 C.F.R. §42.103(a) ................................................................................................78
`
`37 C.F.R. §42.104(a) ................................................................................................79
`
`37 C.F.R. §42.15(a) ..................................................................................................78
`
`37 C.F.R. §42.24 ......................................................................................................78
`
`37 C.F.R. §42.8 ................................................................................................. 76, 78
`
`
`
`iv
`
`
`
`
`
`
`
`
`
`LIST OF EXHIBITS
`
`Petition Exhibit 1001: U.S. Patent No. 7,126,174 to Segawa et al.
`
`Petition Exhibit 1002: U.S. Patent No. 5,153,145 to Lee et al.
`
`Petition Exhibit 1003: U.S. Patent No. 3,617,824 to Shinoda et al.
`
`Petition Exhibit 1004: Expert Declaration of Dr. Sanjay Banerjee, Ph.D.
`
`Petition Exhibit 1005:
`
`J.A. Appels et al., “Some Problems of MOS
`Technology,” Philips Tech. Rev. vol. 31 nos. 7–9, pp.
`225–36, 276 (1970).
`
`Petition Exhibit 1006: U.S. Patent No. 4,110,899 to Nagasawa et al.
`
`Petition Exhibit 1007: U.S. Patent No. 3,787,251 to Brand et al.
`
`Petition Exhibit 1008: B.B.M. Brandt et al., “LOCMOS, a New Technology for
`Complementary MOS Circuits,” Philips Tech. Rev. vol.
`34 no. 1, pp. 19–23 (1974).
`
`Petition Exhibit 1009: U.S. Patent No. 5,702,976 to Schuegraf et al.
`
`Petition Exhibit 1010: U.S. Patent No. 4,506,434 to Ogawa et al.
`
`Petition Exhibit 1011: U.S. Patent No. 4,957,590 to Douglas
`
`Petition Exhibit 1012: U.S. Patent No. 5,976,939 to Thompson et al.
`
`Petition Exhibit 1013: U.S. Patent No. 6,165,826 to Chau et al.
`
`Petition Exhibit 1014: U.S. Patent No. 5,733,812 to Ueda et al.
`
`Petition Exhibit 1015: U.S. Patent No. 5,539,229 to Noble, Jr. et al.
`
`Petition Exhibit 1016: U.S. Patent No. 5,521,422 to Mandelman et al.
`
`Petition Exhibit 1017: U.S. Patent No. 5,021,353 to Lowrey et al.
`
`Petition Exhibit 1018: U.S. Patent No. 4,638,347 to Iyer
`
`Petition Exhibit 1019:
`
`Japanese Patent Application No. 7-192181 to Segawa et
`al.
`
`
`
`v
`
`
`
`Petition Exhibit 1020: Certified Translation of Japanese Patent Application No.
`7-192181 to Segawa et al.
`
`Petition Exhibit 1021: File History of U.S. Patent No. 7,126,174 to Segawa et
`al.
`
`Petition Exhibit 1022: File History of Japanese Patent Application No.
`7-330112 to Segawa et al.
`
`Petition Exhibit 1023: Certified Translation of Portions of the File History of
`Japanese Patent Application No. 7-330112 to Segawa et
`al.
`
`
`
`
`
`vi
`
`
`
`I.
`
`PRELIMINARY STATEMENT
`
`U.S. Patent No. 7,126,174 to Segawa et al. (Ex. 1001) is directed to certain
`
`structures for metal-oxide-semiconductor field-effect transistors (“MOSFETs”)
`
`and their interconnections. MOSFETs, which can act as switches in integrated
`
`circuits, are linked by interconnections, which connect parts of an integrated circuit
`
`to one another.
`
`MOSFET integrated circuits debuted as early as 1965 (see Ex. 1003). By
`
`the mid-1990s, MOSFET/interconnection structures were ubiquitous. Virtually all
`
`of the limitations in the challenged claims were known and constitute admitted
`
`prior art. (See Ex. 1001, 1:52–5:51, Figs. 17, 20(e).) The only feature of the sole
`
`independent claim in the ’174 patent, claim 1, that is not admitted prior art is the
`
`feature of “L-shaped” sidewalls over the MOSFET and interconnection. But this
`
`feature had been known for over a decade before the ’174 patent was filed.
`
`This Petition, supported by the Expert Declaration of Sanjay Banerjee,
`
`Ph.D., (Ex. 1004), establishes that the challenged claims are unpatentable over the
`
`prior art. TSMC respectfully requests inter partes review under 35 U.S.C. §§311–
`
`319 and 37 C.F.R. §42.100 et seq. and cancellation of all challenged claims.
`
`II. TECHNOLOGICAL BACKGROUND
`Integrated Circuits
`A.
`A MOSFET includes a “source,” an inlet to receive current, and a “drain” as
`
`an outlet to output current. (Ex. 1004, ¶44.) Electrodes on the source and drain
`
`
`
`allow current to flow into and out of the transistor. (Id.) Another basic MOSFET
`
`element is a “gate,” which controls current flow between the source and drain
`
`through a “channel” beneath the gate. (Id.) The gate includes a gate insulator
`
`(“gate oxide” or “gate dielectric”) and a gate electrode (“gate”). (Id., ¶45.) The
`
`gate electrode can receive a control voltage to switch the MOSFET on and off, and
`
`the gate insulator generates an associated electric field that controls the channel.
`
`(Id.) “ON” and “OFF” states of a MOSFET are depicted below. (Id.; Ex. 1003,
`
`Fig. 5 (below with color annotation).)
`
`
`
`
`
` ON
`
`
`
`
`
`
`
`
`
`
`
` OFF
`
`To form circuits, MOSFETs are connected by interconnections, which are
`
`electrical conductors that provide pathways for electrical signals. (Ex. 1004, ¶46.)
`
`They can be made from a variety of conducting materials, including metals, metal
`
`alloys, metal compounds, polycrystalline silicon (polysilicon), and combinations of
`
`these (e.g., metal-silicon compounds, called “silicides”). (Id.)
`
`
`
`2
`
`
`
`Integrated circuits having multiple MOSFETs and interconnections have
`
`existed for over 50 years. For example, a patent filed in 1965 discloses multilevel
`
`interconnections formed between MOSFETs in an integrated circuit. (U.S. Patent
`
`No. 3,617,824 to Shinoda et al., Ex. 1003, 4:30–73, Figs. 6–7 (below with color
`
`and annotation).)
`
`
`
`
`
`
`
`3
`
`
`
`Isolation Structures
`
`B.
`The semiconductor industry has steadily moved towards packing more
`
`MOSFETs onto each chip. (Ex. 1004, ¶48.) As device densities increase, the
`
`distance between devices shrinks, and by the early 1970s, decreasing inter-device
`
`distances started to cause undesirable interactions between circuit elements. (See
`
`Ex. 1005, 10–12; Ex. 1006, 1:40–2:26; Ex. 1007, 1:6–2:32; Ex. 1004, ¶49.) The
`
`industry’s solution to this problem was to include insulating “isolation” regions
`
`between the devices to shield them from one another. (Ex. 1005, 10–12; Ex. 1006,
`
`1:7–2:66; Ex. 1007, 1:6–2:32; Ex. 1008, 2–5; Ex. 1004, ¶49.) Use of such
`
`isolation regions has continued through the present time. (Ex. 1004, ¶49.)
`
`LOCOS
`
`1.
`Reported as early as 1970, LOCOS (LOCal Oxidation of Silicon) was one of
`
`the first isolation techniques. (Ex. 1005, 2, 13; Ex. 1008, 2 & n.4; Ex. 1006, 1:8–
`
`14, 1:63–68; Ex. 1004, ¶50.) In LOCOS, selected regions of a silicon substrate are
`
`exposed to oxygen at a high temperature to convert the silicon in those regions into
`
`silicon dioxide. (Ex. 1005, 4, 6, 10; Ex. 1006, 3:18–20, 4:18–34; Ex. 1008, 2–3;
`
`Ex. 1004, ¶50.)
`
`LOCOS has drawbacks. Silicon dioxide grows laterally as the substrate is
`
`oxidized, resulting in unintentional silicon dioxide projections into MOSFET
`
`regions, called “overhang” or “bird’s beaks.” (Ex. 1006, 6:1:10; Ex. 1009, 1:47–
`
`
`
`4
`
`
`
`59; Ex. 1004, ¶51; Ex. 1008, Fig. 2a; Ex. 1010, 1:33–42, Fig. 1 (below with color
`
`and annotation).) By the mid-1990s, this bird’s beak “pose[d] a limitation to
`
`device density” that could be addressed by new isolation techniques. (Ex. 1009,
`
`1:47–59; see also Ex. 1001, 1:29–43 (admitted prior art); Ex. 1004, ¶51.) The
`
`bird’s beak (see annotated Fig. 1 below from U.S. Patent No. 4,506,434 to Ogawa
`
`et al.) also causes undesirable strain. (Ex. 1010, Fig. 1, 1:42–50).
`
`
`
`Shallow Trench Isolation
`
`2.
`Shallow trench isolation (STI) was developed to replace LOCOS for small-
`
`device processes. (Ex. 1001, 1:29–43; Ex. 1009, 2:20–24; Ex. 1004, ¶52.) In STI,
`
`trenches are etched into the substrate and filled with insulating material. (Ex.
`
`1004, ¶52.) Although more expensive and complex than LOCOS, STI resolves the
`
`problems of LOCOS. (Ex. 1009, 2:20–24; Ex. 1010, 1:60–68; Ex. 1004, ¶52.)
`
`Because they are so similar otherwise, STI and LOCOS are interchangeable and
`
`functionally equivalent. (See Ex. 1009, 1:31–2:24; Ex. 1011, 4:8–16; Ex. 1012,
`
`3:1–10; Ex. 1013, 5:56–67; Ex. 1014, 22:49–52; Ex. 1004, ¶53.) Despite the
`
`
`
`5
`
`
`
`added expense and complexity, the industry adopted STI to increase device
`
`density. (Ex. 1004, ¶53; see also Ex. 1002, 1:10–14.)
`
`In some STI processes, the top of the isolation structure is level with the
`
`substrate surface. The industry recognized, however, that such an arrangement can
`
`interfere with MOSFET operation if the transistors are packed too closely, as sharp
`
`corners of the STI structure enhance local electric fields that degrade device
`
`performance. (Ex. 1016, 1:16–37, Abstract, 1:6–35, Figs. 6a, 6b; Ex. 1004, ¶54.)
`
`These problems become worse if the isolation trench recesses below the substrate
`
`surface during subsequent etches because the gate can then “wrap around” the
`
`trench corner. (Ex. 1016, 1:30–37, 3:27–48, 4:58–62, Fig. 2; Ex. 1004, ¶54.)
`
`To mitigate the wrap-around problem, a raised STI structure can extend
`
`above the substrate surface. (See Ex. 1015, 5:49–55, 6:32–50, Fig. 12; Ex. 1016,
`
`Abstract, 3:33–34, Fig. 5; Ex. 1004, ¶55.) Raised STI also helps localize
`
`source/drain regions by providing a barrier during the ion implantation or diffusion
`
`processes used to make them. (Ex. 1015, Abstract, 4:62–65, 5:5–8; Ex. 1004, ¶55.)
`
`Raised STI structures from the prior art appear below in red. (Ex. 1010, Fig. 5(b);
`
`Ex. 1015, Fig. 11; Ex. 1016, Fig. 5.)
`
`
`
`6
`
`
`
`
`
`Insulating Sidewalls
`
`C.
`The ’174 patent acknowledges that a “conventional semiconductor device”
`
`had MOSFETs, interconnections, and STI regions with sidewalls. (Ex. 1001,
`
`1:52–2:21, Figs. 17 (below with color annotation), 20(e); Ex. 1004, ¶56.)
`
`Sidewalls 7a and 7b of features 4a and 4b, respectively, appear below.
`
`
`
`Sidewalls can (1) prevent damage during etching, (2) insulate electrodes and
`
`interconnections to eliminate short-circuits, (3) control the shape of the
`
`source/drain regions by creating a barrier against the migration of impurities, and
`
`
`
`7
`
`
`
`(4) reduce parasitic leakage current. (Ex. 1015, 5:5–9, 6:6–8, 6:32–50; Ex. 1002,
`
`1:44–54, 1:64–2:20, 3:22–30, 5:51–6:4, 6:62–7:7, 7:44–8:5, Fig. 15; Ex. 1016,
`
`1:6–10, 3:49–53, 4:5–17, 4:30–32, 4:58–5:2, Fig. 5; Ex. 1017, 8:58–9:2; Ex. 1004,
`
`¶57.)
`
`U.S. Patent No. 5,153,145 to Lee et al. (Ex. 1002), provides sidewalls on
`
`gates and gate runners (interconnections) to avoid short-circuits. (Id., 1:47–54.) In
`
`response to “increasingly complex interconnection schemes” (Ex. 1002, 1:44–
`
`47), Lee provided insulating sidewalls on the gates and gate runners (Id., 6:62–7:7,
`
`Figs. 13, 15). These “prevent[] electrical contact between patterned layer 170 and
`
`the conductive polysilicon heart 117′ of runner 203” and “facilitate[] the formation
`
`of a sub-gate level interconnection between junction regions of different transistors
`
`. . . without the possibility of shorting to a gate runner.” (Id., 7:44–8:5.) Figure 15
`
`of Lee appears below with color.
`
`
`
`8
`
`
`
`
`
`The process for creating a silicon-metal “silicide” may damage the gate (id.,
`
`1:40–43), so Lee discloses insulating gate sidewall spacers between the gate and
`
`source/drain to address this. (Id., 4:41–5:4, 5:51–60, 7:16–25, Fig. 9 (shown below
`
`with color).) Lee explains that sidewalls “prevent the migration of other types or
`
`particles into the gate stack” to avoid “shorting of the gate to the source/drain.”
`
`(Id., 5:61–6:30; Ex. 1004, ¶59).
`
`
`
`As Lee and other references show, L-shaped sidewalls were known in the
`
`semiconductor processing art. (Ex. 1004, ¶60; Ex. 1002, 3:8–21, Figs. 9, 15; Ex.
`
`1018, 3:61–68, Fig. 5 (shown below on left with color); Ex. 1012, 3:1–10, 4:1–10,
`
`Fig. 7 (shown below on right with color).)
`
`
`
`
`
`9
`
`
`
`
`
`III. THE ’174 PATENT
`A. Admitted Prior Art
`The ’174 patent describes a semiconductor device “with high integration and
`
`a decreased area.” (Ex. 1001, 1:13–16.) The ’174 patent explains that “there
`
`[we]re increasing demands for more refinement of the semiconductor device.”
`
`(Id., 1:17–20.) Although “the LOCOS isolation method [had been] conventionally
`
`adopted in view of its simpleness [sic] and low cost,” the ’174 patent admits that
`
`others already recognized that trench isolation was “more advantageous for
`
`manufacturing a refined semiconductor device.” (Id., 1:17–28.) This was because
`
`the bird’s beak of LOCOS “invades a transistor region against the actually
`
`designed mask dimension,” which was “unallowable” for scaling beyond 0.5 μm.
`
`(Id., 1:29–36.) The ’174 patent further admits, “even in the mass-production
`
`techniques, the isolation forming method ha[d] started to be changed to the trench
`
`isolation method.” (Id., 1:36–43.) The ’174 patent also describes “conventional
`
`semiconductor device[s]” with “the conventional trench isolation,” shown below in
`
`color-annotated Figures 17 and 20(e). (Id., 1:44–2:22, 3:53–5:11.) The ’174
`
`patent further shows that trench isolation with a top surface higher than the surface
`
`of the semiconductor substrate is part of a “conventional trench isolation and a
`
`MOSFET.” (Id., 3:53–55, 3:64–4:8, 4:45–58, 4:16–19, Figs. 19, 20(a)–20(e) (Fig.
`
`20(e) shown below with color annotations).)
`
`
`
`10
`
`
`
`
`
`
`
`B. Challenged Claims1
`The only independent claim of the ’174 patent recites:
`
`
`1 The challenged claims are claims 1, 4, 5, 8–12, 14, and 16.
`
`
`
`11
`
`
`
`1. A semiconductor device, comprising:
`a trench isolation surrounding an active area of a semiconductor
`substrate;
`a gate insulating film formed over the active area;
`a gate electrode formed over the gate insulating film;
`first L-shaped sidewalls formed over the side surfaces of the
`gate electrode;
`first silicide layers formed on regions located on the sides of the
`first L-shaped sidewalls within the active area;
`an interconnection formed on the trench isolation; and
`second L-shaped sidewalls formed over the side surfaces of the
`interconnection.
`(Ex. 1001, 29:39–50.) Claims 4, 5, 8–12, 14, and 16 depend from claim 1.
`
`C. Representative Embodiment
`As shown below in color-annotated Figure 15(f) of the ’174 patent, one
`
`embodiment of the claimed structure has a trench isolation region (2b), a gate
`
`electrode (4a), an interconnection (4b), a gate electrode sidewall (32a), and an
`
`interconnection sidewall (32b). (Ex. 1001, 21:39–65, 26:40–54, 27:4–8, Figs.
`
`15(a)–15(f).) Isolation region 2b may have a top surface higher in a stepwise
`
`manner than the surface of an active area. (Ex. 1001, 13:49–64, 15:34–36.)
`
`Further, the gate and interconnection sidewalls (32a and 32b) are “L-shaped.” (Id.,
`
`27:4–8.)
`
`
`
`12
`
`
`
`
`
`For comparison, “a semiconductor device including the conventional trench
`
`isolation and a MOSFET having the salicide structure,” as the ’174 patent
`
`characterizes it, is shown below. (Ex. 1001, 3:53–5:11, Fig. 20(e) (below with
`
`color annotations).) The only difference relevant to the claim limitations is the “L-
`
`shaped” sidewall feature.
`
`
`
`
`
`13
`
`
`
`D. The ’174 Patent Is Not Entitled to the Benefit of Foreign Priority
`Before December 19, 1995
`The ’174 patent, filed on November 24, 2004,2 claims priority to Japanese
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`Patent Application No. 7-192181 (“the ’181 application”) (Ex. 1019; Ex. 1020),
`
`filed on July 27, 1995, and Japanese Patent Application No. 7-330112 (“the ’112
`
`application”)(Ex. 1022; Ex. 1023), filed on December 19, 1995.3 The challenged
`
`claims are not entitled to the July 1995 priority date.
`
`The ’181 application does not disclose the claimed “first silicide layers” or
`
`even mention silicide. The local interconnection (13) is polysilicon, as is the
`
`interconnection (4b). (Ex. 1020, ¶¶0004, 0009, 0057, 0066, 0072, 0078–0081,
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`0086, 0094, p. 28.)
`
`The ’181 application also does not provide support for the required “first L-
`
`shaped sidewalls formed over the side surfaces of the gate electrode” or “second L-
`
`shaped sidewalls formed over the side surfaces of the interconnection.” The term
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`“L-shaped” does not appear in the ’181 application, and the structures shown in the
`
`’181 application lack the claimed “L” shape. (See Ex. 1019, 38–45; Ex. 1004,
`
`
`2 The ’174 patent claims priority through a line of intervening applications to
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`parent U.S. Application No. 08/685,726, filed on Jul. 24, 1996. (Ex. 1021, 137.)
`
`3 The Japanese Patent Office rejected these applications over the prior art
`
`and never issued a patent. (Ex. 1023, 187–93.)
`
`
`
`14
`
`
`
`¶¶66–69.) The “sidewalls” in the ’181 application, labeled 7a and 7b, are not even
`
`remotely L-shaped. (See Ex. 1020, Fig. 4(a) (below with color annotations).)
`
`
`
`The “insulating film” of the ’181 application, labeled 12, does not constitute
`
`L-shaped sidewalls either. A POSITA (“person of ordinary skill in the art”) would
`
`not have considered a unitary layer that extends over the entire gate or
`
`interconnection to be a “sidewall” or to have “sidewalls.” (Ex. 1004,¶¶67–68.)
`
`Due to these deficiencies, the ’174 patent is not entitled to the July 27, 1995,
`
`priority date of the ’181 application. Because the ’174 patent does not claim the
`
`benefit of foreign priority to any other document other that the ’112 application
`
`filed December 19, 1995, the ’174 patent is not entitled to a benefit of foreign
`
`priority earlier than December 19, 1995.
`
`IV. Statement of Precise Relief Requested for Each Claim Challenged
`A. Claims for Which Review is Requested
`TSMC requests review under 35 U.S.C. §311 of claims 1, 4, 5, 8–12, 14, and
`
`16 and the cancellation of those claims as unpatentable.
`
`
`
`15
`
`
`
`Statutory Grounds of Challenge
`
`B.
`Claims 1, 4, 5, 8–12, 14, and 16 are unpatentable under 35 U.S.C. §103.
`
`C. Level of Ordinary Skill
`A POSITA would possess (1) the equivalent of a Master of Science degree
`
`from an accredited institution in electrical engineering, materials science, physics,
`
`or the equivalent; (2) a working knowledge of semiconductor processing
`
`technologies for integrated circuits; and (3) at least two years of experience in
`
`related semiconductor processing analysis, design, and development. Additional
`
`graduate education could substitute for professional experience, and significant
`
`work experience could substitute for formal education. (Ex. 1004, ¶72.)
`
`D. Claim Construction
`Claim terms are given their ordinary and accustomed meaning as understood
`
`by a POSITA. Phillips v. AWH Corp., 415 F.3d 1303, 1312–13 (Fed. Cir. 2005)
`
`(en banc). Although a claim in an unexpired patent in inter partes review receives
`
`the “broadest reasonable construction in light of the specification of the patent in
`
`which it appears,” 37 C.F.R. §42.100(b), the ’174 patent will expire on July 24,
`
`2016, so the Phillips standard for claim construction should govern this petition,
`
`see id. The plain and ordinary meaning as understood by a POSITA should be
`
`applied to all claim terms of the ’174 patent.
`
`
`
`16
`
`
`
`V. Claims 1, 4, 5, 8–12, 14, and 16 of the ’174 Patent Are Unpatentable
`Lowrey (Ex. 1017) teaches every limitation of the challenged claims except
`
`trench isolation. It uses LOCOS isolation instead. Noble (Ex. 1015) and Ogawa
`
`(Ex. 1010) each disclose devices very similar to Lowrey but that use trench
`
`isolation. Therefore, the Lowrey-Noble and Lowrey-Ogawa combinations disclose
`
`every limitation of the challenged claims.
`
`A POSITA would have been motivated to make the Lowrey-Noble and
`
`Lowrey-Ogawa combinations for many reasons. The admitted prior art of the ’174
`
`patent, and other contemporary references, describe the transition in the 1990s
`
`away from LOCOS toward trench isolation. A POSITA would have understood
`
`that replacing Lowrey’s LOCOS with Noble’s STI or Ogawa’s buried trench
`
`isolation would have just been a simple substitution of one element for a known
`
`equivalent according to known methods to achieve predictable results. A POSITA
`
`would have further understood that making such combinations would have
`
`provided numerous benefits.
`
`A. Disclosures of the Prior Art
`The structures claimed by the ’174 patent were well-known in the art. The
`
`discussion below represents a sampling of the knowledge available to a POSITA
`
`years before the application for the ’174 patent.
`
`
`
`17
`
`
`
`Lowrey (U.S. Patent No. 5,021,353)
`1.
`Lowrey (Ex. 1017) teaches every element of the challenged claims except
`
`for trench isolation. Lowrey was filed February 26, 1990, and issued June 4, 1991.
`
`It therefore qualifies as prior art under §102(b). Lowrey was neither considered
`
`nor cited during prosecution of the ’174 patent.
`
`Lowrey discloses a MOSFET/interconnection structure. Referring to the
`
`illustration of the Lowrey structure below (color-annotated Fig. 12 of Lowrey),
`
`Lowrey discloses a silicon substrate (12) (Ex. 1017, 7:57–64), a field oxide (51)
`
`(id., 1:64–2:32, 8:31–35), source/drain regions (61, 63, 82, 121) (id., 8:53–9:2,
`
`9:18–22, 10:3–15), a gate oxide (31 or 52) (id., 8:37–52), a gate electrode (56)
`
`(id., 8:44–47, 10:3–15), sidewall spacers (62, 71) (id., 8:61–9:12), silicide regions
`
`(122) (id., 10:3–15), and an interconnection (57) (id., 7:14–20, 8:44–47, 9:6–12,
`
`10:3–15).
`
`
`
`18
`
`
`
`
`
`Noble (U.S. Patent No. 5,539,229)
`2.
`Noble (Ex. 1015) teaches trench isolation. Noble was filed on December 28,
`
`1994, and issued on July 23, 1996. It therefore qualifies as prior art at least under
`
`§102(e).
`
`Noble “relates to shallow trench isolation (STI) in which the insulating
`
`material is raised above the surface of the semiconductor.” (Ex. 1015, 1:7–10, Fig.
`
`13 (below).) Noble discloses a silicon substrate (10) (id., 3:59–62), a raised STI
`
`region (30) (id., 4:14–19, 4:40–45, 4:63–65), substrate source/drain regions
`
`(138, 156) (id., 6:13–31), a gate dielectric (14) (id., 3:64–4:1, 4:11–14), a gate
`
`conductor (116) (id., 5:67–6:6), dielectric spacers (152) (id., 6:6–8), silicide
`
`regions (158) (id., 6:24–26), and conductive wiring level (140) (id., 5:53–61,
`
`5:67–6:6). A representative illustration appears below.
`
`
`
`19
`
`
`
`
`
`Ogawa (U.S. Patent No. 4,506,434)
`3.
`Ogawa (Ex. 1010) also teaches trench isolation. Ogawa was filed on
`
`September 3, 1982, and issued on March 26, 1985. It therefore qualifies as prior
`
`art under §102(b). Ogawa was neither considered nor cited during prosecution of
`
`the ’174 patent.
`
`Ogawa teaches “a method wherein each element is isolated from one another
`
`by buried insulating layers which are grown to fill grooves produced along the
`
`surface of a silicon (Si) substrate to surround each element.” (Ex. 1010, 1:61–66;
`
`see also 1:8–15, Fig. 5(c) (below).) Ogawa discloses a silicon substrate (51) (id.,
`
`7:43–47), a buried silicon dioxide layer (52) that extends above the active region
`
`of the substrate (id., 7:43–47, Fig. 5(c)), a silicon dioxide layer (54) as a gate
`
`oxide (id.), a polycrystalline silicon layer (55) and molybdenum silicide layer
`
`(56) double-layer gate electrode (id., 7:51–56, 8:35–38, Fig. 5(c)), a molybdenum
`
`silicide layer (57[sic])4 as a wiring/interconnect level (id., 7:51–56, 8:67–9:5, Fig.
`
`5 (c)), and sources and drains (58) (id., 8:3–7, Fig. 5(c)). A representative
`
`illustration appears below.
`
`4 The label 57 is erroneous in Figure 5(c). (Ex. 1004, ¶80 n.1.) It should
`
`read “56.” (Id.) Layer 57 is a photoresist layer not shown in Figure 5(c). Element
`
`57 in Figure 5(c) corresponds to layer 56 of Figures 5(a) and 5(b). (Ex. 1010,
`
`7:53–56, Figs. 5(a)–5(c).)
`
`
`
`20
`
`
`
`
`
`B.
`
`The Lowrey-Noble combination renders claims 1, 4, 5, 8–12, 14,
`and 16 obvious
`Lowrey teaches every limitation of the c