Umted States Patent
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`Mandelman et al.
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`[19]
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`[11] Patent Number:
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`[45] Date of Patent:
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`US005521422A
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`5,521,422
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`May 28, 1996
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`[54] CORNER PROTECTED SHALLOW TRENCH
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`ISOLATION DEVICE
`Inventors: Jack A. Mandelman, Stormville, N.Y.;
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`Brian J. Machesney, Burlington, Vt.;
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`Hing Wong, Norwalk, Conn.; Michael
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`D. Armacost, Wallkill, N.Y.; Pai-Hung
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`Pan Boise m
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`International Business Machines
`Corporation, Annonk, N,Y,
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`[75]
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`[732 Assignee:
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`[211 Appl_ No; 343,709
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`Dem 2» 1994
`122-
`F1164
`[51j
`Int. (21.6 ..................................................... H01L 29/00
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`10 Claims, 5 Drawing Sheets
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`References Cited
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`U S PATENT Docm [ENTS
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`4,389,294
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`1/1991 Dhong et a1.
`4,988,637
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`3/1991 Kimura et al.
`4,998,161
`..
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`5,064,777
`11/1991 Dhong et al.
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`11/1992 Higuchi et al.
`5,160,988
`.
`257/301
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`12/1992 Dash et al.
`..
`5,173,439
`....__ 437/67
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`
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`10/1993 Ishii
`.......
`5,250,831
`257/305
`5,260,588
`11/1993 Ohta et al.
`257/523
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`
`
`
`1/1994 Manning
`5,275,965
`...... 437/67
`.. 437/21
`3/1994 Sundaresan .
`5,292,670
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`........................... .. 437/21
`3/1994 Strater et al.
`5,298,434
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`FOREIGN PATENT DOCUMENTS
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`
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`401537 12/1990 European Pat. Off.
`............... 257/301
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`4-56279
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`2/1992
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`Japan ..................................... 257/522
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`
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`OTHER PUBLICATIONS
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`T. Furukawa et al., “Process and Device Simulation of
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`
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`Trench Isolation Comer Parasitic Device”, Procedings of the
`
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`
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`Electrochemical Society Meeting, Oct. 9—14, 1988, pp. 1-2.
`
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`
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`A. Bryant et al., “The Current—Carrying Comer Inherent to
`Trench Isolation”, IEEE Electron Device Letters, vol. 14,
`
`
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`
`
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`
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`
`
`N°- 8» Aug 1991 PP- 412414-
`D. Foty et al., “Behavior of an NMOS Treneh—Isolated
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`
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`Comer Parasitic Devide at Low Temperature", Proceedings
`
`
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`
`
`
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`
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`
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`of the Electrochemical Society Meeting, Oct. 1989, pp. 1-2.
`
`
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`
`
`T. Ishijima et 31., “A Deep—Submicron Isolation Technology
`wim T—-shaped Oxide (TSO) Structure”, Proceedings of the
`
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`
`
`IEDM~ 1990: PP- fi57-2_6°-
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`1} C Fm‘! ct 31-: A Highly Manufacmmble Tr6mh_1S°1a-
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`
`
`
`
`
`tion Process for Deep Subnncron DRAMs”, Proceedings of
`
`
`
`
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`the 1EDM’ 1991 PP- 57‘5°-
`_
`J. F. Shepard, “Method to Reduce Loss of Isolation Trench
`
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`
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`Insulation”, IBM Technical Disclosure Bulletin, vol. 33, No.
`
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`10A, pp. 298-299, Mar. 1991.
`
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`C. W. Kaanta et 211, “Use of Easily Removable Sacrificial
`
`
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`Layer to Suppress Chemica1—Meehanical Overpolish Dam-
`age”, IBM Technical Disclosure Bulletin, vol. 34, No. 4B,
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`
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`pp. 343-344, Sep. 1991.
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`Primary Examz'ner—Sara W. Crane
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`Assistant Examiner——A1ice W. Tang
`Attamey, Agent, or Firm—James M. Leas
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`[57]
`ABSTRACT
`
`A semiconductor structure to prevent gate wrap-around and
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`comer parasitic leakage comprising a semiconductor sub-
`strate having a planar surface. A trench is located in the
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`substrate, the trench having a sidewall. An intersection of the
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`trench and the surface forms a corner. A dielectric lines the
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`sidewall of the trench. And, a corner dielectric co-aligned
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`with the comer extends a subrninimum dimension distance
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`over the Substrate from the comm
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`" 437/228
`437/52
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`TSMC Exhibit 1016
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`Page 1 of 9
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`U.S. Patent
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`May 28, 1996
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`Sheet 1 of 5
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`5,521,422
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`1 1
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`10
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`FIG. 1a
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`FIG. 1b
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`FIG. 1c
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`U.S. Patent
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`May 28, 1996
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`Sheet 2 of 5
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`U.S. Patent
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`May 28, 1996
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`U.S. Patent
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`May 28, 1996
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`Sheet 4 of 5
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`5,521,422
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`220
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`1121
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`‘°
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`12
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`FIG. 4a
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`May 28,1996
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`5,521,422
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`3.9...
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`5,521,422
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`1
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`CORNER PROTECTED SHALLOW TRENCH
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`ISOLATION DEVICE
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`FIELD OF THE INVENTION
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`This invention relates generally to semiconductor struc-
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`tures having a trench isolation. More particularly, it relates
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`to field elfect transistor devices adjacent a comer of a trench
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`used for isolation and methods of avoiding comer parasitic
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`leakage cement.
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`This comer leakage problem has commonly been con-
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`trolled with an increased threshold tailor implant dose, but
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`this can degrade device performance. Thus, alternate
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`schemes for controlling the comer are needed.
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`A paper, “A Deep-Subrnicron Isolation Technology with
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`T-shaped Oxide (TSO) Structure,” by T. Ishijima et. al.,
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`Proceedings of the IEDM, 1990, p. 257, addresses the
`problem of trench sidewall inversion. This paper teaches the
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`use of a pair of aligned photomasks to form a T-shaped oxide
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`adjacent the comet of an isolation trench and the use of a
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`channel stop boron implant along sidewalls of the trench.
`The structure moves the device away from the trench
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`sidewall and provides boron to raise the Vt along that
`sidewall. However, isolation is enlarged when photomask
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`alignment tolerances are included in this two-mask-and-
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`implant scheme, making this solution undesirable. Thus, an
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`improved means to control the comer parasitic is needed and
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`is provided by the following invention.
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`SUMMARY OF THE INVENTION
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`It is therefore an object of the present invention to avoid
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`comer leakage without degrading device performance.
`It is another object of this invention to avoid recessing the
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`isolation insulator adjacent the comer.
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`It is another object of this invention to avoid corner
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`leakage and protect the isolation insulator without using
`device area.
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`It is another object of this invention to provide a self-
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`aligned scheme for avoiding comer leakage and protecting
`the isolation insulator.
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`These and other objects of the invention are accomplished
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`by providing a semiconductor structure comprising a semi-
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`conductor substrate having a planar surface. A trench having
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`a sidewall is provided in the substrate. An intersection of the
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`trench and the surface forms a comer. A dielectric lines the
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`sidewall of the trench. And, a comer dielectric co-aligned
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`with the corner extends no more than a subminimum dimen-
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`sion distance over the substrate from the comer.
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`In one embodiment
`the comer dielectric is a spacer
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`self-aligned to the edge of the trench dielectric. In another
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`embodiment, the comer dielectric is a spacer self-aligned to
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`the edge of a window in insulator used as a mask to form the
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`trench.
`In a third embodiment,
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`position of the trench, but the spacer is then removed. When
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`the trench dielectric is later deposited, the trench dielectric
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`forms the comer dielectric in the space provided by the
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`removed spacer resulting in a unitary cap.
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`Methods of fabricating a semiconductor structure of the
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`invention comprise the steps of (a) providing a semiconduc-
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`tor substrate having a substantially planar surface; (b) form-
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`ing a coating on the substrate; (c) forming a window in the
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`coating, the window having an edge; ((1) forming a trench in
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`the substrate, the trench having a sidewall co-aligned to the
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`edge, an intersection of the trench and the surface forming
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`a comer; (e) lining the sidewall and the edge with insulator;
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`and (f) forming a material on the substrate adjacent the
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`comer, the material extending around the trench parallel to
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`the comer and extending no more than a subminimum
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`distance from the comer.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`The foregoing and other objects, features, and advantages
`of the invention will be apparent from the following detailed
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`description of the invention, as illustrated in the accompa-
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`nying drawings, in which:
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`BACKGROUND OF THE INVENTION
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`Contemporary CMOS technologies employ field eifect
`transistors that are adjacent or bounded by trenches. The
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`trenches may provide isolation (shallow trench isolation, or
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`STI) or they may provide a location for semiconductor
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`devices, such as capacitors. Parasitic leakage paths have
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`been found because of the proximity of a semiconductor
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`device to an edge or comer of a trench.
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`In one mechanism, described in a paper, “Process and
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`Device Simulation of Trench Isolation Comer Parasitic
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`Device,” by T. Furukawa and J. A. Mandelman, published in
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`the Proceedings of the Electrochemical Society Meeting,
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`Oct. 9-14, 1988, the parasitic leakage path results from an
`enhancement of the gate electric field near the trench corner.
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`The electric field is enhanced by the comer’s small radius of
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`curvature and the proximity of the gate conductor. Process-
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`ing can exacerbate the problem by sharpening the comer and
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`thinning the gate dielectric near the corner. In addition, in a
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`worst case scenario for comer field enhancement, the gate
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`conductor wraps around the trench comer. This happens
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`when the oxide fill in the isolation trench is recessed below
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`the silicon surface during oxide etches following its forrna-
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`tion.
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`As a result of the enhanced field, the comer has a lower
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`threshold voltage (Vt) than the planar portion of the device.
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`Thus, a parallel path for current conduction is formed.
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`However, for device widths used in contemporary technolo-
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`gies, the top planar portion of the device carries most of the
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`on-current. Trench comer conduction is a parasitic which
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`usually contributes appreciably only to sub-threshold leak-
`age. This parasitic leakage current along the comer is most
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`easily seen as a hump in the subthreshold current curve of a
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`narrow MOSFET.
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`As mentioned in a paper, “The Current-Carrying Comer
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`Inherent to Trench Isolation,” by Andres Bryant, W. Haem-
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`sch, S. Geissler, Jack Mandelman, D. Poindexter, and M.
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`Steger, published in the IEEE Electron Device Letters, Vol.
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`14, No. 8, Aug., 1993, the comer device can even dominate
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`on-currents in applications such as DRAM that require
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`narrow channel widths to achieve high density. This parallel
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`current-carrying comer device becomes the dominant MOS-
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`FET contributor to standby current in low standby power
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`logic applications and to leakage in DRAM cells. Further-
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`more, there exists concern that the enhanced electric fields
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`due to field crowding at the comer impact dielectric integ-
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`rity.
`A paper, “Behavior of an NMOS Trench-Isolated Corner
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`Parasitic Device at Low Temperature,” by D. Foty, J. Man-
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`delman, and T. Furukawa, published in the Proceedings of
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`the Electrochemical Society Meeting, October, 1989, sug-
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`gests that the comer parasitic device does not improve with
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`decreasing temperature nearly as much as the planar sub-
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`threshold slope. Thus, the corner parasitic device may be
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`more of a problem at low temperature than the planar device.
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`Page 7 of 9
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`Page 7 of 9
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`

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`3
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`FIGS. 1a—1e are cross sectional views showing the struc-
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`ture at several steps in the process for making a sen1icon-
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`ductor structure of a first embodiment of the present inven-
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`tion;
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`FIG. 2 is a cross sectional view showing a structure
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`illustrating how gate wrap-around occurs with conventional
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`processing;
`FIG. 3a—3e are cross-sectional views showing the struc-
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`ture at several steps in the process for making a semicon-
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`ductor structure of the second embodiment of the present
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`invention;
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`FIG. 4a—4c cross-sectional views showing the structure at
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`several steps in the process for making a semiconductor
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`structure of the third embodiment of the present invention;
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`FIG. 5 is cross-sectional view showing the structure of a
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`MOSFET adjacent an isolation of the present invention;
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`FIG. 6a is a simulation plot showing equipotential lines
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`for a MOSFET adjacent an isolation with conventional
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`geometry; and
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`FIG. 6b is a simulation plot showing equipotential lines
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`for a MOSFET adjacent an isolation with the geometry of
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`the present invention.
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`DETAILED DESCRIPTION OF THE
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`INVENTION
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`The present invention provides a self-aligned structure
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`over the comer that eliminates a recess formed in an adjacent
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`insulator lined trench. Such trenches include shallow trench
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`isolation (STI) and deep trench capacitor. STI and processes
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`for forming STI are described in commonly assigned U.S.
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`Pat. No. 5,173,439, by Dash et. al., incorporated herein by
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`reference. By eliminating the recess in the insulator, the gate
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`wrap-around problem mentioned hereinabove is eliminated.
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`The structure also offsets the gate conductor from the trench
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`comer, further reducing the comer electric field. Several
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`embodiments are taught,
`including structures that avoid
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`narrowing the channel. The modified gate conductor geom-
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`etry results in an electric field at the trench comer that is
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`actually lower than the field at the top planar region (see
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`FIGS. 6a—6b). The result is a device which is free of the
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`above mentioned high corner electric field parasitic elfects.
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`In addition, applicants have found that, as a result of
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`increased corner field where the gate conductor overlaps the
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`drain dilfusion, gate induced drain leakage (GIDL) is sig-
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`nificantly increased. By eliminating the high field at the
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`the present invention also eliminates this GIDL
`corner,
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`concern.
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`In one embodiment, illustrated in FIGS. 1a—1e, a comer
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`dielectric is provided self-aligned to raised STI. The corner
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`dielectric is a spacer that protects the S11 comer from attack
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`by subsequent etches and that spaces a later formed FET
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`away from the corner.
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`In the process, silicon substrate 10 is provided with a pad
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`oxide 11 and nitride surface coating 12 as illustrated in FIG.
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`1a. Window 13 with nearly vertical sidewall 14 is photo-
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`lithographically defined in surface coating 12 and oxide 11
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`as shown in FIG. 1b. Then trench 16 is etched, defined by
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`window 13 as illustrated in FIG. 1c.
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`Trench 16 and window 13 are then filled with insulator 18.
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`Insulator 18 is then polished, stopping on surface coating 12
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`as illustrated in FIG. 1d. Then surface coating 12 is removed,
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`leaving insulator 18 with nearly vertical sidewalls 20
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`extending above the surface 21 of silicon substrate 10.
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`Spacer 22 is then provided self-aligned to sidewall 20 of
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`insulator 18 by the standard process of depositing a spacer
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`Page 8 of 9
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`5,521,422
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`4
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`insulator having a desired thickness and directional etching
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`to selectively remove the spacer insulator from horizontal
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`surfaces. The spacer insulator can be a material such as CVD
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`oxide, oxidized polysilicon, TEOS, silicon nitride, and
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`boron nitride. Spacer 22 protects the STI adjacent corner 24
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`during subsequent etches, preventing divoting and gate
`wrap-around. Preferably, spacer 22 has a dimension that is
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`less than the minimum photolithographic dimension capable
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`of being formed by a particular process technology.
`In a preferred embodiment, at least a portion of spacer 22
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`remains in place after subsequent etches, thereby also mov-
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`ing the gate controlled channel region of a later formed FET
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`away from corner 24. Thus, high field effects including the
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`corner parasitic FET and GIDL at the drain dilfusion are
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`eliminated. No additional photomasking is required for the
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`formation of spacers 22, a significant advantage over the
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`prior art.
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`Several experiments have been performed to confirm that
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`the RIE proposed for the spacer formation is not detrimental
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`to device characteristics. Results indicate that flatband and
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`breakdown characteristics of silicon on which spacers have
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`been formed are not degraded.
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`FIG. 2 illustrates a mechanism responsible for gate wrap-
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`around and shows how the present invention eliminates this
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`problem. Divot 30 in insulator 18 in trench 16 adjacent
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`corner 24 arises during isotropic etches used in standard
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`semiconductor processing after trench 16 is filled with
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`insulator 18. Divot 30 is formed adjacent corner 24 as a
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`result of the vertical and horizontal attack by etch ant on
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`insulator at corner 24. By providing a sufficiently thick
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`spacer 22 over corner 24 (FIG. 1e), etchant cannot access
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`and form a recess or divot in insulator 18.
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`In a second embodiment, illustrated in FIGS. 3a—3e, a
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`comer dielectric is also provided self-aligned to raised STI.
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`The comer dielectric is again a spacer that protects the STI
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`corner from attack by subsequent etches and that spaces a
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`later formed FET away from the corner. But in this embodi-
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`ment the spacer is formed before the STI, it is inverted
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`compared to the spacer of the first embodiment, and it is
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`formed within the minimum dimension space of the isola-
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`tion. Thus, unlike the first embodiment presented herein-
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`above, in this embodiment no device area is consumed by
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`the corner dielectric, a significant advantage. Furthermore,
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`in this embodiment, the RIE etching of the spacer does not
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`elfect the device region.
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`In the process, silicon substrate 10 is again provided with
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`nitride surface coating 12. Window 13 with nearly vertical
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`sidewall 14 is again photolithographically defined in surface
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`coating 12 as shown in FIG. 3a. In the next step, spacer 22a
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`is formed along sidewall 14 of coating 12. Then trench 16 is
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`etched, defined by spacer 22a in window 13 as illustrated in
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`FIG. 1c. Then, as illustrated in FIG. 1d,
`trench 16 and
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`window 13 are filled with insulator 18. Insulator 18 is then
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`polished, stopping on surface coating 12. Then surface
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`coating 12 is removed, leaving insulator 18 with spacer 22a
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`extending above the surface 21 of silicon substrate 10.
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`As with the first embodiment, spacer 22a protects the STI
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`adjacent comer 24 during subsequent etches, preventing
`divoting and gate wrap-around. Similarly, at least a portion
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`of spacer 22a remains in place after subsequent etch steps,
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`moving a later formed FET away from comer 24. And no
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`additional photomasking is required for the formation of
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`spacer 22a. This embodiment has a significant advantage
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`over the first embodiment
`in that spacer 22a is within
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`window 13, which can have a minimum dimension. Thus,
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`spacer 22a does not take up device area, an advantage
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`10
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`Page 8 of 9
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`

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`duction and the GIDL concerns due to high comer fields are
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`eliminated.
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`While several embodiments of the invention, together
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`with modifications thereof, have been described in detail
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`herein and illustrated in the accompanying drawings, it will
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`be evident that various further modifications are possible
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`without departing from the scope of the invention. For
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`example, the trench need not be filled with insulator. The
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`insulator can be a thin lining along a sidewall or along the
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`top portion of the sidewall. The examples given are intended
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`only to be illustrative rather than exclusive and nothing in
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`the above specification is intended to limit the invention
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`more narrowly than the appended claims.
`What is claimed is:
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`1. A semiconductor structure comprising:
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`a semiconductor substrate having a planar surface;
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`a trench in said substrate, said trench having a sidewall, an
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`intersection of said trench and said surface forming a
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`corner;
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`a comer dielectric co-aligned with said corner and extend-
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`ing over said surface; and
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`a field effect transistor having a channel having a current
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`path extending parallel
`to said corner, said channel
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`being spaced from said comer by said comer dielectric.
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`2. A semiconductor structure as recited in claim 1,
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`wherein said comer dielectric comprises a spacer.
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`3. A semiconductor structure as recited in claim 1 wherein
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`said corner dielectric comprises one of silicon dioxide,
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`silicon nitride, and boron nitride.
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`4. A semiconductor structure as recited in claim 1 wherein
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`said trench is a shallow trench isolation.
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`5. A semiconductor structure as recited in claim 1, firrther
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`comprising an insulator in said trench, wherein said insula-
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`tor fills said trench.
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`6. A semiconductor structure as recited in claim 1, further
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`comprising an insulator in said trench, wherein said comer
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`dielectric and said insulator comprise the same material.
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`7. A semiconductor structure as recited in claim 6,
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`wherein said comer dielectric and said trench dielectric are
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`a unitary structure.
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`8. A semiconductor structure as recited in claim 1, said
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`charmel being defined by a gate, said gate being spaced from
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`said comer by said comer dielectric.
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`9. A semiconductor structure as recited in claim 8, said
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`corner dielectric comprising a spacer.
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`10. A semiconductor structure as recited in claim 9,
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`further comprising an insulator in said trench, wherein said
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`insulator fills said trench.
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`*
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`6
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`*
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`*
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`*
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`*
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`5,521,422
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`5
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`particularly for narrow devices such as DRAM cells. Trench
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`16 can have a dimension that is a subminimum dimension.
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`In a third embodiment,
`illustrated in FIGS. 4a—4c, a
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`unitary structure having a comer dielectric co-aligned with
`the corner and extending a subrninimum dimension distance
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`over the substrate from the comer is provided. In this case
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`corner dielectric 22c is not itself a spacer but it fills the space
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`left when previously formed spacer 22a is removed. This
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`embodiment dilfers from the second embodiment in that
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`spacer 22a of FIG. 3c is removed after trench 16 is etched
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`as illustrated in FIG. 4b. Then, insulator 18a is deposited to
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`fill both trench 16 and the space 22b left vacant by removed
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`spacer 22a. After polishing, coating 12 is removed leaving
`a unitary raised STI structure having a subrninimum dimen-
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`sion corner dielectric 22c, as illustrated in FIG. 4c. In this
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`unitary structur, corner dielectric 22c and insulator 18a are
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`formed of the same material. As with the second embodi-
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`ment, comer dielectric 22c does not take up device area.
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`Trench 16 can have a subminimum dimension while the
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`isolation as a whole 32 covers no more than a minimum
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`dimension. FIG. 4c also illustrates the formation of thermal
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`oxide layer 34 before deposition of insulator 18a, as is well
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`known in the art.
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`As used in this application the phrase, “a corner dielectric
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`co-aligned with the comer” means that the comer dielectric
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`is aligned to an original edge to which the corner is also
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`aligned (or either or both are aligned to an edge, such as a
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`spacer edge, derived from the original edge). Similarly, the
`phrase “a trench having a sidewall co-aligned to an edge,”
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`means that the sidewall is aligned to an original edge to
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`which the edge is also aligned (or either or both are aligned
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`to an edge, such as a spacer edge, derived from the original
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`edge). Separate photolithography steps are avoided by using
`co-aligned structures; both structures are formed from a
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`single masking step aligned to the same mask edge. Little or
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`no additional surface area is consumed compared to pro-
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`cesses requiring separate photolithography steps for both
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`structures.
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`With any of the above embodiments, a MOSFET can then
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`formed bounded by a comer dielectric rather than the comer
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`and sidewall of the STI. As illustrated in FIG. 5, gate
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`dielectric 38 is formed by conventional processing. Gate
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`conductor 40 is then deposited and photolithographically
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`defined. Gate conductor 40 is spaced from comer 24 by
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`comer dielectric 22, 22a, or 22c. Thus, the electric field in
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`the corner region is significantly reduced.
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`Device modeling, illustrated in FIGS. 6a—6b, shows that
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`the modified geometry described here results in a drastic
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`reduction of the trench comer electric field. Parasitic con-
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`10
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`20
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`25
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`35
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`40
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`45
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`Page 9 of 9
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`Page 9 of 9