IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
`US005733812A
`[11] Patent Number:
`[45] Date of Patent:
`
`5, 733, 812
`Mar. 31, 199S
`
`United States Patent
`Ueda et al.
`
`[19]
`
`[54] SEMICONDUCTOR DEVICE WITH A FIELD-
`EFFECT TRANSISTOR HAVING A LOWER
`RESISTANCE IMPURITY DIFFUSION
`LAYER, AND METHOD OF
`MANUFACTURING THE SAME
`
`[75]
`
`Inventors: Tetsuya Ueda; Takashi Uehara;
`Kousaku Yano; Satoshi Ueda, all of
`Osaka, Japan
`
`[73] Assignee: Matsushita Electric Industrial Co. ,
`Ltd. , Osaka, Japan
`
`[21] Appl. No. : 571, 131
`Dec, 12, 1995
`
`[22] Filed:
`
`Related U. S. Application Data
`
`[JP]
`[JP]
`
`of Ser. No. 340, 341, Nov. 14, 1994,
`
`[63] Continuation-in-part
`abandoned.
`Foreign Application Priority Data
`[30]
`Japan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2S4820
`Nov. 15, 1993
`Japan . . . , . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . 7-278546
`Oct. 26, 1995
`[51] Int. CL
`H01L 21/265
`[52] U. S. Cl. . . . . . . . . . . . . . . . . . . . . . . . . . . 438/289; 438/297; 438/301;
`438/586; 438/691
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437/40 R, 40 GS,
`[58] Field of Search
`437/40 RG, 41 R, 41 GS, 44, 45, 187,
`979. 228 POL, 29, 228 PL; 156/636. 1,
`645. 1; 216/52; 148/DIG. 163; 438/289,
`297, 301, 586, 691
`
`[56]
`
`4/87, 660
`4, 330, 931
`4/84, 761
`
`References Cited
`U. S. PATENT DOCUMENTS
`. .
`9/1981 Nicholas
`5/1982 Liu
`4/1986 Wu . . . . . . . . . . .
`
`. . 437/41 GS
`29/571
`. . . . . 437/41 R
`
`13;13
`
`13
`
`12b (, 13b
`
`13a 12c
`
`13b
`
`12o
`
`j
`
`/
`
`4, 713, 356
`4, 727, 043
`4, 780, 429
`5/09, 816
`5/45/10
`5/89, 443
`5, 340, 370
`5, 346/84
`5, 422/89
`5, 447, 874
`
`12/19S7
`2/1988
`10/19S8
`5/1993
`9/1993
`2/1994
`8/1994
`9/1994
`6/1995
`9/1995
`
`Matsumoto et al. . . .
`Roche et al. . . . . . . . . . . .
`Yu et al. . . . . . . . . . . . . . . . .
`. . . . . . . . . . . . .
`Nishigoori
`Jaug . . . . . . . . . . . . . . . . . . . . . . .
`Cadien et al.
`Nasr et al. . . . . . . . . , . . . .
`Pierce et al. . . . . . . . . . . .
`Grivna et al. . . . . . . . . . .
`
`. . . . . . . . . . . . 437/41
`. . . . . . . , . . . 437/29
`. . . . . . . . . . . 437/41
`. . . . . . . . . 1 56/636
`. . . . . . . . . 257/382
`. . . . 437/40 GS
`. . . . . . . . . . . 51/308
`. . . . . . . . . 1 56/636
`. . . . . . . . . . . 437/32
`. . . . . 437/40 GS
`
`FOREIGN P~ DOCUMENI'S
`Primary Examiner — Brian Dutton
`Attorney, Agent, or Finn — McDermott, Will k Emery
`ABSTRACT
`[57]
`
`5-13432
`
`1/1993
`
`Japan .
`
`is formed an isolation which
`an active
`There
`surrounds
`region of a semiconductor
`substrate. Formed over the active
`region and on the isolation, respectively. are a gate electrode
`thereof.
`on both sides
`interconnections
`two gate
`and
`are
`Between the gate electrode and the gate interconnections
`each of which
`is smaller
`located two first interspaces
`in
`width than a specified value and a second interspace which
`is larger
`the specified value and interposed
`than
`in width
`the two first interspaces. In forming side walls on
`between
`both side faces of the gate electrode and gate interconnec-
`film on the substrate,
`the
`tions by depositing an insulating
`the
`film.
`insulating
`interspaces
`are buried with
`first
`fol-
`Thereafter. a metal film is deposited on the substrate,
`lowed by chemical mechanical polishing
`the gate
`till
`and side walls become
`electrode, gate
`interconnections,
`from a
`electrodes
`exposed. By the process, withdrawn
`region for contact with
`is
`the active region
`source/drain
`electrodes
`formed by self alignment, while
`the withdrawn
`from the gate electrode and gate interconnec-
`are insulated
`tions by the side walls.
`
`11 Claims, 27 Drawing Sheets
`
`12a
`
`12b
`
`15
`
`4c
`
`15
`
`XXII]b
`
`4c
`
`12c
`
`Rgpl
`R
`1
`
`TSMC Exhibit 1014
`
`Page 1 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 1 of 27
`
`5, 733, 812
`
`Rac
`
`(SIDE WALL)5
`
`(GATE
`l, ELE( TRQDE) (LOCQS FILM)
`2
`
`Fig 1
`{a)
`{ IMPURI TY
`DI FFUSI ON L AY E R )
`Fig. 1
`
`6
`
`Fig. l
`
`Bb
`
`6a
`
`3(GATE OXIDE FILM)
`
`(SILI CON
`~ SUBSTRATE)
`
`7X { W/TiN/Ti FILM)
`
`7(MULTI-LAYER METAL FILM)
`
`( CONTAC T HOLE )
`
`8{ I N T ER FAC E
`REGION)
`
`(L OW- TEMPERATURE
`("0 OXIDE FILM)
`
`Fig. 1
`
`(cI)
`
`Fig1
`
`{e)
`
`(W PLUG ) 12
`
`FI RST-LAYER
`'l3 METAL
`IN T ERCQNN ECTION
`
`Page 2 of 41
`
`

`
`Mar. 31, 1998
`
`Sheet 2 of 27
`
`5, 733, S12
`
`(W LAYER ) 23
`
`22 (Ti N LAYER)
`
`l
`
`I
`
`21(Ti LAYER)
`
`Fi g. 3
`
`Roc
`/
`
`Rcos
`
`Rcog
`
`I
`
`I
`
`l
`I
`I
`/
`
`/
`I
`/
`
`/
`
`/
`
`Page 3 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 3 of 27
`
`5, 733, S12
`
`('A)I M NQILVI @30 OHVGNViS
`lD 4 g CD CD
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`
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`Cv
`(~HO)
`3A lych 33NVLS IS38 J. 33H5
`
`Page 4 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 4 of 27
`
`5, 733, S12
`
`~o
`
`O
`
`cv
`
`LA
`cD
`ll
`II
`ii) UJ
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`3(i lych 33NVl'51538 l3VJ. N03
`
`Page 5 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 5 of 27
`
`5, 733, S12
`
`Page 6 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 6 of 27
`
`5, 733, S12
`
`F ig. 7
`(a)
`
`Fig. 7
`(b)
`
`FILM(cid:30))
`
`Roc~
`g b(SI LI CIDE
`CQ(POLYSILICON FILM)
`
`I
`
`5
`
`Bb
`
`Ba
`
`51( SECOND POLY SILI CON INTERCONNECTI ON)
`
`Page 7 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 7 of 27
`
`5, 733, 812
`
`Fi g. 8
`
`PMOSFET
`
`PMOSFET
`
`INPUT
`
`QUT P UT
`
`~MOSFET
`
`'h MOSF ET
`
`PMOSFET
`
`71
`
`72
`
`'hMOSFET
`
`PMOSFE T
`
`WMOSFET
`
`5't
`(LOCAL INTERCONNECTI ON)
`
`Page 8 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 8 of 27
`
`5, 733, 812
`
`4C
`
`(GATE
`INTERCONNE
`-CTION )
`
`Roc
`
`2
`
`.
`
`1
`
`Fig. 10
`h)
`
`Fig. 10
`(&)
`
`Fig 10
`(c)
`
`Fig. 10
`(d)
`
`Fig. 10
`(e)
`
`4
`
`7
`
`11/
`
`12
`
`13
`
`Page 9 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 9 of 27
`
`5, 733, 812
`
`F i g. 1]
`
`Roc
`
`/
`/
`
`/'
`/
`/
`
`/
`/
`/
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`/
`/
`
`/
`
`/
`
`/ l
`
`Rcog
`
`Page 10 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 10 of 27
`
`5, 733, S12
`
`F ig. 12(cj)
`
`F ig. 12(b)
`
`I4Q(HTQ FILM)
`
`(TRENCH)
`
`l4
`( BURIED OXIDE FILM)
`
`300nm
`
`F ig. 12(c)
`
`Fig. 12(d)
`
`3Q
`
`Fig. 12 (e)
`
`gb
`
`BQ
`
`E
`
`/7
`
`F ig. 12(f)
`
`7x
`
`Page 11 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 11 of 27
`
`5, 733, S12
`
`q pq (ELECTRODE i
`iFOR GATE J
`
`(ELECT RODE
`~0~(FOR SUBSTRATE)
`
`&MOSFET
`
`)op (ELECTRODE )
`lFOM DRAIN)
`
`(FOR SOURCE~
`
`Page 12 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 12 of 27
`
`5, 733, 812
`
`Fig. 14
`(a)
`
`Rac
`
`Fig. 14
`(b)
`
`81
`
`81
`
`Ret
`
`Flg, g( )
`
`3a
`
`3b
`
`3~
`
`3a
`
`3b
`
`FigV
`
`(d
`
`Ba
`
`Fig. '14
`(e)
`
`Page 13 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 13 of 27
`
`5, 733, S12
`
`F ig. 'l5
`(a)
`
`Fig. 'l5
`(b)
`Rcos
`
`Rcog
`
`10
`
`Fig. 'l5
`(c)
`13
`
`Page 14 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 14 of 27
`
`5, 733, 812
`
`Fi g. 16
`
`&o(3a) 4b(3b)
`
`L (3)
`
`Page 15 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 15 of 27
`
`5, 733, S12
`
`Rac
`
`F ig. 17 (cL)
`
`F i g. l7 (b)
`
`81
`
`Ret
`
`F ig. 'l7 (c)
`
`hv
`
`F ig. l7 (d)
`
`4o
`
`Ab
`
`Page 16 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 16 of 27
`
`5, 733, 812
`
`6b
`
`6G
`
`3
`
`30a(Ti FIm)
`
`30 (T I TANIUM 5IL I CIDE
`LAYER )
`
`10
`
`12
`
`Fi g. 'le(cIj
`PRIOR ART
`
`F ig. &8(b)
`PRIOR ART
`
`Fig. 38 (c)
`PRIOR ART
`
`F iq. 18(dj
`PR ION AR T
`
`Fig. 18(e ~
`PRIOR ART
`
`Fig. 18 (f )
`PRIOR ART
`
`Page 17 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 17 of 27
`
`5, 733, 812
`
`F ig. 19 (a)
`
`4c Rgp2
`
`4
`
`Rgp2
`
`I
`
`Fig. 19(b)
`
`2[
`
`6
`
`3 22
`
`Fig. 19(c)
`
`F ig. l9(d)
`
`F ig19(c)
`
`)3a
`
`12Q
`
`12b
`
`13b
`
`2
`
`7x
`
`10
`
`Page 18 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 1S of 27
`
`5, 733, 812
`
`Fig. 20
`
`Rgpl
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/
`
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`I
`I
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`
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`I
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`
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`
`Rgp2
`
`I
`I
`i
`t
`
`--2
`
`4,
`
`Page 19 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 19 of 27
`
`5, 733, S12
`
`Fig. Z1
`
`Rgpl
`
`Rgp2
`
`Rgp2
`
`I, c
`
`Page 20 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 20 of 27
`
`5, 733, S12
`
`Fig. 22
`
`12Q
`
`7b
`
`4c
`
`33Xlc
`
`12c
`
`Rgpl
`
`XXEc
`
`Page 21 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 21 of 27
`
`5, 733, 812
`
`Fig 23(c)
`
`12Q
`
`4c
`
`15
`
`7b
`
`12b 4c
`13
`
`10
`7Q
`
`F ig. 23(b)
`
`2J
`7a
`
`4c
`
`6 22
`15
`4
`I
`
`2
`
`7b
`
`F i g. 23 (c )
`
`13
`
`12c
`
`Rgpl
`
`Rgpl
`
`2
`
`Page 22 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 22 of 27
`
`5, 733, S12
`
`Vdd
`
`TRp3
`
`TRp2
`
`TRp1
`
`I N PUT
`SI GNAL
`
`OUTPUT
`SIGNAL
`
`TRn3
`
`TRn2
`
`TRnl
`
`Vss
`
`Page 23 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 23 of 27
`
`5, 733, 812
`
`Fi g. 25
`
`TRp3
`
`TRp2
`
`Rgpl
`
`TR pl
`
`4c
`
`Rgp2
`
`Rgpl
`
`4c
`
`Rgp2
`
`Rgpl
`
`Rgpl
`
`TRn3
`
`TRn2
`
`TRnl
`
`Page 24 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 24 of 27
`
`5, 733, S12
`
`16a Rgpl
`
`Rgpl
`
`Rde
`
`I
`
`I
`
`Rgp2
`
`Rde
`
`Rgpl
`
`Page 25 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 25 of 27
`
`5, 733, 812
`
`F ig. 27
`TRp3 TRp2
`
`TRpl
`
`7b
`
`7c
`
`Rde
`12c
`
`Rgpl
`
`4c
`
`TRn3
`
`'}
`TRn2
`
`TRnl
`
`12Q
`
`4c
`
`7c
`
`7c
`12d
`
`Rde
`
`Rgpl
`
`15
`
`Rgpl
`
`Page 26 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 26 of 27
`
`5, 733, S12
`
`F ig. 28
`
`TRp3
`
`TRp2
`
`TRp1
`
`13b
`
`7b
`
`15
`
`Rde
`
`12c
`
`13c
`
`4c
`
`Rde
`
`13d
`
`12d
`
`7c
`
`13Q
`
`-12a
`
`TRn3
`
`TRn2
`
`TRn1
`
`Page 27 of 41
`
`

`
`U. S. Patent
`
`Mar. 31, 1998
`
`Sheet 27 of 27
`
`5, 733, S12
`
`Fig 29(a)
`
`5a
`
`17b
`
`17a 4a
`
`5a
`
`17b
`5a
`
`Fig. 29(b)
`
`ieb
`
`22
`
`18b
`
`15a
`
`F ig. 29(c)
`
`7x
`
`Fig 29(d)
`
`7cl
`
`7
`
`7c
`
`7 b
`
`7d
`
`Fig 29(| )
`
`1&a "" 1pc
`
`12b
`
`13b
`
`Page 28 of 41
`
`

`
`5, 733. 812
`
`1
`SEMICONDUCTOR DEVICE WITH A FIELD-
`EFFECT TRANSISTOR HAVING A LOWER
`RESISTANCE IMPURITY DIFFUSION
`LAYER, AND METHOD OF
`MANUFACTURING THE SAME
`
`of application
`is a Continuation-In-Part
`This application
`Ser. No. 08/340341, filed Nov. 14, 1994 now abandoned.
`
`BACKGROUND OF THE INVENTION
`relates to a semiconductor appara-
`The present invention
`tus in which a field-effect transistor (FEI') is disposed and to
`it
`a method of manufacturing
`the same. More parficularly,
`relates to a method of lowering the resistance of an impurity
`layer in the FET.
`diffusion
`With the increasing miniaturizaiion of a large-scale semi-
`integrated circuit in recent years. a MISFEI' has
`conductor
`the resistances of its
`in size by lowering
`been reduced
`layer and gate interconnection. To lower
`impurity diffusion
`the resistance of an impurity difFusion
`layer, there has been
`for actual use, which is a
`developed "salicide" technology
`method wherein a metal with high melting point such as Ti
`in a silicon
`layer
`diffusion
`is deposited on the impurity
`the vicinity of the Si-Ti interface
`is
`substrate and
`then
`the mutual diffusion of Si and Ti between
`silicidized through
`the resulting Ti film,
`thereby
`the silicon substrate
`and
`lowering the resistance value of the impurity difFusion layer.
`there has been introduced a method
`On the other hand,
`in a contact hole by selective
`is buried
`wherein
`tungsten
`is used to fill up the contact hole,
`CVD or blanket tungsten
`since the aspect ratio of the contact hole has been increased
`the intercon-
`the contact area between
`in order to minimize
`nection and silicon.
`is a
`There has also been proposed a method, which
`in "A NOVEL
`combination of the above two technologies,
`DOUBLE-SELF-ALIGNED TiS12/TiN CONTACT WITH
`SELECTIVE CVD W PLUG FOR SUBMICRON DEVICE
`(IEEE. VLSI
`AND INTFRCONNECI' APPLICATIONS
`Symp 5 — 5 p. 41, 1991)" by Martin S. Wang et al.
`in the
`Below, the composite salicide method disclosed
`above document will be described with reference to FIGS.
`the transition of the cross
`18(a) to 18(f), which
`illustrate
`sectional structure of a silicon substrate during
`the process
`of manufacturing
`a semiconductor
`apparatus.
`FIG. 18(a) shows a MOS transistor of LDD structure
`that
`In the drawing, 1 designates a
`has been formed previously.
`silicon substrate, 2 designates
`formed by a
`an isolation
`LOCOS method, 3 designates a gate oxide film, 4 designates
`a polysilicon electrode, 5 designates a side wall, and 6
`layer (the impurity diffu-
`an impurity diffusion
`designates
`source/drain 6a and
`sion layer includes a low-concentration
`source/drain 6b). The manufacturing
`a high-concentration
`is identical with a conventional method of manu-
`method
`in FIG.
`facturing a CMOS device, up to the stage shown
`the doping with As, P, and B and the
`18(a). Moreova;
`thermal treatment have been conducted in accor-
`subsequent
`dance with the characteristics of a p-channel MOS transistor.
`Next, as shown in FIG. . 18(b), a Ti thin fihn 30 for a salicide
`for sili-
`followed by annealing
`is deposited by sputtering,
`cidization as shown in FIG. 18(c). After that, the titanium on
`the oxide film is removed by wet etching so as to implant Nz.
`layer) 30 is formed
`Subsequently, TiSi„(silicidized titanium
`only on the impurity difFusion layers 6 and gate polysilicon
`4. After a BPSG film 10 was deposited, a contact hole 11 is
`in a desired position of the BPSG film 10 by
`formed
`and by dry etching (using a gas containing
`photolithography
`
`CHF2+02 as its main component). as shown in FIG. 18(d).
`in FIG. 18(e), a W (tungsten) plug 12 is
`Next. as shown
`deposited by selective CVD. Then, after depositing a film
`consisting of TiN/AISiCu/fi by sputtering. as shown in FIG.
`to form a metal inter-
`fihn is patterned
`18(/), the resulting
`connection 13. The above process provides a semiconductor
`apparatus having the MOS transistor with the salicide struc-
`ture and the W plug formed by selective CVD.
`semiconductor apparatus with
`the conventional
`However,
`the structure described above has the following disadvan-
`tages:
`(I) Although
`the formation of a silicide film 7b requires
`the metal with high melting point and
`the reaction between
`layer 6 is
`silicon, if the impurity diffusion
`the underlying
`shallow, it becomes difficult to form a junction between the
`metal with high melting point and silicon. However, since a
`future device requires the formation of an impurity diffusion
`layer as shallow as possible, it becomes difncult to form an
`is not
`the salicide
`technology
`efFective junction, so that
`necessarily compatible with a future device.
`to a gas
`(2) Since the silicide layer shows poor immunity
`in etching for forming
`containing CF as its main component
`a contact hole, defects such as a pin hole are easily caused.
`which may incur an increase in the resistance of the impurity
`diffusio layer.
`(3) In a transistor with a shallow junction formed between
`the metal with high melting point and silicon, over-etching
`for surely forming each contact hole cannot be performed
`in etching for forming a contact hole in the
`satisfactorily
`the reliability
`shallow junction therebetween. Consequently,
`of an interconnection may be impaired.
`(4) A thermal treatment at 650' C. or a higher temperature
`in order to lower the resistance of the silicide
`is required
`the electrical characteristics of the
`layer. Consequently,
`transistor may be impaired.
`(5) The silicide layer hardly serves as a satisfactory barrier
`metal layer in forming the W plug by selective CVD. so that
`junction leakage
`conditions for preventing
`its manufacturing
`become more stringent.
`(6) With the structure shown in FIG. 18(f). the degree of
`the BPSG film 10 is not
`planarization of the base underlying
`satisfactory.
`
`SUMMARY OF THE INVENTION
`the above object, a basic method of rnanufac-
`To attain
`to the present
`apparatus according
`turing a semiconductor
`comprises: a first step of forming an isolation
`invention
`an active region of a semiconductor
`sub-
`which surrounds
`strate in which a MISFET is to be formed; a second step of
`for controlling a threshold of the
`an impurity
`introducing
`above MISFET into the above active region; a third step of
`serv-
`interconnections
`forming at least three first conductive
`ing as a gate electrode of the above MISFET over the above
`active region and serving as gate interconnections of the
`above MISFET on the isolation on both sides of the above
`active region such that an interspace between the above gate
`is
`electrode and each of the above gate interconnections
`composed of at least two first interspaces. each of which is
`than a specified value T, and of a second
`smaller in width
`is
`the above first interspaces, which
`interspace between
`larger in width than the above specified value T; a fourth step
`of depositing an insulating
`film over the above first conduc-
`and the above interspaces; a fifth step
`tive interconnections
`of performing anisotropic etching with respect to the above
`film so as to form side walls composed of remain-
`insulating
`film on both side faces
`ing portions of the above insulating
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`
`3
`interconnections with the above
`of the above first conductive
`film buried in the above first interspaces, while
`insulating
`the active region on both sides of the
`partially exposing
`in the above second
`interconnections
`above first conductive
`two impurity diffusio
`interspace; a sixth step of forming
`region of the above MISFE1"
`layers serving as a source/drain
`in those regions of the active region which are located on
`step of
`both sides of the above gate electrode; a seventh
`depositing, after the above sixth step, a metal film over the
`step of
`surface of the substrate;
`and an eighth
`entire
`performing, after the above seventh step. chemical rnechani-
`the above metal film, the
`cal polishing for partially removing
`and the above side
`interconnections.
`above first conductive
`the chemical mechanical
`walls such that, in a plane when
`the above gate electrode, the above
`is completed,
`pohshing
`and the above metal film are partially
`gate interconnections,
`left and two remaining portions of the above metal film on
`layers, which are
`the above respective
`impurity diffusion
`surrounded by the above side walls and the above insulating
`form second conductive
`in the first interspaces,
`film buried
`isolated from each other.
`electrically
`interconnections
`interconnections
`the second conductive
`By the method.
`the active region function as withdrawn
`for contact with
`region of the MISFEI'.
`electrodes Rom the source/drain
`electrodes are electri-
`Moreover. the individual withdrawn
`cally isolated from each other by the insulating
`fihn buried
`the
`interspaces, while
`individual withdrawn
`the first
`in
`electrodes and the first conductive
`interconnections
`(gate
`are isolated from each
`electrode and gate interconnections)
`elec-
`other by the side walls. Consequently,
`the withdrawn
`trodes for contact with the active region. which occupy a
`so that inter-
`large area. can be formed by self alignment,
`apparatus can be minia-
`in the semiconductor
`connections
`turized without incurring a defective connection between the
`eleclrodes and the active region.
`In the above basic method of manufacturing
`a semicon-
`ductor apparatus, a LOCOS film can be formed in the above
`first step of forming an isolation. Alternatively.
`the isolation
`trench structure can be formed by forming a trench
`with
`the above active region in the above
`portion surrounding
`the above trench
`semiconductor
`substrate and then burying
`portion.
`a semicon-
`In the above basic method of manufacturing
`interconnections
`can
`the first conductive
`ductor apparatus,
`be formed from a polysilicon film in the above third step.
`to utilize general-
`it becomes possible
`By the method,
`the manu-
`purpose polysilicon process, thereby facilitating
`facturing of semiconductor
`and reducing manu-
`apparatus
`facturing cost.
`In the above basic method of manufacturing
`a semicon-
`the first conductive
`interconnections
`can
`ductor apparatus,
`film consisting of a lower
`from a two-layer
`be formed
`layer in the above
`layer and an upper insulating
`conductive
`third step.
`in the step of forming
`the side walls, a
`By the method,
`damage caused by anisotropic etching to the first conductive
`can surely be prevented.
`interconnections
`The above basic method of manufacturing
`a semiconduc-
`tor apparatus further comprises the step of, prior to the above
`fifth step, forming side walls for LDD at least on the side
`faces of the first conductive
`serving as the
`interconnection
`the side waUs formed in the above
`gate electrode, wherein
`second step can function only as side walls for isolation.
`there is formed an active element having
`By the method,
`interconnections.
`LDD structure and miniaturized
`In the above basic method of manufacturing
`a semicon-
`ductor apparatus, after the above fifth step, the above side
`
`walls can be partially processed by dry etching,
`thereby
`intercon-
`the above first conductive
`electrically connecting
`interconnections.
`nections to the above second conductive
`By the method, it becomes possible to electrically
`isolate
`from the second con-
`interconnections
`the first conductive
`ductive interconnections by the side waUs, while electrically
`to the sec-
`interconnections
`the first conductive
`connecting
`in a desired area without
`interconnections
`ond conductive
`interconnection. Consequently,
`the
`forming an additional
`process is simplified and the circuit area is
`manufacturing
`further reduced.
`In the above basic method of manufacturing
`a semicon-
`in the above third step, the first conductive
`ductor apparatus,
`interconnedions which consist of an upper layer composed
`film with a high etching rate and a lower
`of an insulating
`layer composed of a conductive
`film are formed, the above
`the step of. after the above fifth
`method further comprising
`film with a
`step, selectively
`removing only the insulating
`the upper layer of the above
`high etching rate composing
`the above
`in
`interconnections, wherein
`first conductive
`seventh step, the above metal fihn is composed of a metal
`material with a low resistance and in the above eighth step,
`the metal film over the above active region is isolated from
`interconnections by
`the metal film over the first conductive
`the above second conductive
`the above side walls and
`are composed only of the above metal film.
`interconnections
`while chemical mechanical polishing can be performed so as
`interconnections of a
`to compose the above first conductive
`film of the above first conductive
`film and the
`multi-layer
`above metal film.
`By the method. the resistance of the active region, i. e. , the
`layer of the active
`resistance of the region of the diffusion
`high-
`can be reduced without performing
`element
`such as salicide process.
`treatment
`thermal
`temperature
`is not
`semiconductor
`substrate
`the underlying
`Moreover,
`consumed, so that an active element with minimum
`junction
`leakage can be obtained.
`To reduce the capacitance of a gate electrode,
`there are
`second and third methods of
`the following
`also provided
`apparatus. The second
`semiconductor
`manufacturing
`method of manufacturing
`apparatus corn-
`a semiconductor
`the steps of: forming
`isolation
`a circumferential
`prises
`region which surrounds an active region of a semiconductor
`substrate in which a MISFET is to be formed; introducing an
`for controlling a threshold of the above MISFEr
`impurity
`into the above active region; forming a stepped
`insulating
`film consisting of a portion which
`thin to
`is sufilciently
`the function of the above MISFET and a portion
`enable
`the function of the
`thick to disenable
`is sufficiently
`which
`MISFEI' and a gate electrode; forming side walls from an
`insulating material on both sides of the above gate electrode;
`layers which serve as a
`impurity diffusion
`two
`forming
`region of the above MISFEf in those regions of
`source/drain
`the above active region which are located on both sides of
`the above gate electrode; depositing a metal film over the
`entire surface of the substrate after forming
`the above gate
`electrode, the above side walls, and the above circumferen-
`the above metal
`tial isolation
`region; partially
`removing
`isolation region, the above
`film, the above circumferential
`the above side walls by chemical
`gate electrode,
`and
`mechanical polishing such that, in a plane when the chemi-
`two remaining por-
`is completed,
`cal mechanical polishing
`tions of the above metal
`the above respective
`film on
`layers are surrounded by the above gate
`impurity diffusion
`isolation region and
`electrode and the above circumferential
`isolated from each other.
`electrically
`third method of manufacturing
`a semiconductor
`The
`apparatus comprises the steps of: forming a circumferential
`
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`

`
`an active region of a
`isolation
`region which
`surrounds
`in which a MISFET is to be formed;
`substrate
`semiconductor
`for controlling a threshold of the
`introducing
`an impurity
`above MISFEf into the above active region so as to form,
`in a region in which a gate electrode is to be formed. a region
`the impurity has been introduced at a concen-
`into which
`to a low threshold which enables
`the
`tration corresponding
`function of the above MISFEf and a region into which the
`to a concentration correspond-
`impurity has been introduced
`the function of the
`ing to a high threshold which disenables
`above MISFET; forming a gate insulating
`film and the gate
`electrode of the above MISFEI' in the above active region;
`forming side waUs from an insulafing material on both sides
`of the above gate electrode; forming two impurity diffusion
`region of the above.
`layers, which serve as a source/drain
`MISFET, in those regions of the above active region which
`are located on both sides of the above gate electrode;
`the entire surface of the
`film over
`a metal
`depositing
`the above gate electrode, the above
`substrate after forming
`side waUs, and the above circumferential
`isolation region;
`the above metal
`the above
`removing
`and partially
`film,
`the above gate electrode,
`isolation region,
`circumferential
`and the above side walls by chemical mechanical polishing
`such that, in a plane when the chemical mechanical polish-
`ing is completed. two remaining portions of the above metal
`layers are
`film on the above respective
`impurity diffusion
`by the above gate electrode and
`the above
`surrounded
`isolated
`region and electrically
`isolation
`circumferential
`from each other.
`By the methods, the capacitance of the gate electrode after
`is reduced,
`the formation of the semiconductor
`apparatus
`apparatus operable at a high
`in the semiconductor
`resulting
`speed.
`To facilitate the measurement of the characteristics of the
`process
`in
`semiconductor
`the manufacturing
`apparatus
`thereof, there is further provided a fourth method of manu-
`facturing a semiconductor apparatus according to the present
`the steps of: forming a circum-
`invention, which comprises
`isolation region for dividing a surface region of a
`ferential
`into a first primary active region in
`substrate
`semiconductor
`which a first MISFET for use as an active element of the
`is to be formed, a second primary
`semiconductor apparatus
`in which a second MISFET for use as an
`active region
`element under test is to be formed, a first active region for
`continued from a portion of the above second
`measurement
`primary active region in which the gate electrode is to be
`formed, a second active region for measurement
`continued
`from a portion of the above second primary active region in
`is to be formed, a third active region for
`which a drain
`from a portion of the above second
`continued
`measurement
`active region in which a source is to be formed. and
`isolated from each of
`a fourth active region for measurement
`the above active regions;
`an
`introducing
`simultaneously
`thresholds of the first and second
`for controlling
`impurity
`MISFEI's into each of the above active regions; forming
`films and gate electrodes of the
`respective gate insulating
`above first and second MISFETs in the above first and
`second primary active regions; forming side walls from an
`insulating material on both sides of the above gate elec-
`trodes; forming
`layers, which serve
`two impurity diffusion
`regions of the above
`first and second
`as source/drain
`MISFETs, in those regions of the above first and second
`active regions which are located on both sides of the
`above gate electrodes and in the above second and third
`active regions for measurement; depositing a metal film over
`the entire surface of the substrate after forming
`the above
`gate electrodes. the above side walls, and the above circum-
`
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`the above
`isolation region; and partially removing
`ferential
`isolation region,
`the
`metal film. the above circumferential
`above gate electrodes. and the above side walls by chetnical
`mechanical polishing such that. in a plane when the chemi-
`is completed,
`two remaining por-
`cal mechanical polishing
`tions of the above metal film on the above respective active
`regions are surrounded by the above gate electrodes and the
`iso-
`isolation region and electrically
`above circumferential
`lated from each other, the metal film isolated on a region
`extending from the drain in the second primary active region
`to the above second active region for measurement
`being
`used as an electrode for the drain of the second MISFET, the
`metal film isolated on a region extending from the source in
`region to the above third active
`the above second primary
`region for measurement being used as an electrode for the
`source of the second MISFET, the metal film isolated on the
`above fourth active region being used as an electrode for the
`substrate; and directly measuring. when the above chemical
`is completed, characteristics of the
`mechanical polishing
`above second MISFET via
`for the gate,
`the electrodes
`source, and drain of the second MISFET and via
`the
`electrode for the substrate.
`The method enables an easy evaluation of the unfinished
`semiconductor apparatus being manufactured. which facili-
`tates the setting of conditions compatible with the required
`characteristics of the semiconductor apparatus as well as the
`detection of a failure at an early stage of the manufacturing
`process.
`formed in accordance with
`The semiconductor apparatus
`the above individual manufacturing methods also provide
`the same effects.
`
`the layout of a MOSFET in the
`
`cross sectional view partially
`in the step of FIG.
`apparatus
`
`BRIEF DESCRIPrlON OF THE DRAWINGS
`FIGS. 1(a) to 1(f) are cross sectional views showing
`the
`transition of the structure of a semiconductor
`apparatus
`the manufacturing
`to a first embodiment
`according
`during
`process thereof;
`FIG. 2 is an enlarged
`the semiconductor
`showing
`1(f);
`FIG. 3 is a view showing
`first embodiment;
`the dependence of
`FIG. 4 is a characteristic view showing
`the sheet resistance value of an impurity diffusion
`layer on
`the fil thickness and its standard deviation
`in the first
`embodiment;
`the dependence of
`FIG, 5 is a characteristic view showing
`a contact resistance value on a contact hole diameter
`in the
`first embodiment;
`FIGS. 6(a) and 6(b) show and illustrate a SEM photo-
`graph of the MOSFET in a plane when the CMP process is
`in the first embodiment;
`completed
`FIGS. 7(a) to 7(c) are cross sectional views showing
`the
`transition of the structure of the semiconductor
`apparatus
`according to a second embodiment
`during the manufacturing
`process thereof;
`FIG. 8 is an electric circuit diagram of a two-stage
`inverter consisting of four MOSFEI's in the second embodi-
`rnent;
`FIG. 9 is a view showing
`the layout of the two-stage
`in the second embodiment;
`inverter
`FIGS. 10(a) to 10(e) are cross sectional views showing
`the transition of the structure of the semiconductor apparatus
`according to a third embodiment during
`the manufacturing
`process thereof;
`
`Page 31 of 41
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`

`
`5, 733, 812
`
`FIG. 11 is a view showing the layout of a MOSFET in the
`third exnbodiment;
`FIGS. 12(a) to 12(f) are cross sectional views showing the
`transition of the structure of the semiconductor
`apparatus
`according to a fourth embodiment during the manufacturing
`process thereof;
`the layout of a MOSFET with
`FIG. 13 is a view showing
`in a fifth embodiment;
`a measurement pad terminal
`FIGS. 14(a) to 14(e) are plan views and cross sectional
`the transition of the structure of the semi-
`views showing
`conductor apparatus according to a sixth embodixnent