`Chau et al.
`
`[54]
`
`[75]
`
`TRANSISTOR WITH LOW RESISTANCE TIP
`AND METHOD OF FABRICATION IN A
`CMOS PROCESS
`
`Inventors: Robert S. Chau, Beaverton;
`Chia-Hong Jan, Portland; Chan-Hong
`Chern, Portland; Leopoldo D. Yau,
`Portland, all of Oreg.
`
`[73]
`
`Assignee: Intel Corporation, Santa Clara, Calif.
`
`[ *] Notice:
`
`This patent issued on a continued pros(cid:173)
`ecution application filed under 37 CFR
`1.53( d), and is subject to the twenty year
`patent term provisions of 35 U.S.C.
`154(a)(2).
`
`[21] Appl. No.: 08/581,243
`
`[22] Filed:
`
`Dec. 29, 1995
`
`Related U.S. Application Data
`
`[63]
`
`[51]
`[52]
`
`[58]
`
`Continuation-in-part of application No. 08/363,749, Dec.
`23, 1994, Pat. No. 5,710,450.
`Int. Cl? ................................................. HOlL 21!8238
`U.S. Cl. .......................... 438/231; 438/226; 438/233;
`438/232; 438/305; 438/306; 438/586; 438/589;
`438/576; 438/558; 438/561; 438/664
`Field of Search ..................................... 438/589-663,
`438/664, 191, 226-223, 229, 230, 231,
`232, 259, 270, 330, 301, 303, 305, 306,
`586, 576, 558, 565, 581, 583, FOR 168,
`FOR 180, FOR 197, FOR 216, FOR 217,
`FOR 218, FOR 251, FOR 250, FOR 219;
`148/DIG. 147, DIG. 19, DIG. 59; 257/288,
`900
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,133,704
`4,683,645
`4,876,213
`4,998,150
`5,006,476
`
`1!1979 Maciver eta!. ......................... 148/1.5
`8/1987 Naguib eta!. ............................ 437/41
`10/1989 Pfiester ...................................... 437/34
`3/1991 Rodder eta!. ......................... 357/23.1
`4/1991 DeJong eta!. .......................... 437/31
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US006165826A
`[11] Patent Number:
`[45] Date of Patent:
`
`6,165,826
`*Dec. 26, 2000
`
`5,162,263
`5,168,072
`5,231,042
`5,285,088
`5,336,903
`5,341,014
`5,352,631
`5,393,685
`5,397,909
`5,405,795
`
`11/1992 Kunishima eta!. .................... 437/200
`12/1992 Moslehi .................................... 437/41
`7/1993 Ilderem eta!. ........................... 437/44
`2/1994 Sa to et a!. ... ... ... ... .... ... ... ... ... ... 257/192
`8/1994 Ozturk et a!. ............................. 257/19
`8/1994 Fujii eta!. .............................. 257/377
`10/1994 Sitaram eta!. ......................... 437/200
`2/1995 Yoo et a!. ................................. 437/44
`3/1995 Moslehi .................................. 257/383
`4/1995 Beyer et a!. .............................. 437/89
`
`(List continued on next page.)
`
`FOREIGN PATENT DOCUMENTS
`
`8448061
`361051959
`
`5/1998 European Pat. Off ..
`3/1986
`Japan ............................ 438/FOR 168
`
`Primary Examiner-Long Pham
`Attorney, Agent, or Firm-Blakely, Sokoloff, Taylor &
`Zafman LLP
`
`[57]
`
`ABSTRACT
`
`A novel transistor with a low resistance ultra shallow tip
`region and its method of fabrication in a complementary
`metal oxide semiconductor (CMOS) process. According to
`the preferred method of the present invention, a first gate
`dielectric and a first gate electrode are formed on a first
`portion of a semiconductor substrate having a first conduc(cid:173)
`tivity type, and a second gate dielectric and a said gate
`electrode are formed on a second portion of semiconductor
`substrate having a second conductivity type. A silicon nitride
`layer is formed over the first portion of the semiconductor
`substrate including the first gate electrode and over the
`second portion of the semiconductor substrate including the
`second gate electrode. The silicon nitride layer is removed
`from the second portion of the silicon substrate and from the
`top of the second gate electrode to thereby form a first pair
`of silicon nitride spacers adjacent to opposite sides of the
`second gate electrode. A pair of recesses are then formed in
`the second portion of the semiconductor substrate in align(cid:173)
`ment with the first pair of sidewall spacers. A selectively
`deposited semiconductor material is then formed in the
`recesses.
`
`52 Claims, 13 Drawing Sheets
`
`:-210-:~-212--
`
`:~--211---
`
`TSMC Exhibit 1013
`
`Page 1 of 29
`
`
`
`6,165,826
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`5,478,776 12/1995 Luftman eta!. ........................ 437/163
`5,538,909
`7/1996 Hsu ........................................... 437/35
`5,569,624 10/1996 Weiner .................................... 437/200
`
`5,620,912
`5,710,450
`5,726,071
`5,770,507
`
`4/1997 Hwang et a!. .......................... 438/301
`1!1998 Chau eta!. ............................. 257/344
`........................... 437/57
`3/1998 Segawa et a!.
`6/1998 Chen et a!.
`............................. 438/305
`
`Page 2 of 29
`
`
`
`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 1 of 13
`
`6,165,826
`
`102
`
`120
`..........,_ _
`
`___. 11 0 106
`
`120
`11 0 .....__----4
`JQ2
`
`100
`
`FIG. 1 (PRIOR ART)
`
`Page 3 of 29
`
`
`
`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 2 of 13
`
`6,165,826
`
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`
`Page 4 of 29
`
`
`
`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 3 of 13
`
`6,165,826
`
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`FIG. 38
`
`FIG. 3C
`
`Page 5 of 29
`
`
`
`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 4 of 13
`
`6,165,826
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`FIG. 3F
`
`Page 6 of 29
`
`
`
`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 5 of 13
`
`6,165,826
`
`32~
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`
`FIG. 3H
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`Page 7 of 29
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`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 6 of 13
`
`6,165,826
`
`301
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`Page 8 of 29
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`
`Dec. 26, 2000
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`Sheet 7 of 13
`
`6,165,826
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`Page 9 of 29
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`
`
`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 8 of 13
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`6,165,826
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`Page 10 of 29
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`
`
`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 9 of 13
`
`6,165,826
`
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`Page 11 of 29
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`
`Dec. 26, 2000
`
`Sheet 10 of 13
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`6,165,826
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`
`Page 12 of 29
`
`
`
`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 11 of 13
`
`6,165,826
`
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`Page 13 of 29
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`
`
`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 12 of 13
`
`6,165,826
`
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`Page 14 of 29
`
`
`
`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 13 of 13
`
`6,165,826
`
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`Page 15 of 29
`
`
`
`6,165,826
`
`1
`TRANSISTOR WITH LOW RESISTANCE TIP
`AND METHOD OF FABRICATION IN A
`CMOS PROCESS
`
`This application is a Continuation-in-Part of U.S. patent
`application Ser. No. 08/363,749, filed Dec. 23, 1994 now
`U.S. Pat. No. 5,710,450 and assigned to the present
`Assignee.
`
`BACKGROUND OF THE INVENTION
`
`10
`
`15
`
`2
`metal oxide semiconductor process (CMOS) is described.
`According to a preferred method of the present invention, a
`first gate dielectric and a first gate electrode are formed on
`a first portion of a semiconductor substrate having a first
`5 conductivity type, and a second gate dielectric and a second
`gate electrode are formed on a second portion of a semi(cid:173)
`conductor substrate having a second conductivity type.
`Next, ions of a second conductivity type are implanted into
`the first portion of the semiconductor substrate in alignment
`with the outside edges of the first gate electrode. A silicon
`nitride layer is then formed over the first portion of the
`semiconductor substrate including the first gate electrode
`and over the second portion of the semiconductor substrate
`including the second gate electrode. The silicon nitride layer
`is then removed from the second portion of the silicon
`substrate and from the top of the second gate electrode to
`thereby form a first pair of silicon nitride spacers adjacent to
`opposite sides of the second gate electrode. A pair of
`recesses are then formed in the second portion of the
`semiconductor substrate in alignment with the first pair of
`silicon nitride spacers. A selectively deposited semiconduc(cid:173)
`tor material is then formed in the recesses. Dopants are then
`diffused from the selectively deposited semiconductor mate(cid:173)
`rial into the substrate beneath the first pair of silicon nitride
`spacers. Next, a first pair of sidewall spacers are formed
`adjacent to opposite sides of the first gate electrode and a
`second pair of sidewall spacers are formed on the deposited
`semiconductor material adjacent to the outside edge of the
`first pair of silicon nitride spacers. Ions of a second con-
`30 ductivity type are then implanted into the first portion of the
`semiconductor substrate in alignment with the outside edges
`of the first pair of sidewall spacers adjacent to the first gate
`electrode to thereby form a first pair of source/drain contact
`regions in the first portion of the semiconductor substrate.
`Silicide is then formed on the source/drain contact regions
`and on the first gate electrode and on the deposited semi(cid:173)
`conductor material in alignment with the outside edges of
`the second pair of sidewall spacers are on the second gate
`electrode.
`
`1. Field of the Invention
`The present invention relates to the field of semiconductor
`integrated circuits, and more specifically, to the ultra large(cid:173)
`scale fabrication of submicron transistors.
`2. Discussion of Relates Art
`Today literally millions of individual transistors are
`coupled together to form very large-scale integrated (VLSI)
`circuits, such as microprocessors, memories, and applica(cid:173)
`tions specific integrated circuits (ICs). Presently, the most
`advanced ICs are made up of approximately three million
`transistors, such as metal oxide semiconductor (MOS) field
`effect transistors having gate lengths on the order of 0.5 ,urn.
`In order to continue to increase the complexity and compu(cid:173)
`tational power of future integrated circuits, more transistors
`must be packed into a single IC (i.e., transistor density must
`increase). Thus, future ultra large-scale integrated (ULSI)
`circuits will require very short channel transistors with
`effective gate lengths less than 0.1 ,urn. Unfortunately, the
`structure and method of fabrication of conventional MOS
`transistors cannot be simply "scaled down" to produce
`smaller transistors for higher density integration.
`The structure of a conventional MOS transistor 100 is
`shown in FIG. 1. Transistor 100 comprises a gate electrode
`102, typically polysilicon, formed on a gate dielectric layer
`104 which in turn is formed on a silicon substrate 106. A pair
`of source/drain extensions or tip regions 110 are formed in
`the top surface of substrate 106 in alignment with outside
`edges of gate electrode 102. Tip regions 110 are typically
`formed by well-known ion implantation techniques and 40
`extend beneath gate electrode 102. Formed adjacent to
`opposite sides of gate electrode 102 and over tip regions 110
`are a pair of sidewall spacers 108. A pair of source/drain
`regions 120 are then formed, by ion implantation, in sub(cid:173)
`strate 106 substantially in alignment with the outside edges 45
`of sidewall spacers 108.
`As the gate length of transistor 100 is scaled down in
`order to fabricate a smaller transistor, the depth at which tip
`region 110 extends into substrate 106 must also be scaled
`down (i.e., decreased) in order to improve punchthrough 50
`characteristics of the fabricated transistor. Unfortunately, the
`length of tip region 110, however, must be larger than 0.07
`,urn to insure that the later, heavy dose, deep source/drain
`implant does not swamp and overwhelm tip region 110.
`Thus, in the fabrication of a small scale transistor with
`conventional methods, as shown in FIG. 1, the tip region 110
`is both shallow and long. Because tip region 110 is both
`shallow and long, tip region 110 exhibits substantial para(cid:173)
`sitic resistance. Parasitic resistance adversely effects
`(reduces) the transistors drive current.
`Thus, what is needed is a novel transistor with a low
`resistance ultra shallow tip region with a VLSI manufactur(cid:173)
`able method of fabrication in a CMOS process.
`
`20
`
`25
`
`35
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is an illustration of a cross-sectional view of a
`conventional transistor.
`FIG. 2 is an illustration of a cross-sectional view of a low
`resistance ultra shallow tip transistor of the present inven(cid:173)
`tion.
`FIG. 3a is an illustration of a cross-sectional view of the
`formation of a first gate electrode on a p-well and the
`formation of a second gate electrode on a n-well.
`FIG. 3b is an illustration of a cross-sectional view of the
`formation of aN- tip region in the p-well in alignment with
`opposite sidewalls of the first gate electrode of the substrate
`of FIG. 3a.
`FIG. 3c is an illustration of a cross-sectional view of the
`55 formation of a silicon nitride layer over the substrate of FIG.
`3b.
`FIG. 3d is an illustration of a cross-sectional view show(cid:173)
`ing the formation of a first pair of sidewall spacers on
`opposite sides of a gate electrode formed on a substrate and
`60 the formation of recess regions in the n-well of the substrate
`of FIG. 3c.
`FIG. 3e is an illustration of a cross-sectional view show(cid:173)
`ing the deposition of semiconductor material on the sub(cid:173)
`strate of FIG. 3d.
`FIG. 3f is an illustration of a cross-sectional view showing
`the formation of an oxide layer and a silicon nitride layer
`over the substrate of FIG. 3e.
`
`65
`
`SUMMARY OF THE INVENTION
`A novel transistor with a low resistance ultra shallow tip
`region and its method of fabrication in a complementary
`
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`5
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`15
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`3
`FIG. 3g is an illustration of a cross-sectional view show(cid:173)
`ing the formation of a first pair of sidewall spacers adjacent
`to the first gate electrode and a second pair of sidewall
`spacers adjacent to the first pair of silicon nitride spacers on
`the substrate of FIG. 3f
`FIG. 3h is an illustration of a cross-sectional view show(cid:173)
`ing the formation of silicide in the source/drain contact
`regions and on the deposited semiconductor material of FIG.
`3g.
`FIG. 4a is an illustration of a cross-sectional view show- 10
`ing the formation of a boron doped glass layer and the
`formation of N- tip regions in the substrate of FIG. 3a.
`FIG. 4b is an illustration of a cross-sectional view show-
`ing the formation of a silicon nitride layer over the substrate
`of FIG. 4a.
`FIG. 4c is an illustration of a cross-sectional view show(cid:173)
`ing the formation of a first pair of composite sidewall
`spacers adjacent to the gate electrode over the n-well of the
`substrate of FIG. 4b.
`FIG. 4d is an illustration of a cross-sectional view show(cid:173)
`ing the formation of semiconductor material on the substrate
`of FIG. 4c.
`FIG. 4e is an illustration of a cross-sectional view show(cid:173)
`ing the formation of a first pair of spacers adjacent to the gate
`electrode formed over the p-well and the formation of a
`second pair of spacers adjacent to the first pair of composite
`spacers formed adjacent to the gate electrode over then-well
`of the substrate of FIG. 4d.
`FIG. 4fis an illustration of a cross-sectional view showing
`the out diffusion of impurities from deposited semiconductor
`material and the formation of silicide on the substrate of
`FIG. 4e.
`FIG. Sa is an illustration of a cross-sectional view show-
`ing the formation of a silicon nitride layer over the substrate 35
`of FIG. 3a.
`FIG. Sb is an illustration of a cross-sectional view show(cid:173)
`ing the formation of spacers and recesses on the substrate of
`FIG. Sa.
`FIG. Sc is an illustration of a cross-sectional view show- 40
`ing the masking of the n-well and the formation of semi(cid:173)
`conductor material on the p-well of the substrate of FIG. Sb.
`FIG. Sd is an illustration of a cross-sectional view show-
`ing the formation of a mask over the p-well and the
`formation of semiconductor material on the n-well of the 45
`substrate of FIG. Sc.
`FIG. Se is an illustration of a cross-sectional view show-
`ing the formation of a thin oxide layer and the formation of
`a thicker silicon nitride layer over the substrate of FIG. Sd.
`FIG. Sf is an illustration of a cross-sectional view showing
`the formation of a second pair of spacers and the out
`diffusion of dopants from semiconductor material on the
`substrate of FIG. Se.
`FIG. 6a is an illustration of a cross-sectional view show- 55
`ing the formation of p-type semiconductor material on a
`n-well, and the formation of undoped semiconductor mate(cid:173)
`rial on a p-well of a substrate.
`FIG. 6b is an illustration of a cross-sectional view show-
`ing the formation of a mask and the ion implantation of the 60
`substrate of FIG. 6a.
`FIG. 6c is an illustration of a cross-sectional view show(cid:173)
`ing the formation of sidewall spacers and the implantation of
`the substrate of FIG. 6b.
`FIG. 6d is an illustration of a cross-sectional view show- 65
`ing the diffusion of impurities from semiconductor material
`and the formation of silicide of the substrate of FIG. 6c.
`
`4
`FIG. 7a is an illustration of a cross-sectional view show(cid:173)
`ing the formation and patterning of a boron doped glass layer
`on the substrate of FIG. 3a.
`FIG. 7b is an illustration of a cross-sectional view show-
`ing the formation of a silicon nitride layer over the substrate
`of FIG. 7a.
`FIG. 7c is an illustration of a cross-sectional view show(cid:173)
`ing the formation of spacers and recesses in the substrate of
`FIG. 7b.
`FIG. 7d is an illustration of a cross-sectional view show(cid:173)
`ing the formation of semiconductor material over the sub(cid:173)
`strate of FIG. 7c.
`FIG. 7e is an illustration of a cross-sectional view show-
`ing the formation of a second pair of spacers over the
`substrate of FIG. 7d.
`FIG. 7f is an illustration of a cross-sectional view showing
`the out diffusion of impurities from deposited semiconductor
`material and the formation of silicide on the substrate of
`20 FIG. 7e.
`DETAILED DESCRIPTION OF 1HE PRESENT
`INVENTION
`A novel transistor with a low resistance ultra shallow tip
`25 and its method of fabrication in a complementary metal
`oxide semiconductor (CMOS) process is described. In the
`following description numerous specific details are set forth,
`such as specific materials, dimensions, and processes, etc.,
`in order to provide a thorough understanding of the present
`30 invention. It will be obvious, however, to one skilled in the
`art, that the invention may be practiced without these
`specific details. In other instances, well-known semiconduc(cid:173)
`tor equipment and processes have not been described in
`particular detail in order to avoid unnecessarily obscuring
`the present invention.
`A preferred embodiment of a novel transistor 200 with
`low resistivity, ultra shallow tip of the present invention is
`shown in FIG. 2. Transistor 200 is formed on a silicon
`substrate or well 201. A gate dielectric layer 202 is formed
`on a surface 203 of substrate 201 and a gate electrode 204
`is in turn formed on gate dielectric layer 202. A first pair of
`thin sidewall spacers 206 are formed on opposite sides of
`gate electrode 204 (spacers 206 run along the "width" of
`gate electrode 204). Transistor 200 also includes a second
`pair of substantially thicker sidewall spacers 208 formed
`adjacent to the outside edges of the first pair of sidewall
`spacers 206. Transistor 200 includes a pair of source/drain
`regions 211 each comprising a pair of tips or source/drain
`extensions 210 and a source/drain contact region 212.
`Tip or source/drain extension 210 is defined as the source/
`drain region located beneath second sidewall spacer 208,
`first sidewall spacer 206, and the outside edge of gate
`electrode 204. Tip 210 comprises an ultra shallow tip portion
`214 and a raised tip portion 216. Ultra shallow tip portion
`214 is comprised of a doped semiconductor substrate 21S
`formed by "out diffusing" dopants from selectively depos-
`ited semiconductor material 217 into substrate 201. Ultra
`shallow tip 214 extends from beneath first sidewall spacer
`206 to the outside edges of gate electrode 204. Ultra shallow
`tip 214 preferably extends at least 100 A beneath (laterally)
`gate electrode 204 and preferably 500 A for a transistor with
`an effective gate length of approximately 0.10 microns (or
`1000 A) and a drawn gate length of 0.2 ,urn. Additionally,
`ultra shallow tip 214 preferably extends less than 1000 A
`deep into substrate 201 beneath substrate surface 203 for a
`0.10 ,urn effective gate length. It is to be appreciated that
`because novel methods of fabrication are employed in the
`
`50
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`5
`present invention, ultra shallow tip 214 can be characterized
`by a very abrupt junction.
`Tip 210 of transistor 200 also includes a raised tip portion
`216. Raised tip portion 216 is located beneath second
`sidewall spacer 208 and is adjacent to the outside edges of
`first sidewall spacer 206. Raised tip 216 is preferably formed
`of doped semiconductor material 217 selectively deposited
`both above and below surface 203 of semiconductor sub(cid:173)
`strate 201. Raised tip portion 216 also includes a portion 215
`doped by "out diffusing" dopants from selectively deposited
`semiconductor material 217 into substrate 201. Because a
`portion of raised tip 216 is formed above semiconductor
`substrate surface 203, raised tip 216 is said to be "raised". A
`raised tip significantly reduces the parasitic resistance of
`transistor 200 and thereby improves its performance.
`A pair of source/drain contact regions 212 are formed
`adjacent to the outside edge of second sidewall spacer 208.
`Source/drain contact regions 212 comprise selectively
`deposited semiconductor material 217 and "out diffused"
`doped semiconductor substrate 215. Source/drain contact
`regions 212 are partially raised source/drain regions. Silicide
`218 is preferably formed on source/drain regions 212 in
`order to reduce the contact resistance of transistor 200.
`Additionally, according to the present invention, first semi(cid:173)
`conductor material 217 is preferably deposited onto the top
`surface of gate electrode 204. Silicide 218 is also preferably
`formed on deposited semiconductor material 217 on gate
`electrode 204 to help improve contact resistance.
`Additionally, if desired, source/drain contact regions 212
`can be made into deep junction source/drain contacts by ion 30
`implanting or diffusing additional dopants into a region 220
`in substrate 201 in alignment with the outside edges of
`second sidewall spacers 208.
`It is to be appreciated that a valuable feature of the present 35
`invention is the fact that transistor 200 includes a tip or
`source/drain extension 210 which is both ultra shallow and
`raised. In this way, transistor 200 has a shallow tip with a
`very low parasitic resistance. The novel structure of tran(cid:173)
`sistor 200 allows for tip scaling necessary for the fabrication 40
`of transistor 200 with effective gate length less than 0.12 ,urn.
`Because of the novel tip structure 210 of the present
`invention, transistor 200 has good punchthrough perfor(cid:173)
`mance and reduced V r roll-off. Additionally, because of tip
`210, transistor 200 has a low parasitic resistance, resulting in 45
`good drive current.
`The present invention describes several methods of inte(cid:173)
`grating the fabrication of a transistor with a low resistance
`ultra shallow tip into a CMOS process (i.e. into a process
`where both n-type and p-type transistors are formed).
`According to a first preferred method of the present
`invention, as illustrated in FIGS. 3a-3h, a PMOS transistor
`having a low resistance ultra shallow tip is fabricated with
`a conventional NMOS transistor. According to the preferred
`method of the present invention, a silicon substrate 300 is
`provided. A plurality of field isolation regions 305 are
`formed in substrate 300 to isolate wells of different conduc(cid:173)
`tivity types and to isolate adjacent transistors. Field isolation
`regions 305 are preferably shallow trench isolation (STI)
`regions formed by etching a trench into substrate 300 and
`then filling the trench with a deposited oxide. Although STI
`isolation regions are preferred because of their ability to be
`formed to small dimensions with a high degree of planarity,
`other methods can be used such as, but not limited to,
`LOCOS, recessed LOCOS, or silicon on insulator (SOl),
`and suitable insulators, other than oxides, such as nitrides
`may be used if desired.
`
`6
`Silicon substrate 300 includes a first region 302 of p-type
`conductivity in the range of 1x1017/cm3-1x1019/cm3 and a
`second region 304 of n-type conductivity in the range of
`1x1017/cm 3 -1x10 19/cm 3
`. According to the preferred
`5 embodiment, n-type conductivity region 304 is a n-well
`formed by a first implant of phosphorous atoms at a dose of
`4x1013/cm2 and an energy of 475 keY, a second implant of
`phosphorous atoms at a dose of 2.5x1012/cm2 at an energy
`of 60 ke V, and a final implant of arsenic atoms at a dose of
`10 1x1013 /cm2 at an energy of 180 ke V into a silicon substrate
`300 having a concentration of 1x1016/cm3
`in order to
`produce a n-well 304 having a n-type concentration of
`approximately 7.0xl017/cm3
`. Additionally, according to the
`preferred embodiment of the present invention, p-type con-
`15 ductivity region 302 is a p-well formed by a first implant of
`boron atoms at a dose of 3.0x1013/cm2 at an energy of 230
`ke V followed by a second implant of boron ions at a dose of
`4.2x1013 /cm3 and an energy of 50 ke V into substrate 300 in
`order to produce a p-well 302 having a p-concentration of
`20 7.0x1017/cm3
`. It is to be appreciated that p-type conductivity
`region 302 and n-type conductivity 304 may be formed by
`other means including providing an initially doped substrate,
`or depositing an insitu doped semiconductor material with a
`desired conductivity. According to the present invention, a
`25 substrate is defined as the starting material on which the
`transistors of the present invention are fabricated and
`includes p-well 302 and n-well 304.
`According to the present invention, a first gate dielectric
`layer 303 is formed on the top surface 301 of substrate 300
`as shown in FIG. 3a. Gate dielectric layer 303 is preferably
`a nitrided oxide layer formed to a thickness of between
`20--50 angstroms (A). It is to be appreciated that other well
`known gate dielectric layers such as oxides, nitrides, and
`combinations thereof may be utilized if desired. Next, a gate
`electrode 306 is formed over gate dielectric layer 303
`formed over p-well 302 and a gate electrode 308 is formed
`over gate dielectric layer 303 formed over n-well 304. Gate
`electrodes 306 and 308 are preferably formed from a
`1000-3500 A thick layer of blanket deposited polysilicon
`patterned into gate electrodes 306 and 308 with well known
`photolithographic techniques. If desired, the polysilicon
`layer can be ion implanted to the desired conductivity type
`and level prior to patterning.
`It is to be appreciated that other well known patterning
`techniques may be utilized to pattern the polysilicon layer
`into gate electrodes 306 and 308 including submicron lithog(cid:173)
`raphy techniques, such as e-beam and x-ray, and subphoto(cid:173)
`lithographic patterning techniques such as described in U.S.
`Pat. No. 5,434,093 entitled "Inverted Spacer Transistor" and
`50 assigned to the present Assignee. According to the presently
`preferred method of the present invention, polysilicon gate
`electrodes 306 and 308 preferabl¥ have a drawn length of
`approximately 0.2 ,urn (i.e. 2000 A). Additionally, although
`gate electrodes 306 and 308 are preferably polysilicon gate
`55 electrodes, gate electrodes 306 and 308 can be, but are not
`limited to, metal gates, a single crystalline silicon gate, or
`any combination thereof, if desired.
`Next, as shown in FIG. 3b, substrate 300 is covered with
`a photoresist layer. The photoresist layer is then patterned
`60 with well known photolithography techniques to form a
`photoresist mask 310 which exposes p-well 302 and masks
`n-well 304. Next, n-type conductivity ions are implanted
`into substrate 300 to form conventional N- tip regions 312
`in alignment with the outside edges of gate electrode 306.
`65 Gate electrode 306 prevents the region beneath gate elec(cid:173)
`trode 306 from being implanted with ions. Additionally,
`photoresist mask 310 prevents n-well304 from being doped
`
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