United States Patent
`
`[11] Patent Number:
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`4,506,434
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`Ogawa et al.
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`‘[45] Date of Patent:
`Mar. 26, 1985
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`[19]
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`4,391,650
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`................... .. 29/571 X
`7/1983 Pfeifer et al.
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`FOREIGN PATENT DOCUMENTS
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`3023410
`1/1922 Fed. Rep. of Germany.
`1/1977 Japan .............................1s6/661.1
`2174
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`51872 4/1977 Japan ............................... 156/653
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`OTHER PUBLICATIONS
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`IBM Technical Disclosure Bulletin, vol. 23, No. 8, Jan.
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`1981, New York, D. W. Ormond, pp. 3694-3697.
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`IBM Technical Disclosure Bulletin, vol. 21, No. 7, Dec.
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`1978, New York, H. B. Pogge, pp. 2734—2735.
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`IBM Technical Disclosure Bulletin, Abbas et a1., “Sim-
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`plified Isolation for an Integrated Circuit”, vol. 25, No.
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`12, May 1983, pp. 6611-6614.
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`Primary Examiner——Brian E. Hearn
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`Assistant Examiner—David A. Hey
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`Attorney, Agent, or Firm—Armstrong, Nikaido,
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`Marmelstein & Kubovcik
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`ABSTRACT
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`[57]
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`A method for producing semiconductor devices having
`a substrate, element fabrication areas formed in the
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`substrate and isolation areas surrounding the element
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`fabrication areas. The method comprises forming a
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`thermal strain absorbing layer on the top surface of the
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`element fabrication areas, forming at least one groove in
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`an area which is to become the isolation areas, inlaying
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`an insulator in the at least one groove, and annealing the
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`insulator to make the density thereof uniform.
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`9 Claims, 21 Drawing Figures
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`[75]
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`[51]
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`[56]
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`[54] METHOD FOR PRODUCTION OF
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`SEMICONDUCTOR DEVICES
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`Inventors: Tetsuya Ogawa, Machida; Nobuo
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`Toyokura, Kawasaki, both of Japan
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`Fujitsu Limited, Kawasaki, Japan
`[73] Assignee:
`[21] App]. No.: 414,803
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`[22] Filed:
`Sep. 3, 1982
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`_
`[30]
`Foreign Application Priority Data
`sep. 10, 1931 [JP]
`Japan ................................ 56442911
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`Int. c1.3 ................. .. H01L 21/76; HOIL 21/302;
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`HOIL 21/20
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`[52] U.S. c1. ...................................... .. 29/571; 29/578;
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`29/576 w; 148/1.5; 143/175, 148/187;
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`156/643; 156/648; 156/662; 357/49
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`[53] Field of Search ............... .. 29/571, 576 R, 576 13,
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`29/576 w, 573; 148/174, 175, 187, 1.5; 357/47,
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`43, 49, 50; 156/643, 648, 653, 661.1, 662
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`References Cited
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`U.S. PATENT DOCUMENTS
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`
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`1/1969 Bean et al.
`.. . ... 156/648 X
`3,421,055
`. . . ... . ..
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`3/1973 Zoroglu . . .. .
`.. . ... 148/187
`3,719,535
`
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`8/1978 Bondur et al.
`29/576 W X
`4,104,086
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`3/1980 Khan et al.
`....... 29/S71
`4,192,059
`
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`1/1980 Ho et al.
`148/174 X
`4,209,349
`
`
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`
`
`
`...... ..
`6/1980 Ho et al.
`148/1.5 X
`4,209,350
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`2/1981 Anantha et al.
`29/578 X
`4,252,582
`
`
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`4/1981 Kumar et al.
`29/576 W X
`4,261,763
`.
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`5/1983 Ozawa ............................ .. 29/571 X
`4,385,433
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`TSMC Exhibit 1010
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`Page 1 of 15
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`U.S. Patent Mar. 26, 1985‘
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`Sheetl of7
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`4,506,434
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`Fig.2(b)
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`5/1/1141‘ 23
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`Page 2 of 15
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`U.S. Patent Mar. 26, 1985
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`Sheet2of7
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`4,506,434
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`Fig.2(d )
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`2‘
`Fig.2(e)
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`“K 24
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`Fig.2(f)
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`24
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`1/
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`Page 3 of 15
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`U.S. Patent Mar. 26, 1985U.S. Patent Mar. 26, 1985
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`Page 4 of 15Page 4 of 15
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`U.S. Patent Mar. 26, 1985
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`Sheet4of7
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`4,506,434
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`Fig. 4(c)
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`47
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`Fig.(d)
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`U.S. Patent Mar. 26, 1985U.S. Patent Mar. 26, 1985
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`Sheet5of7Sheet5of7
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`Page 6 of 15Page 6 of 15
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`U.S. PatentJ Mar. 26, 1935
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`U.S. Patent Mar. 26, 19854
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`Sheet7of7
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`Page 8 of 15
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`1
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`METHOD FOR PRODUCTION OF
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`SEMICONDUCI‘OR DEVICES
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`4,506,434
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`5
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`The present invention relates to methods for produc-
`tion of semiconductor devices, and more specifically to
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`an improvement applicable to methods for production
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`of buried insulating layers each of which surrounds a
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`portion of a semiconductor substrate in which elements
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`are fabricated, the buried insulating layers functioning
`to isolate from one another, each element fabricated in
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`a chip.
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`2. Description of the Prior Art
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`There is now a tendency irfwhich the dimensions of
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`each element is decreased in order to satisfy require-
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`ments for a larger quantity of elements fabricated in a
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`chip and also for a larger quantity of elements fabri-
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`cated in the unit area of a chip. Such requirements are
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`included in the requirements effective to satisfy the
`ultimate purposes for development of LSI’s and further
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`of VLSI’s. Insofar as the processes for isolating each
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`element fabricated in one chip from one another are
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`concerned, a process which is called local oxidation of
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`silicon is available, and it is well known that this process
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`has various advantages in the aspects of easy production
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`of durable wiring which is free from potential discontin-
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`uation thereof and the potential employment of self-
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`alignment and the like. However, this local oxidation
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`process has drawbacks. The first is the problem of bird’s
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`beak. Referring to FIG. 1, local oxidation of the top
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`surface of a silicon (Si) substrate 11, having a lirriited
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`area covered by a silicon nitride (Si3N4) layer mask 12,
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`is accompanied by lateral growth of a silicon dioxide
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`(SiO2) layer 13. This lateral growth produces a silicon
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`dioxide (SiO2) layer having a bird’s beak shape which
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`extends under the silicon nitride (Si3N4) layer 12. The
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`lateral length A of this bird’s beakcauses a degradation
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`of dimensional accuracy. The second is the problem of
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`strain which is produced in the portion B of the silicon
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`substrate 11. The portion B directly contacts the layer
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`13 of silicon dioxide (SiOz) which is converted from
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`silicon (Si) during the oxidation process which inevita-
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`bly causes expansion in volume of the nitride. This
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`strain, appearing in the silicon (Si) layer B, can cause
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`unsatisfactory characteristics in elements fabricated in
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`the silicon (Si) layer. The third is the problem of white
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`ribbon. Since it is not easy to completely remove the
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`silicon nitride (Si3N4) layer 12, numerous minute parti-
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`cles of the nitride remain on the surface of the silicon
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`(Si) substrate 11 in the form of scattered stains. These
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`residual nitride particles function as a type of mask
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`during oxidation processes carried out in later steps.
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`The above process results in a local oxidation process
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`which is not necessarily satisfactory for the production
`of a semiconductor device having minute patterns. To
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`overcome the foregoing drawbacks, a method wherein
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`each element is isolated from one another by buried
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`insulating layers which are grown to fill grooves pro-
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`duced along the surface of a silicon (Si) substrate to
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`surround each element, has been developed and is pres-
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`ently being used. Unfortunately, however,
`this im-
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`proved method has other drawbacks described below,
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`with reference to the drawings.
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`2
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`this
`Depending on the etching process employed,
`improved prior art method is classified into two inde-
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`pendent categories.
`The first is the case wherein a dry etching process is
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`employed. Referring to FIG. 2(a), the first step is to
`employ a chemical vapor deposition process for the
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`purpose of growing an insulating layer 22 on a silicon
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`(Si) substrate 21 which is provided with grooves 23
`surrounding mesa shaped portions 24 in which elements
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`are to be fabricated, before a photoresist layer 25 is
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`coated on the uneven surface of the insulating layer 22.
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`As a result, the top surface of the photoresist layer 25
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`becomes flat. Referring to FIG. 2(b), the second step is
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`to employ a dry etching process which has a single
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`etching rate regardless of the quality of the material to
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`be etched, to the substrate 21 covered by the insulating
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`layer 22 and by the photoresist layer 25. As a result, the
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`insulating layer 22 remains only in the groove 23, and
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`the top surface of the silicon (Si) substrate 21 becomes
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`uncovered. During this process, however,
`the ion
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`beams employed for the dry etching process readily
`produce damaged areas C along the top surface of the
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`mesa shaped portion 24 of the silicon (Si) substrate 21 in
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`which elements are to be fabricated. These damaged
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`areas can cause unsatisfactory characteristics for ele-
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`ments fabricated in the substrate 21. It is quite natural
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`that the silicon (Si) substrate must be exposed to a plu-
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`rality of high temperature processes such as oxidation
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`and annealing for repairing the damage caused by appli-
`cation of ion implantation processes and the like, during
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`later processes for production of elements therein. Re-
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`ferring to FIG. 2(c), since the foregoing high tempera-
`ture processes are involved with non-uniform variation
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`of density of the insulating layer 22, this variation causes
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`strains E1 and/or E2 to occur at the corners of the mesa
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`shaped portion 24 of the substrate 21 surrounded by the
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`buried insulating layer 22. These strains are also param-
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`eters for causing unsatisfactory characteristics for ele-
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`ments fabricated in the substrate 21.
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`The second is the case wherein a wet etching process
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`is employed. Referring to FIG. 2(d), the first step is to -
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`employ a dry etching process to remove the photoresist
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`layer 25 from the areas on which elements are to be
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`fabricated, leaving the photoresist layer 25 only along
`the grooves. Referring to FIG. 2(e), the second step is
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`to employ a wet etching process to remove the insulat-
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`ing layer 22 from the areas on which elements are to be
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`fabricated, leaving the insulating layer 22 only in the
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`grooves 23. Since the grooves 23 have sharp corners at
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`the bottom and top edges, the density of the insulating
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`layer 22 is not entirely uniform and the density thereof
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`is less along the broken lines shown in each of FIGS.
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`2(a), 2(b), 2(d) and 2(e) than in the other regions. Since
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`a material having a lower density has a larger etching
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`rate, recesses D are produced along the edges of the
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`insulating layers 22 which are buried in the silicon (Si)
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`substrate 21. As a result, the surface of a chip is not flat,
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`causing the possibility of discontinuity and/or‘dimen-
`sional errors for wires which are placed along the sili-
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`con (Si) substrate 21.
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`To prevent occurrence of the foregoing recesses D
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`along the edges of the insulating layer 22, an annealing
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`process is ordinarily employed after the completion of
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`the insulating layer 22. Albeit this annealing process is
`effective to unify or make uniform the density of the
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`insulating layer 22 even in the portions along the broken
`lines shown in FIG. 2, differences in the amount of the
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`coefficient of expansion between the material of the
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`65
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`Page 9 of 15
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`Page 9 of 15
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`4,506,434
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`3
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`substrate and the material of the insulating layer causes
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`stresses to occur along the interfaces of both materials,
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`since the stresses are concentrated along the edges. As a
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`result, strains E1and/or E2 occur along the edges of the
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`element fabrication areas of the substrate 21 surrounded
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`by the buried insulating layer 22 in FIG. 2(f). These
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`strains are also parameters for causing unsatisfactory
`characteristics for elements fabricated in the substrate
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`21.
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`4
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`duction of a semiconductor device in accordance with
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`the present invention. Since a thermal strain absorbing
`layer 32 is interleaved between the top surface of a
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`semiconductor substrate 31 and an insulator layer 33
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`except for the area which is to become a buried insulat-
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`ing layer, strains E1 occur along the edges of the ther-
`mal strain absorbing layer 32 rather than along the top
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`edges of the element fabrication areas of the semicon-
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`ductor substrate 31, during an annealing process which
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`is carried out to make uniform the density of the insulat-
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`ing layer 33. During a dry etching process which is
`carried out to remove a portion of the insulating layer
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`33, damaged areas G are produced in the thermal strain
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`absorbing layer 32 rather than in the semiconductor
`substrate 31. As a result, the portions of the semicon-
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`ductor substrate 31 in which elements are to be pro-
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`duced are protected from potential strains and damage,
`thereby enabling the characteristics of the elements to
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`be enhanced. Since the strains E1 do not occur in the
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`semiconductor substrate 31 and since the magnitude of
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`stress which may cause strains E2 is limited, the amount
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`of strains E2 which occurs along the bottom edges of
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`the element fabrication areas 34 of the semiconductor
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`substrate surrounded by the buried insulating layers is
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`also decreased.
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`The requirements for the thermal strain absorbing
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`layer are (a) that the material will have to be chemically
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`stable under an annealing temperature of approximately
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`900“ C. or higher and (b) that the material readily ab-
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`sorbs strains. Exemplary materials satisfying these re-
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`quirements are polycrystalline silicon (Si), molybdenum
`silicide (MoSi2), tungsten silicide (WSi2), titanium sili-
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`cide (TiSi2) and tantalum silicide (TaSi2).
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`Silicon dioxide (SiO2), silicon nitride (Si3N4) and
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`aluminum oxide (A1203) can be selected as the material
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`of the buried insulating layer.
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`Not only silicon (Si) but also any of the compound
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`semiconductors including galium-arsenic (GaAs), indi-
`um-phosphorus (InP) et al can be selected as the mate-
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`rial of the semiconductor substrate.
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`To achieve the foregoing second object, a method for
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`production of a semiconductor device in accordance
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`with the other embodiment of the present invention
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`comprises, in addition to the steps specified above for
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`the method for production of a semiconductor device in
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`accordance with the present invention, a step to pro-
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`duce a conductive layer on the thermal strain absorbing
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`layer and on the buried insulating layer and a step to
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`pattern the conductive layer to a shape corresponding
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`to the gate electrode and some of the conductive wires.
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`Materials selected as a material for the conductive
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`layer are molybdenum silicide (MoSi2), tungsten silicide
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`(WSi2),
`titanium silicide
`(TiSi2),
`tantalum silicide
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`(TaSi2) and polycrystalline silicon (Si).
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`The present invention, together with its various fea-
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`tures and advantages, can be readily understood from
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`the following more detailed description presented in
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`conjunction with the following drawings.
`FIG. 1 is a cross-sectional view of a silicon (Si) sub-
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`strate showing the position after the completion of a
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`prior art local oxidation process.
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`FIGS. 2(a), 2(b), 2(c), 2(d), 2(e) and 20‘) are cross-sec-
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`tional views of silicon (Si) substrates, each of which
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`shows the state after the completion of each of the
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`major steps of a method for production of a buried
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`SUMMARY OF THE INVENTION
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`An object of the present invention is to provide a
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`method for producing a semiconductor device having a
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`plurality of elements each of which is isolated from one
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`another by buried insulating layers, wherein an im-
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`provement is made (a) to prevent strains E1 which may
`otherwise occur along the top edges of the element
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`fabrication areas of the semiconductor substrate sur-
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`rounded by buried insulating layers which function to
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`isolate each element from one another, from occurring
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`during an axmealing process which is carried out to
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`unify the density of the insulating layer, (b) to decrease
`the amount of strains E2 which occur along the bottom
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`edges of the element fabrication areas of the semicon-
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`ductor substrate surrounded by buried insulating layers
`which function to isolate each element from one an-
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`other during the annealing process which is carried out
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`to unify the density of the insulating layer and (c) to
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`prevent damaged areas C which may otherwise be pro-
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`duced along the element fabrication areas of a semicon-
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`ductor substrate surrounded by buried insulating layers,
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`from being produced during a dry etching process
`which is carried out to remove a part of the insulating
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`layer which is grown on the semiconductor substrate
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`leaving the other part of the insulating layer in grooves
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`surrounding the element fabrication areas of the semi-
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`conductor substrate, the remaining part of the insulating
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`layer being the buried insulating layer which functions
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`as an isolation region.
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`The other object of the present invention is to pro-
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`vide a method for production of a semiconductor de-
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`vice having a plurality of elements each of which has
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`satisfactory quality due to lack of damage in the element
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`fabrication areas of the semiconductor substrate sur-
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`rounded by buried insulating layers which function to
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`isolate each element from one another, wherein an im-
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`provement is made to simplify the steps for production
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`of wiring.
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`To achieve the foregoing first object, a method for
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`production of a semiconductor device in accordance
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`with the present invention comprises a step of growing
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`a thermal strain absorbing layer on at least a portion of
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`the top surface of a semiconductor substrate, the por-
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`tion being an area which is not an area which becomes
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`an isolation area, a step of producing at least one groove
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`along said area which becomes an isolation area, a step
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`of inlaying an insulator in said at least one groove, and
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`a step of annealing said insulator.
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`The concept of the present invention is to interleave
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`a thermal strain absorbing layer between the top surface
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`of a semiconductor substrate and an insulating layer, of
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`which a part is to become a buried insulating layer, for
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`the purpose of allowing the thermal strain absorbing
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`layer to absorb strains which may otherwise occur due
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`to an annealing process and to prevent damage which
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`may otherwise be produced by irradiation of ion beams.
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`FIG. 3 shows the cross-sectional view of a semicon-
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`ductor device produced employing a method for pro-
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`10
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`15
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`20
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`25
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`30
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`35
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`45
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`50
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`55
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`60
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`65
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`Page 10 of 15
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`Page 10 of 15
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`

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`4,506,434
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`5
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`25
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`30
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`5
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`insulating layer which functions as isolation, according
`to the prior art.
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`FIG. 3 is a cross-sectional view of a semiconductor
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`device produced employing a method for production of
`a semiconductor device in accordance with the present
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`invention.
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`FIGS. 4(a), 4(b), 4(c), 4(d) and 4(2) are cross-sectional
`views of silicon (Si) substrates, each of which shows the
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`state after the completion of each of the major steps of
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`a method for production of a semiconductor device in
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`accordance with one embodiment of the present inven-
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`tion.
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`FIGS. 5(a), 5(b) and S(c) are cross-sectional views of
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`silicon (Si) substrates, each of which shows the state
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`after the completion of each of the major steps of a
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`method for production of a semiconductor device in
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`accordance with another embodiment of the present
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`invention.
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`FIG. 6 is a cross-sectional view of a complementary
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`MOS (C-MOS) semiconductor device produced em-
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`ploying a method of production in accordance with a
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`third embodiment of the present invention.
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`FIGS. 7(a) and 7(b) are cross-sectional views, of
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`which the former and the latter respectively show an
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`intermediate state of and the state after the completion
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`of a process for production of a 1-transistor and 1-
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`capacitor type dynamic random access memory cell in
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`accordance with a fourth embodiment of the present
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`invention.
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`FIGS. 8(a) and 8(b) are cross-sectional views, of
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`which the former and the latter respectively show an
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`intermediate state of and a state after the completion of
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`a process for production of a bipolar type integrated
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`circuit device in accordance with a fifth embodiment of
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`35
`the present invention.
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`DETAILED DESCRIPTION OF THE
`
`
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`PREFERRED EMBODIMENTS
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`In the following description, one of each embodiment
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`in accordance with the present invention will be pres- 40
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`ented, on the assumption that FET’s are produced in a
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`silicon substrate, such FET’s being isolated from one
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`another by buried insulating layers each of which sur-
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`rounds each of the FET-s.
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`The first embodiment is a method for production of a 45
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`semiconductor device having a plurality of FET’s, each
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`of which is fabricated in an element fabrication area of
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`a silicon (Si) substrate surrounded by a buried insulating
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`layer, wherein an improvement is realized in which a
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`thermal strain absorbing layer of polycrystalline silicon
`(Si) is interleaved between the substrate and the insulat-
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`ing layer such that the polycrystalline silicon (Si) layer
`absorbs potential strains and damage which may other-
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`wise occur in the silicon (Si) substrate. This embodi-
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`ment will be presented, referring to FIGS. 4(a), 4(b),
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`4(c), 4(d) and 4(e).
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`Referring to FIG. 4(a), the top surface of a silicon (Si)
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`substrate 41 is oxidized to produce a silicpn dioxide
`(SiO2) layer 42 having a thickness of 500 A, before a
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`60
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`polycrystalline silicon (Si) layer 43 having a thickness of
`1,000 A is grown on the silicon dioxide (SiO2) layer 42.
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`The function of the silicon dioxide (SiO2) layer 42 is to
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`make it easy to remove the polycrystalline silicon (Si)
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`layer 43 in a later step. In other words, it functions to
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`solve the difficulty in removing the polycrystalline
`silicon (Si) layer 43 when it is produced directly on the
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`silicon (Si) substrate 41, which is, of course, a material
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`identical to the layer. The function of the polycrystal-
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`6
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`line silicon (Si) layer 43 is to absorb, strain and damage.
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`Therefore, this layer 43 can be replaced by a molybde-
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`num silicide (MoSi2) layer, a tungsten silicide (WSi2)
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`layer, a titanium silicide (TiSi2) layer, a tantalum silicide
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`(TaSi2) layer or the like, insofar as the annealing tem-
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`perature range is 900° through l,l0O° C. This is because
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`these materials are stable from the chemical viewpoint
`in the foregoing temperature range and readily absorb
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`strains. A photoresist layer 44 is produced on the sur-
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`face of polycrystalline silicon (Si) layer 43, before a
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`patterning process is applied to the photoresist layer 44
`for the purpose of producing grooves along the area
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`corresponding to the area in which a buried insulating
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`layer is produced. A thickness of the layer 43 is thicker
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`than 500 A for absorb.
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`the patterned photoresist
`Referring to FIG. 4(b),
`layer 44 functions as a mask during a parallel plate type
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`reactive ion etching process applied to the substrate for
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`the purpose of partly removing the polycrystalline sili-
`con (Si) layer 43, the silicon (Si) substrate 41 for the
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`ultimate purpose to produce grooves 45 having the
`depth of 6,500 A in the silicon (Si) substrate 41. A car-
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`bon fluoride (CF4) gas containing oxygen (02) by 5% is
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`employed as the reactive gas and an etching rate of 200
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`A/min. is realized at a pressure of 5 X 10-3 Torr. After
`the photoresist layer 44 is entirely removed, a low pres-
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`sure chemical vapor deposition process is employed to
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`grow a silicon dioxide (SiO2) layer 47 having a thick-
`ness of 8,000 A which entirely covers the top surface of
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`the substrate 41. Thereafter, the substrate is subjected to ,
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`an annealing process for 20 minutes in the nitrogen (N2)
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`gas at a temperature of l,000° C. for the purpose of
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`unifying or making uniform the density of the silicon
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`dioxide (SiO2) layer 47. Albeit strains may occur in the
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`polycrystalline silicon (Si) layer 43 during this process,
`the entire portion of the silicon (Si) substrate 41 is main-
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`tained free from strains. In other words, potential strains
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`which might otherwise occur along the edges of the
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`element fabrication area 46 of the silicon (Si) substrate
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`41 surrounded by the buried insulating layer 47, are
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`absorbed by the polycrystalline silicon (Si) layer 43.
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`The top surface of the silicon dioxide (SiO2) layer 47 is
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`coated by a photoresist layer 48 of e.g. AZl350J pro-
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`duced and marketed by Shipley Company Inc. of the
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`U.S.A. and the top surface of the photoresist layer 48
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`becomes flat.
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`Referring to FIG. 4(c), a dry etching process is ap-
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`plied to the substrate until the top surface of the poly-
`crystalline silicon (Si) layer 43 is exposed. An argon
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`(Ar) gas at a pressure of 7n>< 10-4 Torr. is employed and
`an etching rate of 500 A/min.
`is realized. Although
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`damage may occur in the polycrystalline silicon (Si)
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`layer 43, during this process, the entire silicon (Si) sub-
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`strate 41 is protected from damage. This means that
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`potential damages which might be otherwise be pro-
`duced along the edges of the element fabrication area 46
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`of the silicon (Si) substrate 41 surrounded by the buried
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`insulating layer 47, are absorbed by the polycrystalline
`silicon (Si) layer 43.
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`Referring to FIG. 4(d), a dry etching process is ap-
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`plied to the substrate to remove only the upper portion
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`of the silicon dioxide (SiO2) layer 47 by a depth corre-
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`sponding to the thickness of the polycrystalline silicon
`(Si) layer 43. A trifluoromethane (CHF3) gas at a pres-
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`sure of 0.05 Torr. is employed and an etching rate of 800
`A/min. is realized.
`—
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`Referring to FIG. 4(e), a plasma etching process em-
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`ploying a carbon fluoride (CF4) gas containing 5% of
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`50
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`55
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`65
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`Page 11 of 15
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`Page 11 of 15
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`4,506,434
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`7
`oxygen (02) at a pressure of 1 (one) Torr. is applied to
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`thesubstrate to remove the polycrystalline silicon (Si)
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`layer 43 at an etching rate of 500 A/min. Thereafter, a
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`hydrogen fluoride (HF) solution is brought into contact