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`US005702976A
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`United States Patent
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`Schuegraf et al.
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`[19]
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`an PatentvNumber:
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`[45] Date of Patent:
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`5,702,976
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`Dec. 30, 1997
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`[54] SHALLOW TRENCH ISOLATION USING
`now DIELECTRIC CONSTANT INSULATOR
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`[75]
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`Inventors: Klaus F. Schuegmf; Aftab Ahmad,
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`both of Boise, Id.
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`[73] Assignee: Micron Technology, Inc., Boise. Id.
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`4,824,797
`5,429,995
`5,492,736
`5530.293
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`4/1989 Goth
`"1995 Nishiyama et
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`211996 Laxman et al.
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`6/1995 Cohm 8! a1-
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`.
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`437167
`437/238
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`427/579
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`257/752
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`P'i'"0’Y EW"""'¢"‘-T1'|"18 D338
`Attorney, Agen; or Firm—Knobbe. Martens. Olson & Bear.
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`[LP-
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`ABSTRACT
`[57]
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`A shallow trench isolation is disclosed wherein the trench
`depth is reduced beyond that achieved in prior an processes-
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`The reduced wench depth helps to eliminate the formation of
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`Voids during _th=_trcnch rcfil} prodcss and provides _for
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`greater plananty In the final isolation structure. Effective
`device isolation is achieved with a reduced trench depth by
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`utilizing refilling dielecuic materials having low dieleclric
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`constant
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`Appl. No.: 547,620
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`[22] Filed:
`Oct. 24, 1995
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`[51]
`Int. Cl.‘ ..........
`us. Cl.
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`H0lL 2lfl6
`357737; 437/240; 437/238;
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`143/D1G_ 50
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`437/64. 65, 67,
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`437/23g_ 240; 143/DIG 50
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`[58] Field of Search
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`[55]
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`4,502,914
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`Refemnces Cited
`U.S. PATENT DOCUMENTS
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`3/1985 Tmmpp et al.
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`437/67
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`22 Claims, 4 Drawing Sheets
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`‘£7’ S’
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`r §.4.1E//
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`TSMC Exhibit 1009
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`Page 1 of 9
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`//W//
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`Page 2 of 9
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`Page 3 of 9
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`U.S. Patent
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`Dec. 30, 1997
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`Sheet 3 of 4
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`5,702,976
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`ré’t'9r3/1
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`22
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`2.?
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`22
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`%////%
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`Page 4 of 9
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`Page 4 of 9
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`U.S. Patent
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`Dec. 30, 1997
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`Sheet 4 of 4
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`5,702,976
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`22
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`‘r
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`Page 5 of 9
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`Page 5 of 9
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`25
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`1
`SHALLOW TRENCH ISOLATION USING
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`LOW DIELECTRIC CONSTANT INSULATOR
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`FIELD OF THE INVENTION
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`The invention relates generally to silicon integrated cir-
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`cuit design and process technology. In particular, the inven-
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`tion pertains to trench isolation process technology.
`BACKGROUND OF THE INVENTION
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`Implementing electronic circuits involves connecting iso-
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`lated devices through specific electronic paths. In silicon
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`integrated circuit fabrication it is necessary to isolate devices
`from one another which are built into the same silicon
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`matrix. They are subsequently interconnected to create the
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`desired circuit configuration. In the continuing trend toward
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`higher device densities, parasitic interdevice currents
`become more problematic, thus isolation technology has
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`become one of the most critical aspects of contemporary
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`integrated circuit fabrication.
`Over the last few decades a variety of successful isolation
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`technologies have been developed to address the require-
`ments of different integrated circuit types such as NMOS,
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`CMOS and bipolar. In general, the various isolation tech-
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`nologies exhibit difierent attributes with respect to such
`characteristics as minimum isolation spacing, surface
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`planarity, process complexity and defect density generated
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`during isolation processing. Moreover, it is common to trade
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`tion process for a particular integrated circuit application.
`In metal-oxide-semiconductor (MOS) technology it is
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`necessary to provide an isolation structure that prevents
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`parasitic channel formation between adjacent devices, such
`devices being primarily NMOS or PMOS transistors or
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`CMOS circuits. The most widely used isolation technology
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`for MOS circuits has been that of LOCOS isolation, an
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`acronym for LOCal Oxidation of Silicon. LOCOS isolation
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`essentially involves the growth of a recessed or semito-
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`cessed oxide in unmasked non-active or field regions of the
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`silicon substrate. This so-called field oxide is generally
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`grown thick enough to lower any parasitic capacitance
`occurring over these regions, but not so thick as to cause step
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`coverage problems. The great success of LOCOS isolation
`technology is to a large extent attributed to its inherent
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`simplicity in MOS process integration, cost eflectiveness
`and adaptability.
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`In spite of its success, several limitations of LOCOS
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`technology have driven the development of alternative iso-
`lation structures. A well-known limitation in LOCOS isola-
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`tion is that of oxide undergrowth at the edge of the mask
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`which defines the active regions of the substrate. This
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`so-called bird's beak (as it appears) poses a limitation to
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`device density, since that portion of the oxide adversely
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`influences device performance while not significantly con-
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`tributing to device isolation. Another problem associated
`with the LOCOS process is the resulting circuit planarity or
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`lack thereof. For submicron devices, planarity becomes an
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`important issue, often posing problems with subsequent
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`layer conformality and photolithogmphy.
`Trench isolation technology has been developed in part to
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`overcome the aforementioned limitations of LOCOS isola-
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`tion for submicron devices. Refilled trench structures essen-
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`tially comprise a recess formed in the silicon substrate which
`is refilled with a dielectric material. Such structures are
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`fabricated by first forming submicron-sized trenches in the
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`silicon substrate, usually by a dry anisotropic etching pro-
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`cess. The resulting trenches typically display a steep side-
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`wall profile as compared to LOCOS oxidation. The trenches
`are subsequently refilled with a dielectric such as chemical
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`vapor deposited (CVD) silicon dioxide (SiO2). They are then
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`planaxized by an etchback process so that the dielectric
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`remains only in the trench, its top surface level with that of
`the silicon substrate. The etchback process is often per-
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`formed by etching photoresist and the deposited silicon
`dioxide at the same rate. The top surface of the resist layer
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`is highly planarized prior to etchback through application of
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`two layers of resist, and flowing the first of these layers.
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`Active regions wherein devices are fabricated are those that
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`were protected from etch when the trenches wae created.
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`The resulting structure functions as a device isolator having
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`excellent planarity and potentially high aspect ratio benefi-
`cial for device isolation. Refilled t:rench isolation can take a
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`variety of forms depending upon the specific application;
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`they are generally categorized in terms of the trench dimen-
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`sions: shallow trenches (<1 pm), moderate depth trenches
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`(1-3 pm), and deep, narrow trenches (>3 um deep, Q mu
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`wide). Shallow Trench Isolation (STI) is used primarily for
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`isolating devices of the same type and is often considered an
`alternative to LOCOS isolation. Shallow trench isolation has
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`the advantages of eliminating the birds beak of LOCOS and
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`providing a high degree of smface planarity.
`The basic trench isolation process is, however, subject to
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`drawbacks, one of these being void formation in the trench
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`during dielectric refill. Such voids are formed when the
`refilling dielectric material forms a constriction near the top
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`of a trench, preventing flow of the material into the trench
`interior. Such voids compromise device isolation as well as
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`the overall structural integrity. Unfortunately, preventing
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`void formation during trench refill often places minimum
`size constraints on the trenches themselves, which may
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`compromise device packing density or device isolation. For
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`example, a key parameter measuring device isolation is the
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`field threshold voltage between adjacent devices, that is. the
`voltage necessary to create a parasitic channel beneath a
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`field oxide region linking adjacent devices. The field thresh-
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`old voltage is influenced by a number of physical and
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`material properties of the trench isolator such as insulator
`thickness, dielectric constant c, substrate doping, field
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`implant dose and substrate bias. Thus, a principal difiiculty
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`in decreasing the trench depth is the compromise in device
`isolation. Clearly, it is highly desirably to develop a shallow
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`trench isolation process which overcomes the problem of
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`void formation while providing effective device isolation.
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`SUMM.ARY OF THE INVENTION
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`It is an object of the present invention to provide a trench
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`isolation process which alleviates the problem of void
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`formation during dielectric refill. It is another object of the
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`present invention to provide a trench isolator having reduced
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`dimensions, advantageous for device density and wafer
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`planarity. It is a further object of the present invention to
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`provide a shallow trench isolator having enhanced device
`isolation characteristics.
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`In accordance with one aspect of the present invention. a
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`process for isolating devices on a semiconductor substrate
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`comprises first removing portions of the semiconductor
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`substrate,
`thereby forming recesses preferably having a
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`trench profile. The trenches are then refilled with a material
`having a dielectric constant lower than the dielectric con-
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`stant of silicon dioxide which is about 3.9. Using a low-
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`edielectric material allows the trench dimensions to be
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`reduced while still providing effective device isolation char-
`acteristics. Preferably, the dielectric material comprises a
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`halide-doped glass such as Fluorine-doped SiO2. To insure
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`5,702,976
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`Page 6 of 9
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`against device contamination, the invention further com-
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`prises forrning a barrier Layer over the trenches prior to
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`refilling them with the low-edielectric material.
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`In accordance with another aspect of the present
`invention, an isolation stucture in a semiconductor substrate
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`comprises a recessed tench formed in the semiconductor
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`substrate and a material having a low dielectic constant
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`filling the tench. The tench stucture preferably has a depth
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`less man 250 nm, and furthermore comprises a barrier layer
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`disposed between the interior tench surface and me dielec-
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`tic material. The dielectric material preferably has a dielec-
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`tic constant lower man about 3.9, and may comprise a
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`Fluoride-doped silicon dioxide composition.
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`In accordance with yet another aspect of the present
`invention, a method of reducing the formation of voids in a
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`refilled tench isolation process comprises forming trenches
`having an aspect ratio less than about 2:1, and men refilling
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`the trenches with a material having a dielectric constant less
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`man the dielectic constant of silicon dioxide. The tenches
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`preferably have a depth of less than 200 nm, and are refilled
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`with a material comprising a Fluorine-doped silicon dioxide
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`composition.
`These and other aspect and attributes of the present
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`invention will become more fully apparent with the follow-
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`ing detailed description and accompanying figures.
`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIGS. lA—lC are schematic sections illustrating an exem-
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`plary shallow tench isolation process.
`FIG. 2 is a schematic section of a tench refill having a
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`void.
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`FIG. 3 is a schematic section illustating an embodiment
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`of the present shallow tench isolation process.
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`DETAILED DESCRIPTION OF THE
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`INVENTION
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`In accordance with the principles of the present invention,
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`an improved shallow tench isolation technology utilizes a
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`tench that is shallower than prior art trenches, and yet
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`provides the same degree of device isolation. The shallower
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`tench helps prevent the formation of voids during dielectric
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`refill. However, despite the smaller dimensions of the
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`present
`inventive tench, equivalent device isolation is
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`achieved through use of a dielectric refill having a lower
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`dielectric constant e than in prior an isolation trenches. To
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`better illustrate these inventive principles, a brief description
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`of an exemplary S'I‘I process is provided first hereinbelow.
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`An exemplary S'II process may comprise first a masking,
`patterning and dry etch process, producing trenches in the
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`silicon substrate as shown in FIG. 1A. The semiconductor
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`substrate 10 is masked and patterned to expose the regions
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`of the substrate to be etched. ‘The mask 12 may for example
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`comprise a resist layer which is resistant to the dry aniso-
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`tropic etch used to create the tenches. The mask 12 may be
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`patterned by conventional photolithographic means to define
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`the regions of the substrate 10 to have trenches formed
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`thmein. The tenches 14 are formed by an anisotropic dry
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`etch, such as a plasma or reactive ion etch. A preferred
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`characteristic of the tenches 14 is the steep sidewall profile
`as compared to conventional LOCOS processes.
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`After the trenches 14 are formed, the mask 12 is removed
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`by selective etching or chemical mechanical polishing and
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`the trenches are refilled with a dielectric material 16, as
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`shown in FIG. 1B. A preferred dielectric refill material for
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`SP1 is chemical vapor deposited silicon dioxide (CVD-Si0,)
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`due to its high quality and excellent conformality. Confor-
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`mality is particularly important because the refilled material
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`must be supplied to fill trenches having relatively high
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`aspect ratios (height:widm>1).
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`Following the tench refill 16, the top surface of the
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`substrate 10 is planarized by an etchback process, typically
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`also performed using a chemicallmechanical polish. Prior to
`etchback. the substate 10 may be coated with a layer of
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`photoresist (not shown) in order to provide a planar surface
`with which to begin the etchback. The etchback itself
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`provides a planarized substrate surface 18, having dielectric
`material 16 filling the trenches 14 up to and level with the
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`top surface 18.
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`As shown in FIG. 2, a common problem associated with
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`tench refill
`isolation is the formation of voids in the
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`trenches. During refill of the tench 14 with dielectic
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`material 16, the tench 14 often becomes constricted near the
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`top of the tench, mereby preventing complete refill of the
`tench, resulting in a void 20. The void 20 lowers the
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`isolation characteristics of the refilled tench in addition to
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`introducing structural instabilities in subsequent processes.
`Increasing the tench width can alleviate void formation,
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`however it also undesirably decreases device density.
`In accordance with the principles of the present invention,
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`void formation is alleviated by decreasing tench depth.
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`Utilizing shallower tenches decreases the possibility of void
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`formation and favorably increases surface planarity of the
`final refilled trench structure. For example in a typical
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`DRAM application, a tench in accordance with the present
`invention may have dimension of approximately 200 nm
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`deep and 250 nm wide while prior art trenches typically have
`dimensions of approximately 275 nm deep and 350 nm
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`wide. However, as is well known in the art, a key parameter
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`measuring device isolation is the field threshold voltage
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`between adjacent devices, that is, the voltage necessary to
`create a parasitic channel beneath a field oxide region
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`linlcing adjacent devices. The field threshold voltage is
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`influenced by a number of physical and material properties
`of the tench isolator such as insulator thiclmess, dielectic
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`constant a, substrate doping, field implant dose and substrate
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`bias. Thus, a principal dilficulty in decreasing the tench
`depth is the compromise in device isolation.
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`To circumvent this problem, the shallow tench isolation
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`of the present invention maintains effective device isolation
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`in a shallower tench by utilizing dielectic materials having
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`a lower dielectric constant than used in the prior art. For a
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`given tench geometry,
`the field threshold voltage is a
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`decreasing fundion of the field dielectric constant. Thus, to
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`compensate for smaller tench dimensions,
`the present
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`invention utilizes dielectic materials having lower dielectric
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`constant. A possible dielectic material is a low index glass
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`such as a halide-doped silicon dioxide, deposited by into-
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`ducing the halide during CVD of silicon dioxide. For
`example, F:SiO, possesses a dielectric constant of approxi-
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`mately 3.2, while typical CVD—SiO2 has a dielectric constant
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`of about 3.9. Use of such materials allows arelative decrease
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`in tench depth by about 20%.
`Fluorine or other elements comprising a reduced dielec-
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`tric constant material may however cause deleterious effects
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`on neighboring devices if they diffuse into adjacent active
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`areas. Therefore, a preferred embodiment of the present
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`invention also incorporates a diffusion barrier layer lining
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`the tench so as to prevent dopant migration into the silicon
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`substate. Use of a preferred barrier layer in the form of a
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`grown oxide or nitide film. or a deposited stoichiometric or
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`non-stoichiometric oxide or nitride film inhibits contamina-
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`tion of the isolation field—efl’eet tansistor, thereby preserving
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`desirable characteristics such as a high mreshold voltage.
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`The integrated devices subject to isolation are also protected
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`by the barrier layer from contamination.
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`In accordance with the aforementioned principles, a pre-
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`ferred shallow trench isolation may for example comprise
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`the following process steps illustated in FIGS. 3A—3D. As
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`shown in FIG. 3A, the silicon wafer 10 is first covued by a
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`Page 7 of 9
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`mask 12, such as a resist or silicon oxide/nitride bilayer, and
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`then patterned and etched to define the field isolation
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`regions. The wafer is then subject to a dry anisotropic etch
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`such as a halide plasma complex, thereby forming the
`trenches 22 in the silicon substrate 10. As mentioned earlier,
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`in comparison to the prior art trench isolation, the trenches
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`of the present invention are about 200 nm deep, shallower
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`than the prior art by about 20%.
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`As mentioned previously, to avoid contamination of sub-
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`strate regions adjacent to the trenches 22, it is preferable to
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`form a barrier layer 24 over the trenches 22 prior to
`dielectric refill as shown schematically in FIG. 3B. The
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`barrier layer 24 may for example comprise a silicon oxide or
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`nitride film grown in an appropriate ambient or a chemical
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`vapor deposited oxide or nitride film at least 5 nm thick. The
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`barrier layer 24 functions to prevent difiusion of dopants
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`deposited during the subsequent dielectric refill process.
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`Although in general nitride forms a superior dilfusion barrier
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`to oxide, the higher dielectric constant of nitride should be
`considered in the overall isolation sn'ucture. It may be for
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`that oxide performs adequately as a ditfusion
`example.
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`barrier while having the advantage of a lower dielectric
`constant than nitride. Thus, barrier layer thickness and
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`dielectric constant should be considered in the overall trench
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`design.
`A shown in FIG. 3C, the trenches 22 are refilled with a
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`dielectric material 26 having a low dielectric constant e of
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`about 3.3. As mentioned previously,
`the use of a low
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`dielectric constant material lowers the gate capacitance of
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`the isolation field-efiect transistor,
`thereby raising the
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`threshold voltage. A CVD-Si02 doped with a halide such as
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`Fluorine is a presently preferred material.
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`To complete the trench structure, a planarizing step is
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`performed as shown in FIG. 3D. A planarizing process may
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`for example comprise depositing and reflowing a resist layer
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`to attain a planar top surface, followed by an etchback
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`procedure to remove material down to the substrate surface.
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`While the planarizing process may proceed in accordance
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`with well-known processes, the present preferred isolation is
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`advantageous because the shallower trench structures and
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`consequent thinner refilled layers allow for a greater degree
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`of planarity.
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`Thus. the present invention provides several advantages
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`over the prior art by avoiding cavities in the trenches,
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`providing more effective device isolation using low-e mate-
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`rials and having a greater degree of planarity in the final
`trench struwure.
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`Although described above with reference to the preferred
`embodiments, modifications.within the scope of the inven-
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`tion may be apparent to those slcilled in the art, all such
`modifications are intended to be within the scope of the
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`appended claims.
`What is claimed is:
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`1. A process for isolating devices on a semiconductor
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`substrate comprising the steps of:
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`removing predetermined portions of the semiconductor
`substrate forming recesses therein; and
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`refilling the portions of the semiconductor substrate with
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`a material comprising an in situ doped silicon oxide
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`complex,
`the material having a dielectric constant
`lower than the dielectric constant of undoped silicon
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`dioxide.
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`2. The process of claim 1, wherein the step of removing
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`portions of the semiconductor wafer comprises forming
`trenches in the semiconductor wafer.
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`3. The process of claim 2. wherein the trenches have a
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`depth of less than 200 nm.
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`6
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`4. 'll1e process of claim 3, wherein the trenches have an
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`aspect ratio of less than 2:1.
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`5. A process for isolating devices on a semiconductor
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`substrate comprising the steps of:
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`removing predetermined portions of the semiconductor
`substrate forming recesses therein; and
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`refilling the portions of the semiconductor substrate with
`a material having a dielectric constant lower than the
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`dielectric constant of silicon dioxide,
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`wherein the material having a dielectric constant lower than
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`that of silicon dioxide comprises a halide-doped silicon
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`dioxide composition.
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`6. The process of claim 5, wherein the halide-doped
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`silicon dioxide complex comprises a Fluorine-doped silicon
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`dioxide complex.
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`7. The process of claim 1, wherein the refilling material
`has a dielectric constant less than about 3.9.
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`8. The process of claim 1. further comprising forming a
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`barrier layer over the semiconductor substrate prior to the
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`step of refilling portions of the semiconduaor substrate.
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`9. The process of claim 8, wherein the barrier layer
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`comprises a silicon dioxide composition.
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`10. The process of claim 8. wherein the barrier layer
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`comprises a silicon nitride composition.
`11. A method of reducing the formation of voids in a
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`refilled trench isolation process comprising the steps of:
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`forming trenches having an aspea ratio less than 221;
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`refilling the trenches with an insulating material; and
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`halide-doping the material.
`12. The method of claim 11, wherein the trenches have a
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`depth of less than 200 nm.
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`13. A method of reducing the formation of voids in a
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`refilled trench isolation process comprising the steps of:
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`forming trenches having an aspect ratio less than 2:1; and
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`refilling the trenches with a mataial having a dielectric
`constant less than the dielectric constant of silicon
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`dioxide,
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`wherein the refilling material comprises a Fluorine-doped
`silicon dioxide composition.
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`14. The method of claim 11, wherein the halide-doped
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`material has a dielectric constant of less than about 3.9.
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`15. The method of claim 1, wherein the material com-
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`prises a halide-doped oxide.
`16. The method of claim 1, wherein the material com-
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`prises a fluoride-doped oxide.
`17. The method of claim 11. wherein refilling fire trenches
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`comprises depositing silicon dioxide.
`18. The method of claim 17. wherein depositing silicon
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`dioxide comprises a chemical vapor deposition.
`19. The method of claim 18, wherein halide-doping the
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`mataial comprises in situ halide doping during chemical
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`vapor deposition of the material.
`20. The method of claim 11, wherein doping the material
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`comprises introducing a halide into the material while
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`refilling the trenches.
`21. The method of claim 11. wherein the halide comprises
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`fluorine.
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`22. A process for isolating devices on a semiconductor
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`substrate comprising the steps of:
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`forming trenches within the substrate;
`lining the trenches with a dilfusion barrier;
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`refilling the trenches with silicon dioxide; and
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`halide-doping silicon dioxide.
`3|!
`*
`*
`3t!
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`SR
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`5,702,976
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`
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`5
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`25
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`35
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`Page 8 of 9
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`Page 8 of 9
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`

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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`CERTIFICATE OF CORRECTION
`
`
`
`
`PATENT NO.
`: 5’702’976
`
`
`
`DATED
`
`
`
`
`
`
`; December 30, 1997
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`"WEN1-OR(S) 1 Klaus Schuegraf Afiab Ahmad
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`It is certified that error appears in the above-indentified patent and that said Letters Patent is hereby
`corrected as shown below:
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`On the title page item [57],
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`In the Abstract,I.ine3, delete “wench” and insert —-trench-—.
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`Attest:
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`Signed and Sealed this
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`Twenty-third Day of June, 1998
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`BRUCE LEHMAN
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`AfI€S!ing Oflicer
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`Commissioner of Patents and Trademarks
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`Page 9 of 9
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`Page 9 of 9