United States Patent
`Lee et al.
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`USOOSISS 145A
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`Patent Number:
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`Date of Patent:
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`5,153,145
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`Oct. 6, 1992
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`[73] Assignee:
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`154]
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`I75]
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`[21]
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`[33]
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`[51]
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`[531
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`153]
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`FET WITH GATE SPACER
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`Inventors:
`Kuo-I-Iua Lee; Chih-Yuan Lu; Janmye
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`Sung. all of Lower Macungie
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`Township, Lehigh County, Pa.
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`AT&T Bell Laboratories, Murray
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`Hill. NJ.
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`Appl. No.: 422.834
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`Filed:
`Oct. 17, 1989
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`Int. Cl.-5 ................. .. HOIL 21/24; I-I011. 21/265;
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`HOIL 21/336
`US. Cl. ...................................... .. 437/44; 437/41;
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`437/200
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`Field of Search ..................... .. 437/34. 27, 28. 29.
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`437/30. 40. 41. 44. 56. 67. 235. 238. 239. 241.
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`186. 196. 200; 357/233. 23.4; 148/DIG. 147
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`References Cited
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`U.S. PATENT DOCUMENTS
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`3/1985 Chino .................................. .. 437/44
`4.503.601
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`437/44
`4.701.423 10/1987
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`437/44
`4.703.551 ll/1987
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`437/29
`4.727.038
`2/1988
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`437/44
`4.818.714
`4/1989
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`6/1989 Chiu et al.
`.......................... .. 437/3-1
`4.843.023
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`FOREIGN PATENT DOCUMENTS
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`0241267 ll/1985 Japan .
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`0101077
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`5/1986 Japan.
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`OTHER PUBLICATIONS
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`
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`al..
`“Fabrication of High Performance
`Tsang et
`LDDFET‘s with Oxide Sidewal1—Spacer Technology“.
`
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`
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`IEEE Journal of Solid State Circuits. vol. SC—17,No. 2.
`
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`Apr. 1982, pp. 220-226.
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`IEEE Electron Device Letters V. 9(4), (1988). “LDD
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`MOSFET‘s Using Disposable Side Wall Spacer Tech-
`nology." J. R. Pfiester, pp. 189-192.
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`VLSI Technology Symposium (1988). “Simultaneous
`
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`Formation of Shallow—Deep Stepped Source/Drain for
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`Submicron CMOS." C. W. Oh et al.. pp. 73-74.
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`Prfmary Examt‘ner—~Oli1< Chaudhuri
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`Assistant Examt'ner—M. Wilczewski
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`Attorney, Agent. or Firm—-John T. Rehberg
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`[57]
`ABSTRACT
`structure and
`A semiconductor
`integrated circuit
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`method of fabrication is disclosed. The structure in-
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`cludes a FET gate with adajcent double or trip1e-lay-
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`ered gate spacers. The spacers permit precise tailoring
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`oflightly doped drain junction profiles having deep and
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`shallow junction portions.
`In addition. a selfialigned
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`silicide may be formed solely over the deep junction
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`portion thus producing a reliable low Contact resistance
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`connection to source and drain.
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`5 Claims, 5 Drawing Sheets
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`TSMC Exhibit 1002
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`Page 1 of 10
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`U.S. Patent
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`Oct. 6, 1992
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`Sheet 1 of 5
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`5,153,145
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`Page 2 of 10
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`U.S. Patent
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`Oct. 6, 1992 I
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`Sheet 2 of 5
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`5,153,145
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`U.S. Patent
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`Oct. 6, 1992
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`Oct. 6, 1992
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`U.S. Patent
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`U.S. Patent
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`Oct. 6, 1992
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`Sheet 5 of 5
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`FIG, 14
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`123 121 118
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`

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`1
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`FET WITH GATE SPACER
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`5,153,145
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`TECHNICAL FIELD
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`This invention relates to integrated circuits and. more
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`particularly to integrated circuits with field effect tran-
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`sistors (FETs) and methods for making same.
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`BACKGROUND OF THE INVENTION
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`Those concerned with the development of integrated
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`circuit technology have continually sought to develop
`structures and methods of fabrication which will
`in-
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`crease circuit packing density, circuit performance, and
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`improve process yields.
`For example. some designers of submicron MOS-
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`FETs have employed a so-called lightly-doped drain
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`structure (LDD). The LDD structure features a shal-
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`low junction near the device gate and a deeper junction
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`spaced more remotely from the gate. The shallow junc-
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`tion helps to avoid punch-through and short channel
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`effects. However, the shallow junction exhibits a high
`sheet resistance and therefore may.
`taken alone, ad-
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`versely affect device performance.
`Various approaches to LDD technology have been
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`investigated in the past. Among them are: Pftester.
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`“LDD MOSFETs Using Disposable Side Wall Spacer
`Technology.“ IEEE Electron Device Letters V. 9(4),
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`p. 189-192 (l988) and Oh et al.. “Simultaneous Forma-
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`tion of Shallow-Deep Stepped Source/Drain for Sub-
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`micron CMOS.“ VLSI Technology Symposium, p.
`73-74 (1988).
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`Some of the above-mentioned publications feature
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`the use of silicide processes in an attempt to reduce the
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`high sheet resistance problems mentioned above. How-
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`ever. an examination of the published processes reveals
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`various practical difficulties with their implementation.
`Whether or not an LDD structure is employed. vari-
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`ous other problems may occur during device processing
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`which may subsequently degrade integrated circuit
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`performance. For example. various steps associated
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`with silicide processes may cause either damage to the
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`silicon substrate surface or may contribute to shorting
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`between the source/drain and gate.
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`Another problem confronting integrated circuit de-
`signers is the need to interconnect individual transistors
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`with increasingly complex interconnection schemes.
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`Designers frequently employ gate-level local intercon-
`nection schemes. However, if it
`is either necessary or
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`desirable for a local interconnection line to cross over a
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`gate runner, care must be taken to prevent electrical
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`contact betweenthe gate runner and the local intercon-
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`nection line. Those concerned with the development of
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`integrated circuits have consistently sought processes
`which will solve the above and other problems.
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`SUMMARY OF THE INVENTION
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`The present invention provides for a field effect tran-
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`sistor with a gate stack formed upon a semiconductor
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`substrate. During fabrication, three material layers are
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`formed over the gate stack and upon the substrate. At
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`least the outer two material layers are sequentially an-
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`isotropically etched, creating two spacers adjacent the
`gate stack (and gate runners).
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`The spacers perform a variety of useful functions in
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`various alternative embodiments of the invention. For
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`example, in one embodiment, the spacers may facilitate
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`creation of LDD junction profiles, the spacers serving
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`to mask portions ofthe substrate while partial junctions
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`are formed. The spacers simultaneously facilitate the
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`formation ofa self-aligned silicide Contact over only the
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`deep portion of the LDD junction. The self-aligned
`silicide-over-deepjunction structure has a desirably low
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`sheet resistance.
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`In another embodiment the gate stack and runners are
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`covered with a dielectric layer. At
`least one spacer
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`together with the dielectric layer serves to insulate the
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`runner so that local conductive interconnection r'nay
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`extend over the runner without risk of shorting.
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`The spacers perform a variety of other useful func-
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`tions in various embodiments. For example, one of the
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`spacers may be chosen from a material which is imper-
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`vious to migration of metal from silicide contacts over
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`source/drain regions to the conductive portion of the
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`gate. Such migration has been observed through con-
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`ventional spacer arrangements and has contributed to
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`shorting of the gate to the source/drain. Other advan-
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`tages of the invention are discused below.
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`BRIEF DESCRIPTION OF THE DRAWING
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`FIGS. 1-15 are cross-sectional views depicting illus-
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`trative processing sequences for
`fabricating various
`embodiments of the present invention.
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`DETAILED DESCRIPTION
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`The inventive concept may be best understood by a
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`discussion ofthe various procedures which may illustra-
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`tively be utilized to fabricate the inventive device.
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`FIG. 1 generally shows a representative cross-section
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`of a portion of a wafer during initial steps of typical
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`fabrication. Reference numeral 11 denotes a substrate
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`which may typically be silicon or epitaxial silicon. Ref-
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`erence numeral 13 denotes a portion of a field oxide,
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`while reference numeral 15 denotes a gate dielectric
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`layer which is typically an oxide. Reference numeral 17
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`denotes a layer conductive material which may be, for
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`example, polysilicon. Typical thicknesses for layers 15
`and 17, respectively. are 100-200 A and 2500-4000 A,
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`respectively.
`Turning to FIG. 2, layers 15 and 17 have been pat-
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`terned by methods known to those skilled in the art to
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`create FET gate stack designated by reference numeral
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`18. Next. another oxide layer 19 is formed. as illustrated
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`in FIG. 3. Oxide layer 19 is desirably a thermal oxide,
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`such as one grown at approximately 900° C. in oxygen.
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`However, a deposited oxide might also be used. It will
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`be noted that oxide layer 19 surrounds gate 18, covering
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`sides 20 and 22 and top 24 of gate 18. A typical thickness
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`for oxide layer 19 is 150-250 A. Layer 19 is desirably as
`thick as or thicker than gate oxide 15. Generally a ther-
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`mal oxide is preferred because of its low interface trap
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`density. Next, dielectric layer 21 which is typically
`silicon nitride or silicon oxynitride is deposited. An
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`exemplary thickness for layer 21 is 150-400 A.
`Finally, layer 23 is deposited upon layer 21. Layer 23
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`may desirably be a deposited oxide of silicon. Such an
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`oxide may be formed from silane or by decomposition
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`of a variety of organometallic precursors such as tetra-
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`ethoxysilane, (known by the acronym “TEOS“), or
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`diacetoxy-ditertiarybutoxysilane (known by the acro-
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`or
`tetramethylcyclotetrasilane
`nym “DADBS”),
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`known by the acronym “TMCTS" and sold by J. C.
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`Schumacher, a unit of Air Products and Chemicals Inc.,
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`under the trademark “TOMCATS." Layer 23 may be
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`doped, if desired, with boron or phosphorous. An exem-
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`plary thickness for layer 23 is 800-4000 A. Alterna-
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`tively. layer 23 may be polysilicon.
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`In FIG. 4. layers 23. 21. and 19 have been anisotropi-
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`cally etched in sequence. The figure shows gate stack 18
`surrounded on sides 20 and 22 by the nested remnants of
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`layers 23. 21. and 19. For convenience in the following
`discussion each of the above-mentioned remnants will
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`be termed a “spacer." However. it should be noted that
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`spacers 19 and 2] (which are nested beneath spacer 23)
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`have a generally “L-shaped" appearance (in cross-sec-
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`tion). Spacer 23 has a generally rounded outer contour
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`resembling a fillet. Of course,
`in actual practice the
`rounded contour of spacer 23 may become somewhat
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`distorted by various processing procedures. Similarly.
`“L-shapes" of spacers 19 and 21 may become somewhat
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`distorted, producing tilted spacers with slightly irregu-
`lar sides or other irregularities. However. in general. the
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`anisotropic etching procedures in current common use
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`will produce a nested set of spacers, the inner two 19
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`and 21 having comparatively flat sides and the outer are
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`23 having a rounded or curved outer surface.
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`The presence of layer 21 between layers 23 and 19
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`makes it possible to fairly precisely control the etching
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`of layer 19 to avoid over-etching and damage to sub-
`strate surface 26. For example. if layer 23 is BPTEOS.
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`layer 21 is silicon nitride. and layer 19 is thermal oxide.
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`it will be found that layer 21 serves as an etch step
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`against the etching oflayer 23. Once layer 21 is reached.
`the artisan is on notice that
`the remaining two thin
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`layers must be etched with care.
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`It may be considered desirable to protect the surface
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`26 of substrate 1]. Ifprotection for surface 26 is desired.
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`then layer 19 need not be etched at this juncture. Of
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`course. ifla_ver 19 is not etched. only two spacers 21 and
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`35
`23 will be formed and layer 19 will overlie surface 26.
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`(For convenience. FIG. 4 shows layer 19 etched to
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`form a spacer.)
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`Layer 19 is. as mentioned before. desirably a ther-
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`mally grown oxide. The oxide exhibits a low interface
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`trap density and serves as a stress relief buffer for over-
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`lying layer 21. (Typical silicon nitride films, such as that
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`recommended for layer 21. may exhibit considerable
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`stresses.) Thus layer 19 prevents high stresses in layer 21
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`from distorting substrate 11.
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`Now that formation ofa nested double or triple layer
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`spacer has been described. a variety of applications of
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`the inventive structure together with alternative em-
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`bodiments and their advantages will be described.
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`FIGS. 5-7 illustrate how the inventive concept may
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`50
`now be utilized to form a lightly-doped drain structure.
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`Referring first
`to FIG. 5, an ion implantation step.
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`shown schematically by species denoted by reference
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`numeral 31 is performed to form deeply-doped junc-
`tions 25 and 27. The appropriate ion species 31 is deter-
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`mined by whether an NMOS or PMOS device is to be
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`formed. Of course, should a CMOS pair of devices be
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`desired, photoresist 29 is deposited upon that portion of
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`the structure which must be shielded from the implanta-
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`tion species 31. It will be noted, as illustrated in FIG. 5,
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`that gate 18 flanked by spacers 19, 21, and 23 effectively
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`mask portions 28 and 30 of substrate 11 from implanta-
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`tion species 31. (If layer 19 has not been etched, it may
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`serve to protect surface 26 during the implantation step.
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`Spacers 21 and 23 will still serve as protective masks for
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`regions 28 and 30.)
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`A variety of other techniques may be utilized to form
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`junctions 25 and 27. In each case spacers 21, 23 (and
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`spacer 19 if formed) will mask portions 28 and 30 of
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`4
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`substrate 11. For example. a variety of gaseous and solid
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`diffusion techniques known to those skilled in the art
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`may be employed to form junctions 25 and 27.
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`Next. as illustrated by FIG. 6. spacers 23 are removed
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`in anticipation of formation of the shallow portion of
`the device junctions. If spacers 23 are made from un-
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`densified TEOS or even densified TEOS or BPTEOS,
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`they may be etched much more quickly than field oxide
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`13 or any protective oxide (such as layer 19 or another
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`regrown oxide layer) which may cover deep junction
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`27. For example. using a 15:] HF etch. the etch rate for
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`thermal oxide is approximately 200 A per minute, while
`for undensified TEOS the etch rate is approximately
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`1400 A per minute and for phosphorous doped TEOS.
`20,000 A per minute. If spacer 23 has been made from
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`polysilicon,
`it may be removed by plasma etching.
`(However. if material 17 is also polysilicon, it will also
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`be attacked by the plasma etching process. Conse-
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`quently. it
`is desirable that there be a protective layer
`such as silicon nitride material 17 ifspacer 23 is polysili-
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`con. The use of various layers. such as silicon nitride
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`over the gate stack is discussed in greater detail in subse-
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`quent paragraphs.)
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`After spacer 23 has been removed. a second implant
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`using ion species 37 shown in FIG. 6 is performed. The
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`second implantation species must penetrate the “foot"
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`of spacers 21 and 19. The foot serves to absorb some of
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`the ionic species. thus creating shallowjunction regions
`33 and 35 in portions 28 and 30 of substrate 11. Proper .
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`tailoring of the implant energy and dosage and the
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`thickness of the feet of layers 21 and 19 permits the
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`achievement of carefully controlled shallow junctions
`33 and 35.
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`If a CMOS pair is being formed. photoresist 29 may
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`be stripped. a new photoresist may be positioned over
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`the already-formed device depicted in FIG. 6 and the
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`complementary device formed by similar steps.
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`Next. as illustrated in FIG. 7. a thermal drive-in may
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`be performed. Other techniques such as laser heating
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`may also be employed to remove implant damage and
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`activate the dopant species. Next,
`if desired, a self-
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`aligned salicidation (salicide) may be performed. FIG. 9
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`illustrates the structure of FIG. 7 after a salicidation
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`step has been performed. Typically. a metal such as
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`titanium. tantalum, molybdenum. or tungsten is blanket-
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`deposited over the structure depicted in FIG. 7. Then
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`the structure is heated by methods known to those
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`skilled in the art, causing the metal to react preferen-
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`tially with underlying silicon, forming silicide regions
`51, 53, and 55, respectively, above junctions 25 and 27
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`and gate 18. The unreacted metal which may cover, for
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`example, spacer 21. is subsequently easily washed away.
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`this juncture,
`it
`is worthwhile to note several
`At
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`advantages of the structure depicted in FIG. 9 and
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`formed by the sequene of steps in FIGS. 1-7. Silicide
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`regions 51 and 53 are self-aligned with respect to the
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`deep junctions 27 and 25, respectively. For example,
`silicide region 51 covers all of the deep junction 27 but
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`does not cover the shallow junction 35 (due, of course,
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`to the presence oflayers 21 and 19). It is undesirable for
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`silicide region 51 to extend over the shallow junction 35
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`because leakage from the shallow junction to the sub-
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`strate will be dramatically increased. The leakage will
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`be caused by tunneling induced by asperities in the
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`bottom ofthe silicide layer through the depletion region
`between the lightly doped area such as 35 and substrate
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`11. Another difficulty caused by formation of silicides
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`upon lightly doped regions such as region 35 is that
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`to U-
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`30
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`40
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`45
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`55
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`60
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`65
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`Page 8 of 10
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`Page 8 of 10
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`

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`5,153,145
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`‘J!
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`10
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`20
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`to 'JI
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`40
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`6
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`gate to the source/drain. The present invention helps to
`eliminate this failure mode when spacer 21 is a material
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`which forms a shield or barrier against silicon migra-
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`tion, such as silicon nitride or silicon oxynitride.
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`When the present invention is compared to structures
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`which utilize a single silicon oxide spacer, another ad-
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`vantage is manifested. The anisotropic etching process
`which is used to create a single silicon oxide spacer is
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`frequently carried out beyond nominal completion, i.e..
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`over-etching is performed. The over-etching frequently
`creates trenches in the field oxide. A trench may occur
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`at the edge where the field oxide contacts the source/-
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`drain junction (i.e., where the oxide bird's beak meets
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`the doped silicon surface). The trench exposes some of
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`the undoped silicon substrate.
`Unfortunately, a subsequent salicidation process cre-
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`ates an electrical short circuit between the junction and
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`the exposed silicon in the trench via the salicide. The
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`present invention helps to avoid the over-etching prob-
`lem because layer 21 serves as an etch step during etch-
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`ing of layer 23. When layer 21 is reached, the artisan is
`on notice that further etching must be done with care.
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`(Another type of over-etching which may be avoided
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`by the present invention is trenching which may occur
`in a field oxide between two runners which overlie the
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`oxide. The trenching may exaggerate the aspect ratio of
`the space between the runners and makes subsequent
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`dielectric coverage difficult. Again.
`the presence of
`layer 21 which may serve as an etch-stop helps to pre-
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`vent the over-etching and trenching problem.)
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`Although application of the inventive concepts has
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`been discussed so far chiefly in connection with forma-
`tion of a lightly doped drain (LDD) structure. the in-
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`ventive concept may also be applied to devices which
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`do not require a lightly doped drain. An example of
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`such application is provided by FIG. 8. The structure
`depicted in FIG. 8 is obtained after the structure de-
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`picted in FIG. 4 is fabricated. The structure of FIG. 8 is
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`produced by an ion implantation step and drive-in ap-
`plied to the structure of FIG. 4. Examination of FIG. 8
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`shows source and drain regions 41 and 43 formed be-
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`neath gate stack 18 which is flanked by layers 19, 21.
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`and 23. It will be noted that layer 23 need not be re-
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`moved from the structure depicted in FIG. 8 because
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`there is no need for a lightly doped junction.
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`Another application of the inventive concept is de-
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`
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`picted in FIGS. 11-15. FIG. 11 is a cross-sectional view
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`of a portion of a semiconductor wafer during typical
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`initial steps of fabrication. Substrate 111 may be silicon
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`or epitaxial silicon. Field oxide 113 is formed upon
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`substrate 111. Gate oxide 115 is formed overlying sub-
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`strate 111. Layer 117, which may be typically polysili-
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`con, is formed aboved layer 115. Layer 118, which may
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`be silicon nitride or silicon oxynitride, covers layer 117.
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`‘Layers 115, 117, and 118 are formed typically during
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`initial steps of semiconductor wafer fabrication. Com-
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`parison of FIG. 11 with FIG. 1 reveals that an extra
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`layer (layer 118) has been deposited in FIG. 11 and is
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`absent in FIG. 1. Typical thicknesses for layers 115, 117,
`and 118 are 100-200 A, 2500-4000 A, and 1500-3000 A,
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`respectively.
`Turning to FIG. 12, it may be noted that layers 118,
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`117, and 115 have been patterned to produce gates 201
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`and 205 together with runner 203 which extends over
`field oxide 113. Thus, it will be noted that FIGS. 12-15
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`depict the formation of "two adjacent transistors sepa-
`rated by field oxide 113. Furthermore, gate level runner
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`203 extends along field oxide 113. Gate level runner 203
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`5
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`specific contact resistivity is likely to increase at the
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`interface between the silicide and the doped silicon. The
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`increased resistivity is due to the light doping at the
`interface between the silicide and the doped silicon.
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`
`The inventive process may be contrasted with the
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`
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`process discussed in Oh et al. mentioned above. The Oh
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`et al. process employs two layers (oxide followed by
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`nitride) after gate formation. A nitride spacer is formed
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`which serves to define the limits of an underlying oxide
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`spacer. The nitride spacer is removed. leaving only a
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`single oxide spacer prior to junction formation. The
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`oxide spacer serves to screen some of the incident ion
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`species during ion implantation. thus forming a one-stop
`LDD junction. However. the Oh et al. process does not
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`admit the use of a protective oxide layer (such as layer
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`19) over the entire silicon surface to protect against
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`implant damage. Furthermore, applicants’
`two-step
`junction formation procedure allows more precise tail-
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`oring of the junction profiles. In the Oh et al. process. a
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`subsequent additional CVD spacer must be formed
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`prior to silicide formation. However, it is not possible to
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`precisely align the CVD spacer with the initial oxide
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`spacer (which defines the edge of the deep portion of
`the junction) and consequently the silicide contact can-
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`not be precisely aligned with the deep junction edge.
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`By way of further comparison, applicants‘ process
`presents various advantages over the process mentioned
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`in the Pfiester article mentioned above. In particular the
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`Pfiester article shows a single spacer with rounded sides
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`to separate two separate implantation doses, thus creat-
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`ing an LDD structure. By contrast. applicants‘ inven-
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`tion permits the formation of deep and shallow junction
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`regions by implantation through two different
`thick-
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`nesses of dielectric. Consequently. very precise tailor-
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`ing. ofthe final junction profile is achievable with appli-
`cants‘ invention. Furthermore. the Pfiester article does
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`not mention silicidation. If silicidation were attempted
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`with the Pfiester. there is no method for self-aligning
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`the silicide with the deep junction.
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`Furthermore,
`the inventive structure possesses yet
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`another set of advantages over conventional transistor
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`structures and processes. These advantages are enumer-
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`ated below:
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`invention requires less masking than
`The present
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`45
`conventional LDD processes. Typical CMOS LDD
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`fabrication requires three or four masks. However, the
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`present invention requires only two masks (one mask
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`covering the p-substrate while the n-substrate is being
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`processed and vice versa) to form a CMOS LDD struc-
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`ture.
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`The present invention helps to prevent shorting be-
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`tween source/drain silicide and -the gate. It has been
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`found that certain metals such as titanium (commonly
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`used in silicidation of source/drain contacts) may tend
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`to migrate through TEOS-type spacers toward the gate
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`and cause shorting between the source/drain and the
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`gate. However, the present invention helps to eliminate
`this failure mode because spacer 21 (which is typically
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`silicon nitride or silicon oxynitride) forms a protective
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`shield or barrier against metal migration.
`Another important advantage of the present inven-
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`tion is that layer 21 may help prevent the migration of
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`other types of particles into the gate stack. In particular,
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`it has been found that some devices fabricated without
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`layer 21 may experience various failures during burn-in.
`Some failures are believed due to the migration of sili-
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`con particles through conventional silicon oxide gate
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`spacers. The silicon particles may cause shorting of the
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`50
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`S5
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`60
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`65
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`Page 9 of 10
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`Page 9 of 10
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`8
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`tated the formation of a sub-gate level interconnection
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`between junction regions of different transistors (i.e.. a
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`connection formed prior to passivation dielectric depo-
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`sition and Contact window opening) without the possi-
`bility of shorting to a gate runner.
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`We claim:
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`1. A method of semiconductor integrated circuit
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`fabrication comprising:
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`forming a gate stack upon a substrate:
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`forming a first material layer upon said gate stack and
`upon said substrate:
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`forming a second material layer upon said first mate-
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`rial layer:
`forming a third material layer upon said second mate-
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`rial layer;
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`anisotropically etching said third layer to form a first
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`spacer and then etching said second layer to form a
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`second spacer underlying said first spacer;
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`exposing sa