US006281562B1
`(10) Patent No.
`a2) United States Patent
`US 6,281,562 B1
`Segawaetal.
`(45) Date of Patent:
`*Aug. 28, 2001
`
`
`2/1994 Roth et al. oe 437/190
`5,286,674
`(54) SEMICONDUCTOR DEVICE WHICH
`
`w. 257/370
`6/1994 Kihara etal. .
`5,319,235 *
`REDUCES THE MINIMUM DISTANCE
`
`Ishimaru .......
`vee 257/387
`3/1995.
`5397,910
`5,401,673
`3/1995 Urayama...
`we 437/187
`REQUIREMENTS BETWEEN ACTIVE
`Eo
`5,413,961
`5/1995. Kim eaeseeeesssee
`vee 437/195
`SBP 71988 Tanta
`"14883
`Inventors: Mizuki Segawa; ao Miyanaga;
`
`5,521,422 *
`5/1996 Mandelmanetal.
`ve 257/510
`Toshiki Yabu; Takashi Nakabayashi,
`5,561,311 * 10/1996 Hamamotoet al.
`........... 257/309
`Takashi Uehara; Kyoji Yamashita;
`5,777,370 *
`7/1998 Omid-Zohooret al.
`we 257/374
`Takaaki Ukeda; Masatoshi Arai;
`
`we 257/396
`5,804,862 *
`9/1998 Matumoto ......0...
`Takayuki Yamada; Michikazu
`2/2000 Noble, Jr. et al. wu 438/296
`6,022,781 *
`Matsumoto,all of Osaka (JP)
`FOREIGN PATENT DOCUMENTS
`(73) Assignee: Matsushita Electric Industrial Co.,
`Ltd., Osaka (JP) 0 243 988=11/1987 (EP).
`
`0 513 639
`11/1992 (EP).
`4-68564 *
`3/1992 (TP)
`vaesescsssssesscsssseecssssseeesesnees 257/510
`6-163843
`6/1994 (JP).
`* cited by examiner
`
`(15)
`
`(*) Notice:
`
`This patent issued on a continued pros-
`ecution application filed under 37 CFR
`1.53(d), and is subject to the twenty year
`patent
`term provisions of 35 U.S.C.
`154(a)(2).
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`US.C. 154(b) by 0 days.
`
`(56)
`
`References Cited
`
`Primary Examiner—Olik Chaudhuri
`Assistant Examiner—Howard Weiss
`(74) Attorney, Agent, or Firm—McDermott, Will & Emery
`67)
`ABSTRACT
`An isolation which is higher in a stepwise manner than an
`active area of a silicon substrate is formed. On the active
`(21) Appl. No.: 08/685,726
`area, an FET including a gate oxide film, a gate electrode, a
`:
`gate protection film, sidewalls and the like is formed. An
`Jul. 24, 1996
`Filed:
`(22)
`insulating
`film is deposited on the entire top
`surface of the
`sas
`:
`ss
`substrate, and a resist film for exposing anarea stretching
`Foreign Application Priority Data
`(30)
`over the active area, a part of the isolation and the gate
`Tul. 27, 1995
`(UP)
`ceseecsssecssssssscsssccssssccssseccsssecssseesssss 7-192181
`protection film is formed on the insulating film. There is no
`Dec. 19, 1995
`(IP) ecccecsessessecsscenssseneeseecsseensnnenesnes 7-330112
`need to provide an alignment margin for avoiding interfer-
`7
`ence with the isolation and the like to a region where a
`(51)
`Int. Chee HO1L 29/167; HO1L 29/00;
`connection hole is formed. Since the isolation is higher in a
`HO1L 21/331, HOLL 21/76
`stepwise manner than the active area, the isolation is pre-
`(52) U.S. C0. cee eceseeeeeeeee 257/510; 257/304; 257/774;
`vented from being removed by over-etch in the formation of
`438/359; 438/424
`(58) Field of Search 2... 257/304, 510,|a connection hole to come in contact with a portion where
`257/774, 311; 438/359, 424
`an impurity concentration is low in the active area. In this
`manner, the integration of a semiconductor device can be
`improved and an area occupied by the semiconductor device
`can be decreased without causing degradation of junction
`voltage resistance and increase of a junction leakage current
`
`
`
`
`
`
`
`
` Exhibit 2061
`
`TSMCv.IP Bridge
`IPR2016-01246
`
`Page 1 of 38
`
`U.S. PATENT DOCUMENTS
`4,578,128 *
`3/1986 Mundtet al. 0. 148/191
`5,177,028
`1/1993 Manning.........
`5,196,910 *
`3/1993 Moriuchi et al. eee 257/510
`
`12 Claims, 21 Drawing Sheets
`
`23
`
`in the semiconductor device.
`VALLELLLLLLaeWE
`
`Page 1 of 38
`
`Exhibit 2061
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 1 of 21
`
`US 6,281,562 B1
`
`FIG. 1(a)
`
`>!
`
`FIG. 1Cb)
`
`2b
`
`,
`
`2b
`
`Page 2 of 38
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`Page 2 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 2 of 21
`
`US 6,281,562 B1
`
`4x
`
`FIG. 2(a)
`
`2b
`
`FIG. 2(e)
`
`FIG. 2(b)
`
`FIG. 2(c) F
`
`FIG. 2¢d)
`
`1
`
`Page 3 of 38
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`Page 3 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 3 of 21
`
`US 6,281,562 B1
`
`7
`
`4x
`
`FIG. 3¢c)
`
`FIG. 3(d)
`
`X
`
`%
`
`F
`
`25a
`
`4
`
`
` YY
`rinse KeKa*
`
`FIG. 3(f) F
`
`Page 4 of 38
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`Page 4 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 4 of 21
`
`US 6,281,562 B1
`
`FIG. 4(a)
`
`
` Co SN
`stn
`M/A
`VAN ne
`
`
`
`Ws
`
`FIG. 4(b)
`
`
`
`V4
`
`
`
`PAY NA
`
`
`
`ioe LOTINSZ
`Ak 8 PRE
`PINS
`
`
`FIG. 4(c) -
`
`Page 5 of 38
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`Page 5 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 5 of 21
`
`US 6,281,562 B1
`
`
`
`FIG. 5(a) F
`
`FIG. 5(b)
`CT|LY
`
`
`
`VL
`
`
`
`
`FIG. 5(c) F
`
`Page 6 of 38
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`Page 6 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 6 of 21
`
`US 6,281,562 B1
`
`1
`
`2b
`
`NRPS
`
`15x FIG. 6(b) |
`
`FIG. 6(c)
`
`FIG. 6(d)7 *
`
`FIG. 6(e) Aa
`
`FIG. 6(F)
`
`Page 7 of 38
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`Page 7 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 7 of 21
`
`US 6,281,562 B1
`
`FIG. 7(a)
`
`FIG. 7(c)
`
`FIG. 7(b)
`
`Page 8 of 38
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`Page 8 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 8 of 21
`
`US 6,281,562 B1
`
`FIG. 8(a)
`
`
`
`FIG. 8(b)
`
`SSre
`N\
`
`
`
`
`FIG. 8(c)
`
`
`
`
`aeLS
`
`
`
`ENS
`
`
`Page 9 of 38
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`Page 9 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 9 of 21
`
`US 6,281,562 B1
`
`FIG. 9(a)
`FIG. 9Cb)
`
`
`rexVen.
`
`PRES
`W/EZANthy=
` IN
`
`VLLLLLLLLELL
`
`23
`
`FIG. 9(c)
`
`Page 10 of 38
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`Page 10 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 10 of 21
`
`US 6,281,562 B1
`
`FIG. L0(a) bf
`
`
` ASRPES
`KY
`
`FIG. 10(c)
`
`Page 11 of 38
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`Page 11 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 11 of 21
`
`US 6,281,562 B1
`
`FIG. 11(a)
`
`
`
`—_= Secas)\all
`
`473PESTIAYNS
`
`
`
`FIG. 11(b) L&
`Ewe
`PIG. 110) Lae
`
`
`
`
`
`Page 12 of 38
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`Page 12 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 12 of 21
`
`US 6,281,562 B1
`
`oathKW
`
`CIDIPD
`
`Page 13 of 38
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`Page 13 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 13 of 21
`
`US 6,281,562 B1
`
`Reiso
`
`Revet
`
`Reiso
`
`FIG. 13(a)
`
`ZZ.
`EZZZZZA
`FIG. 1300) ee
`“nee
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` FIG. 13Cc)
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`LLLAfftae (YLL|Rehzee|
`F I G. l 3 ( e) Lf — yy SLRIZA
`
`
`LLLLLLLD OS
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`p
`
`Page 14 of 38
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`Page 14 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 14 of 21
`
`US 6,281,562 B1
`
`SRRSSSROORPILI2LLLDLL
`
`eeeeo
`
`SOASSS
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`bs
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`FIG. 14(c) |2eeae
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`FIG. 14¢d)
`IND
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`FIG. 14Ce) ISS
`
`
`Page 15 of 38
`
`Page 15 of 38
`
`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 15 of 21
`
`US 6,281,562 B1
`
`Refet
`
`Reiso
`
`FIG. 15(e)
`
` FIG. 15¢d)
`
`- aTNAL)flHo
`FIG. 15(£) F
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`
`
`Page 16 of 38
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`Page 16 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 16 of 21
`
`US 6,281,562 B1
`
`Page 17 of 38
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`Page 17 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 17 of 21
`
`US 6,281,562 B1
`
`FIG. 17
`PRIOR ART
`
`
`
`Page 18 of 38
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`Page 18 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 18 of 21
`
`US 6,281,562 B1
`
`DIAMETER
`OF HOLE
`
`END OF ISOLASION
`
`FIG. 18(a)
`PRIOR ART
`
`
`
`
`MGI80 LA"
`VS LL 25a
`
`PN
`PRIOR ART
`
`
`
`
`FIG. 18(c)
`
`Page 19 of 38
`
`Page 19 of 38
`
`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 19 of 21
`
`US 6,281,562 B1
`
`FIG. 19
`PRIOR ART
`
`Lf
`
`LIV TRY]
`PISFTTTTROSSCLN4
`C986:|+ a. 8°60"
`
`Page 20 of 38
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`Page 20 of 38
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`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 20 of 21
`
`US 6,281,562 B1
`
`Re SO
`
`Refet
`|
`
`Reiso
`10
`
`Refet
`}
`
`Reiso
`
`FIG. 20(a)
`PRIOR ART
`
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`
`
` FIG. 20 (Cc) VILELILITITYT
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`ANNO
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`105a
`116
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`FIG. 200) SS ss
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`PRIOR ART
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`PRIOR ART
`
`Page 21 of 38
`
`Page 21 of 38
`
`

`

`U.S. Patent
`
`Aug. 28, 2001
`
`Sheet 21 of 21
`
`US 6,281,562 B1
`
`FIG. 21(a)
`PRIOR ART
`
`FIG. 21(b)
`PRIOR ART
`
`IMPURITY ION
`113
`
`Page 22 of 38
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`Page 22 of 38
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`

`

`US 6,281,562 B1
`
`1
`SEMICONDUCTOR DEVICE WHICH
`REDUCES THE MINIMUM DISTANCE
`REQUIREMENTS BETWEEN ACTIVE
`AREAS
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a semiconductor device
`including transistors and connection between the transistors
`for constituting an LSI with high integration and a decreased
`area.
`
`With the recent development of a semiconductor device
`with high integration and high performance,
`there are
`increasing demands for more refinement of the semiconduc-
`tor device. The improvementof the conventional techniques
`cannot follow these demands, and novel
`techniques are
`unavoidably introduced in some technical
`fields. For
`example, as a method of forming an isolation, the LOCOS
`isolation method is conventionally adopted in view of its
`simpleness and low cost. Recently, however, it is considered
`that a trench buried type isolation (hereinafter referred to as
`the trench isolation) is more advantageous for manufactur-
`ing a refined semiconductor device.
`Specifically, in the LOCOSisolation method, since selec-
`tive oxidation is conducted, the so-called bird’s beak occurs
`in the boundary with a mask for preventing the oxidation. As
`a result, the dimension of a transistor is changed because an
`insulating film of the isolation invades a transistor region
`against the actually designed mask dimension. This dimen-
`sional change is unallowable in the refinement of a semi-
`conductor device after the 0.5 wm generation. Therefore,
`even in the mass-production techniques, the isolation form-
`ing method hasstarted to be changedto the trench isolation
`method in which the dimensional change is very small. For
`example, IBM corporation has introduced the trench isola-
`tion structure as a 0.5 um CMOSprocess for the mass-
`production of an MPU (IBM Journal of Research and
`Development, VOL. 39, No. 1/2, 1995, pp. 33-42).
`Furthermore, in a semiconductor device mounting ele-
`ments such as a MOSFETin an active area surrounded with
`
`an isolation, an insulating film is deposited on the active
`area, the isolation and a gate electrode, and a contacthole is
`formed by partly exposing the insulating film for connection
`between the active area and an interconnection member on
`
`a layer above the insulating film. This structure is known as
`a very commonstructure for the semiconductor device.
`FIG. 17 is a sectional view for showingthe structure of a
`conventional semiconductor device. In FIG. 17, a reference
`numeral 1 denotesa silicon substrate, a reference numeral 2b
`denotes an isolation with a trench isolation structure which
`
`is made of a silicon oxide film and whose top surface is
`flattened so as to be at the same level as the top surface of
`the silicon substrate 1, a reference numeral 3 denotes a gate
`oxide film madeofa silicon oxide film, a reference numeral
`4a a denotes a polysilicon electrode working as a gate
`electrode, a reference numeral 4b denotes a polysilicon
`interconnection formed simultaneously with the polysilicon
`electrode 4a, a reference numeral 6 denotes a low-
`concentration source/drain region formed by doping the
`silicon substrate with an n-type impurity at a low
`concentration, a reference numeral 7a denotes an electrode
`sidewall, a reference numeral 7b denotes an interconnection
`sidewall, a reference numeral 8 denotes a high-concentration
`source/drain region formed by doping the silicon substrate
`with an n-type impurity at a high concentration, a reference
`numeral 12 denotes an insulating film made of a silicon
`oxide film, and a reference numeral 13 denotes a local
`
`10
`
`15
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`interconnection made of a polysilicon film formed on the
`insulating film 12.
`The local interconnection 13 is also filled within a con-
`
`nection hole 14 formed in a part of the insulating film 12, so
`as to be contacted with the source/drain region in the active
`area through the connection hole 14.
`In this case,
`the
`connection hole 14 is formed apart from the isolation 2b by
`a predetermined distance. In other words, in the conven-
`tional layout rule for such a semiconductor device, there is
`arule that the edge of a connection holeis previously located
`away from the boundary between the active area and the
`isolation region so as to prevent a part of the connection hole
`14 from stretching over the isolation 2b even when a mask
`alignmentshift is caused in photolithography (this distance
`between the connection hole and the isolation is designated
`as an alignment margin).
`However, in the structure of the semiconductor device as
`shown in FIG. 17, there arise problems in the attempts to
`further improve the integration for the following reason:
`A distance La between the polysilicon electrode 4a and
`the isolation 2b is estimated as an index of the integration.
`In order to prevent the connection hole 14 from interfering
`the isolation 2b as described above,
`the distance La is
`required to be 1.2 um, namely, the sum of the diameterof the
`connection hole 14,that is, 0.5 um, the width of the electrode
`sidewall 7a, that is, 0.1 um, the alignment margin from the
`polysilicon electrode 4a, that is, 0.3 um, and the alignment
`margin from the isolation 25, that is, 0.3 wm. A connection
`hole has attained a more and morerefined diameter with the
`development of processing techniques, and also a gate
`length has been decreased as small as 0.3 wm orless. Still,
`the alignment margin in consideration of the mask alignment
`shift in the photolithography is required to be approximately
`0.3 wm. Accordingly, as the gate length and the connection
`hole diameter are more refined, the proportion of the align-
`ment margin is increased. This alignment margin has
`become an obstacle to the high integration.
`Therefore, attempts have been made to form the connec-
`tion hole 14 without considering the alignment margin in
`view of the alignment shift in the photolithography. Manu-
`facturing procedures adopted in such a case will now be
`described by exemplifying an n-channel MOSFETreferring
`to FIGS. 18(a) through 18(c).
`First, as is shown in FIG. 18(a), after forming an isolation
`2b having the trench structure in a silicon substrate 1 doped
`with a p-type impurity (or p-type well), etch back or the like
`is conducted for flattening so as to place the surfaces of the
`isolation 2b and thesilicon substrate 1 at the same level. In
`
`an active area surrounded with the isolation 2b, a gate oxide
`film 3, a polysilicon electrode 4a serving as a gate electrode,
`an electrode sidewall 7a, a low-concentration source/drain
`region 6 and a high-concentration source/drain region 8 are
`formed. On the isolation 2b are disposed a polysilicon
`interconnection 4b formed simultaneously with the polysili-
`con electrode 4a and an interconnection sidewall 7b. At this
`
`point, the top surface of the high-concentration source/drain
`region 8 in the active area is placed at the samelevel as the
`top surface of the isolation 2b. Then, an insulating film 12
`of a silicon oxide film is formed on the entire top surface of
`the substrate.
`
`Next, as is shown in FIG. 18(b), a resist film 25a used as
`a mask for forming a connection hole is formed on the
`insulating film 12, and the connection hole 14 is formed by,
`for example, dry etching.
`Then, as is shown in FIG. 18(c), the resist film 25a is
`removed, and a polysilicon film is deposited on the insulat-
`
`Page 23 of 38
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`

`

`US 6,281,562 B1
`
`3
`ing film 12 and within the connection hole 14. The poly-
`silicon film is then made into a desired pattern, thereby
`forming a local interconnection 13.
`Atthis point, in the case where the alignment margin in
`view of the mask alignment shift in the formation of the
`connection hole 14 is not considered in estimating the
`distance La between the polysilicon electrode 4a and the
`isolation 2b, a part of the isolation 2b is included in the
`connection hole 14 when the exposing area ofthe resist film
`25a is shifted toward the isolation 2b due to the mask
`
`4
`trode 109a, an upper gate interconnection 109b and a
`source/drain electrode 109c each madeofsilicide are respec-
`tively formed. Furthermore,
`this semiconductor device
`includes an interlayer insulating film 111 madeofa silicon
`oxide film, a metallic interconnection 112 formed on the
`interlayer insulating film 111, and a contact member 113
`(buried conductive layer) filled in a connection hole formed
`in the interlayer insulating film 111 for connecting the
`metallic interconnection 112 with the source/drain electrode
`109¢.
`
`10
`
`Now, the manufacturing procedures for the semiconduc-
`alignment shift in the photolithography. Through over-etch
`tor device including the conventional trench isolation and
`the MOSFETwith the salicide structure shown in FIG. 19
`in conducting the dry etching of the insulating film 12,
`although the high-concentration source/drain region 8 made
`will be described referring to FIGS. 20(a) through 20 (e).
`of the silicon substrate is not largely etched because ofits
`First, as is shown in FIG. 20(a), a silicon oxide film 116
`small etchingrate, the part of the isolation 2b included in the
`and a silicon nitride film 117 are successively deposited on
`connection hole 14 is selectively removed, resulting in
`a silicon substrate 101, andaresist film 120 for exposing an
`forming a recess 40 in part of the connection hole 14. When
`isolation region and maskingatransistor region is formed on
`the recess 40 in the connection hole 14 has a depth exceed-
`the silicon nitridefilm 117. Then,by usingtheresist film 120
`ing a given proportion to the depth of the high-concentration
`as a mask, etching is conducted, so as to selectively remove
`source/drain region 8, junction voltage resistance can be
`the silicon nitride film 116 and the silicon oxide film 117,
`decreased and a junction leakage current can be increased
`and further etch the silicon substrate 101, thereby forming a
`because the concentration of the impurity in the high-
`trench 104. Then, impurity ions are injected into the bottom
`concentration source/drain region 8 is low at that depth.
`of the trench 104, thereby forming a channelstop region 115.
`In order to prevent these phenomena,it is necessary to
`Then, as is shown in FIG. 20(5), a silicon oxide film (not
`provide a predetermined alignment margin as is shownin the
`shown) is deposited, and the entire top surface is flattened
`structure of FIG. 17 so as to prevent the connection hole 14
`until the surface of the silicon nitride film 117 is exposed.
`from interfering the isolation 2b even when the alignment
`Through this procedure, a trench isolation 105a madeof the
`silicon oxide film filled in the trench 104 is formed in the
`shift is caused in the lithography. In this manner, in the
`conventional layout rule for a semiconductor device, an
`alignment margin in view of the mask alignmentshift in the
`photolithography is unavoidably provided.
`Furthermore, a distance between the polysilicon electrode
`4a and the connection hole 14is also required to be provided
`with an alignment margin. Otherwise, the connection hole
`14 can interfere the polysilicon electrode 4a due to the
`fluctuation caused in the manufacturing procedures, result-
`ing in causing electric short-circuit between an upper layer
`interconnection buried in the connection hole and the gate
`electrode.
`
`As described above, it is necessary to provide the con-
`nection hole 14 with margins for preventing the interference
`with other elements around the connection hole, which has
`become a large obstacle to the high integration of an LSI.
`Also in the case where a semiconductor device having the
`so-called salicide structure is manufactured, the following
`problemsare caused due to a recess formed intheisolation:
`FIG. 19 is a sectional view for showing an example of a
`semiconductor device including the conventional
`trench
`isolation and a MOSFEThavingthe salicide structure. As is
`shown in FIG. 19, a trench isolation 105a is formed in a
`silicon substrate 101. In an active area surrounded with the
`
`isolation 105a, a gate insulating film 1034, a gate electrode
`107a, and electrode sidewalls 1084 on both side surfaces of
`the gate electrode 107a are formed. Also in the active area,
`a low-concentration source/drain region 106a and a high-
`concentration source/drain region 106b are formed on both
`sides of the gate electrode 107a. A channel stop region 115
`is formed below the isolation 105a. Furthermore, in areas of
`the silicon substrate 101 excluding the isolation 105a@ and
`the active area, a gate interconnection 107b made of the
`same polysilicon film as that for the gate electrode 107a is
`formed with a gate insulating film 1035 sandwiched, and the
`gate interconnection 106b is provided with interconnection
`sidewalls 1085 on its both side surfaces. On the gate
`electrode 107a, the gate interconnection 1075 and the high-
`concentration source/drain region 106b, an upper gate elec-
`
`15
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`20
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`25
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`35
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`40
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`45
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`isolation region Reiso.
`Next, as is shown in FIG. 20(c), after the silicon nitride
`film 117 andthe silicon oxide film 116 are removed,a gate
`oxide film 103 is formed on the silicon substrate 101, and a
`polysilicon film 107 is deposited thereon. Then, a photore-
`sist film 121 for exposing areas excluding a region for
`forming a gate is formed on the polysilicon film 107.
`Then, as is shownin FIG. 20(d), by using the photoresist
`film 121 as a mask, dry etching is conducted,
`thereby
`selectively removing the polysilicon film 107 and the gate
`oxide film 103. Thus, a gate electrode 107a of the MOSFET
`in the transistor region Refet and a gate interconnection
`106b stretching over the isolation 105a@ and the silicon
`substrate 101 are formed. After removing the photoresist
`film 121, impurity ions are injected into the silicon substrate
`101 by using the gate electrode 107a as a mask, thereby
`forming a low-concentration source/drain region 106a.
`Then,a silicon oxide film 108 is deposited on the entire top
`surface of the substrate.
`
`50
`
`Next, as is shownin FIG. 20(e), the silicon oxide film 108
`is anisotropically dry-etched,
`thereby forming electrode
`sidewalls 108a and interconnection sidewalls 1085 on both
`
`side surfaces of the gate electrode 107a and the gate inter-
`connection 1065, respectively. At this point, the gate oxide
`film 103 below the silicon oxide film 108 is simultaneously
`removed, and the gate oxide film 103 below the gate
`electrode 107a alone remains. Then,
`impurity ions are
`diagonally injected by using the gate electrode 107a and the
`electrode sidewalls 108a as masks, thereby forming a high-
`concentration source/drain region 106b. Then,after a Ti film
`is deposited on the entire top surface, high temperature
`annealing is conducted, thereby causing a reaction between
`the Ti film and the components madeof silicon directly in
`contact with the Ti film. Thus, an upper gate electrode 109a,
`an upper gate interconnection 109b and a source/drain
`electrode 109c madeof silicide are formed.
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`55
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`60
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`65
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`The procedures to be conducted thereafter are omitted, but
`the semiconductor device including the MOSFEThavingthe
`
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`US 6,281,562 B1
`
`5
`structure as shown in FIG. 19 can be ultimately manufac-
`tured. In FIG. 19, the metallic interconnection 112 is formed
`on the interlayer insulating film 111, and the metallic inter-
`connection 112 is connected with the source/drain electrode
`109c¢ through the contact member 113 including a W plug
`and the like filled in the contact hole.
`When the aforementioned trench isolation structure is
`adopted, the dimensional change of the source/drain region
`can be suppressed because the bird’s beak, that is, the oxide
`film invasion of an active area, which is caused in the
`LOCOSmethod wherea thick silicon oxide film is formed
`by thermal oxidation, can be avoided. Furthermore, in the
`procedure shownin FIG. 20(c), the surfaces of the isolation
`105a and the silicon substrate 101 in the transistor region
`Refet are placed at the same level.
`In such a semiconductor device having the trench type
`isolation, however, there arise the following problems:
`When the procedures proceed from the state shown in
`FIG. 20(d) to the state shown in FIG. 20(e), the silicon oxide
`film 108 is anisotropically etched so as to form the sidewalls
`108a and 108d. At this point, over-etch is required. Through
`this over-etch, the surface of the isolation 105a is removed
`by some depth.
`FIGS. 21(a) and 21(5) are enlarged sectional views
`around the boundary between the high-concentration source/
`drain region 1065 andtheisolation 105a after this over-etch.
`As is shownin FIG. 21(a), between the procedures shown
`in FIGS. 20(d) and 20(e), the impurity ions are diagonally
`injected so as to form the high-concentration source/drain
`region 106b. Through this ion injection,
`the high-
`concentration source/drain region 1065 is formed also below
`the edge of the isolation 105a@ because the isolation 105a is
`previously etched by some depth. Accordingly, the high-
`concentration source/drain region 106b is brought closer to
`the channel stop region 115, resulting in causing the prob-
`lems of degradation of the junction voltage resistance and
`increase of the junction leakage current.
`In addition, as is shown in FIG. 21(5), in the case where
`the Ti film or the like is deposited on the high-concentration
`source/drain region 1065 so as to obtain the silicide layer
`through the reaction with the silicon below, the thus formed
`silicide layer can invade the interface between the silicon
`substrate 101 and the isolation 105a with ease. As a result,
`a short-circuit current can be caused between the source/
`drain electrode 109c made of silicide and the channel stop
`region 115.
`
`SUMMARYOF THE INVENTION
`
`invention is improving the
`The object of the present
`structure of an isolation, so as to prevent the problems
`caused because the edge of the isolation is trenched in
`etching for the formation of a connection hole or sidewalls.
`In order to achieve the object, the invention proposesfirst
`and second semiconductor devices and first through third
`methods of manufacturing a semiconductor device as
`described below.
`Thefirst semiconductor device of this invention in which
`
`a semiconductor elementis disposed in each ofplural active
`areas in a semiconductor substrate comprises an isolation for
`surrounding and isolating each active area,
`the isolation
`having a top surface at a higher level than a surface of the
`active area and having a step portion in a boundary with the
`active area; an insulating film formed so as to stretch over
`each active area and the isolation; plural holes each formed
`by removinga portion of the insulating film disposedat least
`
`10
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`15
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`20
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`25
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`30
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`35
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`40
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`45
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`50
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`60
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`65
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`6
`on the active area; plural buried conductive layers filled in
`the respective holes; and plural interconnection members
`formed on the insulating film so as to be connected with the
`respective active areas through the respective buried con-
`ductive layers.
`Owingto this structure, in the case where a part oforall
`the holes are formedsoasto stretch over the active areas and
`the isolation due to mask alignment shift
`in
`photolithography, a part of the isolation is removed by
`over-etch for ensuring the formation of the holes. In such a
`case, even when the top surface of the isolation is trenched
`to be lower than the surface of the active area, the depth of
`the holes formed in the isolation is small in the boundary
`with the active area because of the level difference between
`the top surface of the isolation and the surface of the active
`area. Accordingly, degradation of the junction voltageresis-
`tance and increase of the junction leakage current can be
`suppressed. Therefore, there is no need to provide a portion
`of the active area where each hole is formed with an
`
`alignment margin for avoiding the interference with the
`isolation caused by the mask alignment shift in the lithog-
`raphy. Thus, the area of the active area can be decreased,
`resulting in improving the integration of the semiconductor
`device.
`
`In the first semiconductor device, at least a part of the
`plural holes can be formed so as to stretch over the active
`area and the isolation due to fluctuation in manufacturing
`procedures.
`In other words, even when no margin for the mask
`alignment
`in the lithography is provided,
`the problems
`caused in the formation of the holes can be avoided.
`
`Furthermore, the angle between a side surface of the step
`portion and the surface of the active area is preferably 70
`degrees or more.
`As a result, when the hole interferes the isolation, the part
`of the isolation included in the hole is definitely prevented
`from being etched through over-etch in the formation of the
`holes down to a depth where the impurity concentration is
`low in the active area.
`
`The isolation is preferably a trench isolation made of an
`insulating material filled in a trench formed bytrenching the
`semiconductor substrate by a predetermined depth.
`This is because no bird’s beak is caused in the trench
`
`isolation differently from a LOCOSfilm as described above,
`and hence, the trench isolation is suitable particularly for the
`high integration and refinement of the semiconductor
`device.
`
`In the first semiconductor device, when the semiconduc-
`tor element is a MISFETincluding a gate insulating film and
`a gate electrode formed on the active area; and source/drain
`regions formed in the active area on both sides of the gate
`electrode,
`the following preferred embodiments can be
`adopted:
`The semiconductor device can further comprise a gate
`interconnection made of the same material as that for the
`gate electrode and formed onthe isolation, each of the holes
`can be formed on an area including the source/drain region,
`the isolation and the gate interconnection, and the plural
`interconnection members can be connected with the gate
`interconnection on the isolation.
`
`Owing to this configuration, in the case where the inter-
`connection members work as local
`interconnections for
`
`connecting a gate interconnection on the isolation with the
`active area, there is no need to separately form holes in the
`insulating film on the gate interconnection andthe insulating
`
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`US 6,281,562 B1
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`7
`film on the active area. In addition, there is no need to
`provide the separate holes with alignment margins from the
`boundary between the active area and the isolation.
`Accordingly, the area of the isolation can also be decreased,
`resulting in largely improving the integration of the semi-
`conductor device.
`
`The semiconductor device can further comprise electrode
`sidewalls made of an insulating material and formed on both
`side surfaces of the gate electrode; and a step sidewall made
`of the same material as the insulating material for the
`electrode sidewalls and formed on the side surface of the
`step portion. In this semiconductor device, at least a part of
`the holes can be formed by also removing a portion of the
`insulating film disposed on the step sidewall.
`Owing to this structure,
`the abrupt
`level difference
`between the surfaces of the isolation and the active area can
`be released by the step sidewall. Therefore, a residue is
`scarcely generated in patterning the interconnection
`members, and an upper interconnection is prevented from
`being disconnected and increasing in its resistance.
`The semiconductor device can further comprise a gate
`protection film formed on the gate electrode, and at least a
`part of the holes can be formed so as to stretch over the
`source/drain region and at least a part of the gate protection
`film.
`
`Owingto this structure, a part of the gate protection film
`included in the hole is removed by the over-etch in the
`formation of the holes. However,
`the gate electrode is
`protected by the gate protection film, and hence, electrical
`short circuit between the gate electrode and the intercon-
`nection membercan be prevented. Accordingly, there is no
`need to provide an alignment margin from the gate electrode
`in the area where each hole is formed, resulting in further
`improving the integration.
`The interconnection members can befirst layer metallic
`interconnections, and the insulating film can be an interlayer
`insulating film disposed between the semiconductor
`substrate, and thefirst layer metallic interconnections. In this
`case,
`the semiconductor device preferably further
`comprises, between the interlayer insulating film and the
`semiconductor substrate an underlying film made of an
`insulating material having high etching selectivity against
`the interlayer insulating film.
`The second semiconductor device of this invention in
`which a semiconductor elementis disposed in each of plural
`active areas in a semiconductor substrate comprises a trench
`isolation for isolating and surrounding each active area, the
`trench isolation having a top surface at a higher level than a
`surface of the active area and having a step portion in a
`boundary with the active area; and a step sidewall formed on
`the side surface of the step portion of the trench isolation.
`Owingto this structure, in the impurity ion injection for
`the formation of an impurity diffused layer of the semicon-
`ductor device, the step sidewall disposed at the edge of the
`trench isolation can prevent the impurity ions from being
`implanted below the edge of the isolation. Furthermore, also
`in adopting the structure including a source/drain electrode
`made ofsilicide, the step sidewall c