`
`s
`United States Patent
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`
`
`Dash etal.
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`
`
`FAUCETANE
`US003173439A
`
`
`[11] Patent Number:
`(5
`5,173,439
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`
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`[45] Date of Patent:
`Dec. 22, 1992
`
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`
`
`
`
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`[54] . FORMING WIDE DIELECTRIC-FILLED
`
`
`
`ISOLATION TRENCHESIN
`
`
`SEMI-CONDUCTORS
`
`
`
`Inventors: Somanath Dash; Michael L,
`
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`
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`Kerbaugh, both of Burlington;
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`Charles W. Koburger, III, Essex;
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`Brian J. Machesney, Burlington,all
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`of Vt.; Nitin B. Parekh, Austin, Tex.
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`International Business Machines
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`Corporation, Armonk, N.Y.
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`[21] Appl. No.: 679,568
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`
`:
`2,
`[22] Filed:
`2, 1991
`Apr.
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`[75]
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`[73] Assignee:
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`.
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`0341898 11/1989 European Pat. Off.
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`2599892 12/1987 France .
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`1/1984 Japan .
`59-13342
`
`
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`59-175138 10/1984 Japan ..
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`
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`59-177941 10/1984 Japan .
`
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`59-193044 11/1984 Japan .
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`60-236244 11/1985 Japan .
`
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`59-117233
`7/1989 Japan .
`
`
`
`’ OTHER PUBLICATIONS
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`
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`IBM Technical Disclosure Bull, vol. 30, No. 2 Gul.
`
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`
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`1987) pp. 539-540.
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`Primary Examiner—G. Fourson
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`Attorney, Agent, or Firm—Calfee, Halter & Griswold
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`[57]
`ABSTRACT
`
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`A methodofforminga planarized dielectric filled wide
`Related U.S. Application Data
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`[63]|Continuation of Ser. No. 427,153, Oct. 25, 1989, aban- shallow trench in a semi-conductor substrate is pro-
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`vided. A layer of etch stop such as Si3N4 is deposited
`doned.
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`5
`onto the semi-conductor substrate, and wide trenches
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`ee my a
`437enanon
`are formed through the Si3Nq into the substrate by con-
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`ventional RIE. The surface of the substrate including
`mes
`=
`, 437/228
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`the trenches have formed thereon a SiOcoating, con-
`[58] Field of Search
`437/62, 67, 69, 70.
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`forming to the surface of the substrate. A layer of etch
`437/72, 225 228,203:148/DIG. 50 DIG. 85,
`resistant material such as polysilicon is deposited onto
`Oe
`=“ DIG 86
`ELE
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`the SiQ2 material. The polysilicon outside the width of
`,
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`py
`.
`hes
`th
`Jj
`hanical
`is
`d by
`Ref
`Cited
`h
`ch
`the trenches is then removed
`by chemical-mechanica’
`eferences
`Cite
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`polishing to expose the SiOz there below, while leaving
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`the SiO2 above the trenches covered with polysilicon.
`US. PATENT DOCUMENTS
`
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`4,278,987 ....cseesecccssssrsesersense 357/48=The exposed SiOQ2 is then RIE etched down to the7/1981 UmaiZUmi
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`#376672 x,tons wane us
`SisNg,
`leaving a plug of SiOz capped with the etch
`Soar13ot
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`7/1985 Silveste;
`resistant polysilicon over each trench. These plugs are
`148/175
`4.526631
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`156/645
`then removed by mechanical polishing down to the
`4.671.851 6/1987 Beyer
`..
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`4,671,970
`6/1987 Keiser ™
`. 427/93
`$i3N4, to provide a planarized uppersurface of SiO2 and
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`6/1989 Breiten
`156/643
`Si3Nq4 on the top of the substrate. The invention also is
`4,836,885
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`4,962,069 10/1990 Haskell etal.sssssssssesessnn 437/228 useful in forming planarized surfaces on substrates hav-
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`ing trenchesfilled with conductive material.
`FOREIGN PATENT DOCUMENTS
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`1/1989 European Pat. Off.
`.
`0300569
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`56
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`14 Claims, 1 Drawing Sheet
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`18
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`10
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`1 1
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`0
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`Page 1 of 6
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`TSMC Exhibit 1058
`TSMCv. IP Bridge
`IPR2016-01246
`
`Page 1 of 6
`
`TSMC Exhibit 1058
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

`U.S. Patent
`
`Dec. 22, 1992
`
`5,173,439
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`12
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`|
`12
`[em
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`10
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`10
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`Fig.2
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`7LSL2AeLLL.
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`SESS
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`Page 2 of 6
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`1
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`5,173,439
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`FORMING WIDE DIELECTRIC-FILLED
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`ISOLATION TRENCHESIN SEMI-CONDUCTORS
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`2
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`rial, but with a semi-conductor material having a differ-
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`ent characteristic than the base substrate material. This
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`also uses a masking process.
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`U.S. application Ser. No. 189,863, filed May 3, 1988,
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`owned by the assignee of this invention, discloses an-
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`other technique for planarizing wide dielectric filled
`isolation trenches.
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`One of the principal objects of this invention is to
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`provide an improved method of forming dielectric
`filled wide trenches in a semi-conductor substrate
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`which is self-aligning and has resultant good planariza-
`tion.
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`- 0
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`- 5
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`This is a continuation of copending application Ser.
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`No. 07/427,153 filed on Oct. 25, 1989, now abandoned.
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`BACKGROUND OF THE INVENTION
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`This inventionrelates generally to the manufacture of
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`semi-conductor devices. More particularly, the inven-
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`tion relates to a method of forming planarized wide —
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`filled trenches in the surface of a semi-conductor sub-
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`strate, especially a silicon wafer, particularly filled with
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`SUMMARYOF THE INVENTION
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`dielectric material, although the invention also can be
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`used to form trenchesfilled with conductive material.
`A method or process for forming a wide, shallow
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`filled trench on the surface of a semi-conductor sub-
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`In the art of large-scale integrated chips, a large num-
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`ber of surface conductors are required for distribution
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`strate is provided, and in particular a dielectric filled
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`of operating voltages and currents and digital signals
`trench. The process includes forming a wide, shallow
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`between devices. Although surface conductors are insu-
`trench in the surface of the semi-conductor substrate
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`20
`lated from the semi-conductor substrate upon which
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`followed by conformally depositing a layer of dielectric
`they are formed, a certain amount of capacitive cou-
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`material on the surface of the substrates including in the
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`pling is present between the insulated conductor and the
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`trench. A layer ofetch-resistant material is deposited on
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`substrate through the insulating material. This capaci-
`the layer of the dielectric material. Portions of the etch
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`tive coupling degrades the signal carried by the surface
`resistant material outside the width of the trench are
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`conductors.
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`selectively removed, preferably by chemical-mechani-
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`While this capacitive coupling can be minimized by
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`cal polishing, such that the remaining portions of the
`increasing the thickness of the dielectric material sepa-
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`etch resistant material reside within the width of the
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`rating the conductors and the substrate,it is more desir-
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`trench. Following this, a dielectric plug is formed above
`able to recess the dielectric material below the surface
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`the trench by etching the layer of dielectric material
`of the substrate and maintain the planarity of the sub-
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`which is not covered by the etch resistant material
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`strate rather than add the dielectric material onto the
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`down to the top of the trench. Finally, the dielectric
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`surface of the substrate. This is accomplished by form-
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`plug is removed, preferably by polishing, to obtain a
`ing shallow trenches in the surface of the substrate, and
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`dielectric filled trench, having an upper surface in sub-
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`filling the trenches with dielectric material, normally
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`stantial planarity with the upper surface of the substrate.
`silicon dioxide. These trenches may be either narrow
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`This invention also can be used to fill.and planarize
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`trenches(i.e., less than about one micron in width, and
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`trenches with conductive material.
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`more typically about 0.5 microns) and wide trenches
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`DESCRIPTION OF THE DRAWINGS
`(i.e., those wider than about one micron).
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`is relatively simple to maintain planarity when
`It
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`40
`FIGS. 1 through 6 are cross-sectional views, some-
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`forming dielectric filled narrow trenches. However,
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`what diagrammatic, showing successive stages of pro-
`problems of maintaining planarity with the semi-con-
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`cessing of a semi-conductor having wide and narrow
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`ductor substrate and the dielectric material are pres-
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`shallow trenches formed,filled with dielectric material
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`ented with wide trenches because of the conformal
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`and planarized according to this invention.
`nature of the deposition of the dielectric and especially
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`DESCRIPTION OF THE PREFERRED
`silicon dioxide in the wide trenches.
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`EMBODIMENTS
`There have been several prior art proposals for solv-
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`ing these problems of forming planarized dielectric
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`Referring now to the drawings, and for the present,
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`filled wide trenches. One such proposal, described in
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`FIG. 1, there is shownasilicon semi-conductor sub-
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`U.S. Pat. No. 4,385,975 assigned to the assignee of this
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`strate 10 having an etch stop coating ofsilicon nitride
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`invention,utilizes a step in the process of depositing a
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`(Si3N4) 12 deposited thereon. Thesilicon nitride is typi-
`photoresist material through a mask over the dielectric
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`cally about 1000 A thick and can be deposited by con-
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`material contained in the trenches before planarization.
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`ventional means such as by chemical vapor deposition
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`The dielectric material is then reactive ion etched (RIE)
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`(CVD)from SiH2Cl2+NHs3at 400 mTorr, at 770° C.
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`with the photoresist masking the underlying material
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`The silicon nitride is then patterned by conventional
`from etching,thus resulting in a relatively planer struc-
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`photoresist techniques to reveal underlying openings
`ture. U.S. Pat. No. 4,671,970 also utilizes a photoresist
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`where both wide and narrow trenchesare to be formed.
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`as a mask for reactive ion etching ofdielectric material.
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`Two such trenches 14 and 16 are shown in FIG. 2
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`These teachings of masking, while somewhat effective,
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`formed in substrate 10 although it is to be understood
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`nevertheless have certain drawbacks. They require:
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`60
`that normally many such trenches are formed. The
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`extra masking and photolithographic steps, which adds
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`trench 14 is a wide trench, typically wider than about
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`two processing steps, and more importantly create sig-
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`one micron, and the trench 16 is a narrow trench,less
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`nificant problems of alignment; i.e., the mask must be
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`than one micron wide and typically about 0.5 microns
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`perfectly aligned to deposit the photoresist exactly
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`wide. These can be formed by conventional RIE etch-
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`within the conformalor trough portion of the deposited
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`ing in a well-known manner,such as, for example, in a
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`dielectric material to be utilized to mask just that dielec-
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`plasma of NF3+Ar at 10 mTorr and 0.1-0.2 W/cm?,
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`tric material desired and to exposetherest.
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`utilizing the photoresist as a mask material whichis a
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`US. Pat. No. 4,278,987 shows a somewhat different
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`well-known practice in the art. Other processes, also
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`techniqueforfilling trenches, not with dielectric mate-
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`25
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`Page 3 of 6
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`Page 3 of 6
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`3,173,439
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`3
`which are well-known, may be used to form the
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`trenches 14 and 16.
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`the present invention is espe-
`As indicated above,
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`cially useful for forming dielectric filled wide trenches;
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`however, FIGS.1 through6 illustrate how the present
`invention can be used on substrates which contain nar-
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`row trenches as well as wide trenches.
`.
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`As shownin FIG. 3, a layer of silicon dioxide (SiO2)
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`18 is formed over the surface ofthe substrate, including
`— 0
`both the wide and narrow trenches 14 and 16. Prefera-
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`bly the SiQ2 layer is deposited using well-known CVD
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`processes which typically includes vapor deposition in
`tetraethylorthosilane (TEOS) at 650 mTorr at 715° C.
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`Of course, other processes could be used. The thickness
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`of the CVD SiOzlayer is approximately equal to the
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`total depth ofthe trench so that the top of the SiOlayer
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`in the trench 14 is approximately even with the top
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`layer of the silicon substrate. This is typically about
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`6000 A. in thickness, although this can vary greatly with
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`different substrates, depending upon the utilization of 20
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`the substrates for forming devices and the type of con-
`ductors which are to be formed on the substrate.
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`Ontopofthesilicon dioxide layer 18 is formed a thin
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`layer of polysilicon 20 which typically is about 1000 A
`thick. This polysilicon can be deposited in any conven-
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`tional manner,
`a preferred method being CVD in
`SiH4+ H3 at 400 mTorrat 620° C. This resultant struc-
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`ture is shown in FIG. 3. This structure is then subjected
`to a chemical-mechanical polish to remove just that
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`portion of the polysilicon 20 which is located outside
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`the confines of the trench 14. In the preferred polishing
`technique the substrate is mounted onto a flat circular
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`holder which maintains the exposed surface of the
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`polysilicon 20 is contact with a rotating polyurethane
`pad. The pad is wetted with a slurry of an abrasive
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`material in a basic aqueoussolution, such as SiOz, plus
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`aluminum oxide (Al2O3) and tetramethylammonium
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`hydroxide (TMAH). As the polyurethane pad rotates
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`against the surface of the exposed polysilicon, the chem-
`icals react with the very outer-most surface of the
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`polysilicon 20 to loosen it from the polysilicon which
`underlies it. The mechanical or abrasive action of the
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`SiO? then removes this loosened surface whereverit
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`contacts it. Such chemical-mechanical polishing is well-
`knownin the art. This is a continuous process in that a
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`continuousreaction occurs at the outer surface with the
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`chemicals for loosening this layer and those loosened
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`portions of the polysilicon are removed by the abrasive
`action of the SiO).
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`The chemical-mechanical polishing continues until
`all of the polysilicon that lies outside of the boundaries
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`of the trench 14 has been removed as shownin FIG.4.
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`Coincidentally it can be seen that actually all of the
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`polysilicon has been removed from the surface of the
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`dielectric 18, filling the narrow trench 16. This, how-
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`ever, is not a problem because of the narrowness of the
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`trench 16, and there is very little conformality which is
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`indicated by the small indentation shown thereabove
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`andis not significant.
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`The material shown in FIG.4 is then anisotropically
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`etched by reactive ion etching (RIE). Typically this can
`be done in a CHF3+CO2 atmosphere at 0.1~-0.2
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`W/CM?and 40 mTorr. This RIE is reactive with the
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`SiOmaterial 18 but is not reactive with the polysilicon
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`65
`material 20. Thus, the SiO2 material not. masked by the
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`polysilicon material 20 is removed with thesilicon ni-
`tride layer 12 acting as an etch stop in a well-known
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`manner. This will result in the structure shown in FIG.
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`4
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`5 in which the underlying silicon nitride 12 has been
`revealed on both sides of the wide trench 14 and on
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`both sides of the narrow trench 16. Also, it should be
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`noted that with respect to the narrow trench 16,since
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`there was no polysilicon material overlying the silicon
`dioxide in the trench 16, that the etch was also reacting
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`with the SiO2 overlying the trench 16 to provide a
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`planarized surface of the dielectric material 18 with
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`respectto thesilicon nitride 12. However, with respect
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`to the material overlying the wide trench 14, a plug of
`material is left which comprises the SiOz material un-
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`derlying the polysilicon 20. This plug of material ex-
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`tends significantly above the planarized level of the
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`silicon nitride 12, thus providing essentially a planarized
`surface over all of the substrate, except over any
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`trenches wherethere are these plugs of material.
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`The entire wafer shown in FIG. 5 is then again
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`chemically-mechanically polished using a silica slurry
`in basic aqueous solution and polished against a rotating
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`polyurethane disk. This polishing step will remove the
`plugs of material which are above the wide trenches 14
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`resulting in a final structure shown in FIG. 6. Thesili-
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`con nitride12 acts as the end point for the polishing so
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`that the entire surface of the wafer which includes both
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`wide and narrow trenchesfilled with silicon dioxide are
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`essentially planarized and hence ready for further pro-
`cessing such as the formation of the conductor patterns
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`on the surface.
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`Several modifications can be made to the process.
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`For example, a thin (50 nm)layer ofpolysilicon can be
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`deposited over the silicon nitride layer 12. This will
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`improve the selectivity of the SiO2 RIE, making com-
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`plete removal thereof more feasible without impairing
`the uniformity of the silicon nitride etch stop. Also a
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`thin (50 nm)layer of silicon nitride can be deposited
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`over the SiO2 layer 18 before the deposition of the
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`polysilicon layer 20. This will help prevent reduction of
`the SiOz layer during the first chemical-mechanical
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`polishing step for the remaining polysilicon layer 20
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`overlying the trenches 18.
`It is also contemplated that similar process steps can
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`be used to form planarized surfaces wherein trenches
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`are filled with conductive materials rather than dielec-
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`tric material. In such case, the masking materials and
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`etch reagents and conditionsare selected to provide the
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`selectivity required.
`While several embodiments of the present invention
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`have been shown and described, various adaptions and
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`modifications can be made without departing from the
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`scope of the invention as defined in the appended
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`claims.
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`Whatis claimed is:
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`1. A process for forming a wide dielectric-filled isola-
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`tion trench in the surface of a semi-conductor substrate
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`comprising the steps of:
`forming a wide trench in the surface ofthe substrate;
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`conformally forming a layer of dielectric material
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`over the surface of the substrate including in said
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`trench the top surface of which layerof dielectric
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`material extends above the plane of the surface of
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`the substrate;
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`conformally forming a layer of etch resistant material
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`onsaid layerof dielectric material which etch resis-
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`tant material will mask said dielectric material from
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`reactive ion etching;
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`selectively removing only those portionsofsaid etch
`resistant material that extend above the surface of
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`the dielectric material by physical polishing and
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`_ we
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`30
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`55
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`60
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`Page 4 of 6
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`Page 4 of 6
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`

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`5,173,439
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`5
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`not removing any etch resistant material disposed
`below the surface of said dielectric material, such
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`that the only remaining portion of the etchresistant
`material resides within the width of said trench;
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`forming a dielectric plug above said trench compris-
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`ing the remaining etch resistant material overlying
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`dielectric material by anisotropically reactive ion
`etching said layer of dielectric material which is
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`not masked bysaid etch resistant material down to
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`the top of said trench; and
`:
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`removing said dielectric plug to obtain a dielectric-
`filled trench having an upper surface in substantial
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`planarity with the upper surface ofsaid substrate.
`2. The invention as defined in claim.1 wherein said
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`dielectric material forms a depression above the wide
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`trench.
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`3. The invention as defined in claim 1 wherein said
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`etch-resistant material is polysilicon.
`4. The invention as defined in claim 3 wherein the
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`selective removal of polysilicon comprises chemical-
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`mechanicalpolishing.
`5. The method of claim 4 wherein the chemical me-
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`chanical polishing of the polysilicon is done with a
`slurry of abrasive material maintained in a basic aqueous
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`solution.
`-
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`6. The invention as defined in claim 1 wherein said
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`plug material is removed downto the top ofthe trench
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`by chemical-mechanical polishing.
`7. The invention as described in claim 6 wherein a
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`layer of etch stop material is provided on the surface of
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`said semi-conductorsubstrateat least in the region adja-
`cent said wide trenches, and said layer of dielectric
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`material which is not masked by said etch resistant
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`material is etched down to the etch stop layer.
`8. The invention as defined in claim 1 wherein said
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`dielectric material is silicon dioxide.
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`9. The invention as defined in claim 7 wherein said
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`etch stop material is silicon nitride.
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`6
`10. The invention as defined in claim 9 wherein a
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`layer of polysilicon is formed between said silicon ni-
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`tride layer and said layer of dielectric material to pro-
`vide an etch stop for silicon dioxide removal.
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`11. The invention as defined in claim 7 wherein a
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`layer of silicon nitride is formed over the dielectric
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`material.
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`12. A process for forming a filled wide trench in the
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`surface of a substrate comprising thesteps of:
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`forming a wide trench in the surface ofthe substrate;
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`conformally forminga layer offilling material on the
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`surface of the substrate including in said trench the
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`top surface of which filling material extends above
`the plane of the surface of the substrate;
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`conformally forming a layerof etch-resistant material
`on said layer offilling material which etch resistant
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`material wil] mask said filling material from reac-
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`tive ion etching;
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`selectively removing only those portionsof said etch
`resistant material that extend above the surface of
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`the filling material by physical polishing and not
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`removing any etch resistant material disposed
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`below the surfaceofsaid filling material, such that
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`the only remaining portion of the etch resistant
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`material resides within the width ofsaid trench;
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`forming a plug above said trench comprising the
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`remaining etch resistant material overlyingfilling
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`material by anisotropically etching said layer of
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`filling material which is not masked by said etch
`resistant material down to the top of said trench;
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`and
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`removing said plug to obtaina filled trench having an
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`upper surface in substantial planarity with the
`upper surface of said substrate.
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`13. The invention as defined in claim 12 wherein said
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`filling material is a conductive material.
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`14. The invention as defined in claim 12 wherein said
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`filling material is a dielectric material.
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`*
`*
`*
`*
`*
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`Page 5 of 6
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`Page 5 of 6
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`

`

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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`
`CERTIFICATE OF CORRECTION
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`
`PATENTNO.
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`:
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`
`5,173,439
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`DATED
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`INVENTOR(S}:
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`:
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`Dec. 22, 1992
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`Dash, et al.
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`It is certified that error appears in the above-identified patent and that said Letters Patentis hereby
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`corrected as shown below:
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`Column 5,
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`line 33 change "trenches, and" to --trench, and--
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`Signed and Sealed this
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`Second Day of November, 1992
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`Attest:WSence (fy
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`Attesting Officer
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`Commissioner of Patents and Trademarks
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`BRUCE LEHMAN
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`Page 6 of 6
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`Page 6 of 6
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