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`IEEE 1993 Bipolar Circuits and Technology Meeting 3.3
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`A TrenchIsolation Process for BICMOSCircuits
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`Stephen Poon and Craig Lage
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`Advanced Products Research and Development Laboratory, MotorolaInc.,
`3501 Ed Bluestein Blvd., Austin, Texas 78721
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`ABSTRACT
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`A newisolation process using 1 um deep trenchis
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`developed for BiCMOS circuits. Well behaved
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`MOSFETs and NPN devices with excellent parasitic
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`performance were achieved. Low leakage diodes with
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`butted junctions were demonstrated by inclusion of an
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`oxidation barrier in the trench liner and utilizing a GeOQ2
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`doped oxide with matched thermal coefficient of
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`expansion to the silicon substrate for trench fill.
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`Planarity for arbitrary width isolation was obtained by
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`using oxide RIE followed by chemical-mechanical
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`polishing.
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`INTRODUCTION
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`Trench isolation has been reported since the early
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`1980's as a replacement for LOCOSisolation for VLSI.
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`However, process complexity associated with trench
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`technology hasrestricted its appealto a limited number
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`of circuit applications while continuous modifications
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`and improvements to LOCOS has enabled its
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`implementation in a proposed 16 Mbit fast SRAM cell
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`with 1 um active pitch [1]. Nevertheless, LOCOSis not
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`expected to scale significantly beyond 1 um pitch due
`to its intrinsic limitations such as field oxide thinning,
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`bird's beak encroachment,
`lack of planarity, and
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`punchthrough. As a result, trench isolation is required
`to meet the demands of ULSI. However,a relatively
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`simple process with sufficient benefits must be
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`developed to gain wide acceptance.
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`In this paper, a single isolation processutilizing a 1
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`uum deeptrench with arbitrary width is proposed for
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`BiCMOScircuits to avoid the complexity of shallow and
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`deep trench isolation typically employed in high
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`performance BiCMOStechnology [2]. A schematic
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`representation of the structure is shown in Figure 1.
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`Latchup immunity,
`intrawell and interwell isolations,
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`reduced parameter capacitance, as well as bipolar
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`parasitic reduction are simultaneously satisfied with the
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`proposed structure. The processing technique used
`to fabricate this structure and the electrical results
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`achieved are described.
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`FABRICATION
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`The processplatform was adopted from a 0.5 um
`BiCMOStechnology developed for 4 Mbit fast SRAMs
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`[3]. Epi thickness is optimized to ensure up-diffusion
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`from the buried layers to merge with the trench bottom
`to obtain the desired isolation and parasitic
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`characteristics. A hard mask is used to protect the
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`active regions for etching of a 1 um depth trench into
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`the substrate. Both thermal oxide and composite
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`thermal oxide/deposited nitride trench liners were
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`evaluated along with several chemical vapor deposited
`oxides to determine the most suitable combination of
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`CH3315-9/93/0000(0045)$1.00 © 1993 IEEE
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`processes to minimize defect generation in the
`substrate and to minimize seam or void formation in
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`narrow width trenches.
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`A combination of oxide RIE and chemical
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`mechanical polishing process [4,5] is used for the
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`planarization of arbitrary width trench. A schematic
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`cross section of the pianarization process sequenceis
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`shownin Figure 2. Comparedto [4], this planarization
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`sequence has a reduced number of process steps and
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`has replaced the more complex planarization etchback
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`process with an oxide RIE process. At this point, MOS
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`and bipolar devices were fabricated using previously
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`reported processes [3] to evaluate the merit of the
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`proposed structure.
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`RESULTS AND DISCUSSION
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`Transistor characteristics were measured on both
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`CMOSand non-self-aligned NPN devices. Typical 0.5
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`um Wdrawn subthreshold characteristics are shownin
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`Figure 3. Both n- and p- channel devices exhibit ideal
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`behavior with no degradation of the subthreshold
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`slope. A Gummelplot for 0.8 um emitter NPN is shown
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`in Figure 4.
`Functional BICMOS and ECL ring
`oscillators were also achieved.
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`Field punchthrough voltage on intrawell and
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`interwell isolation structures are shown in Figure 5.
`Results measured on trench isolated structures were
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`independent offield width and are well above 10 voits.
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`Holding voltage for latchup and parasitic bipolar gain
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`are improved compared to a PBLisolation control
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`because current path in the substrate is interrupted by
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`the trench bottom reaching into up-diffusion from the
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`buried layer. These results are shown in Figures 6 and
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`7, respectively. A SEM micrograph whichillustrates this
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`is shownin Figure 8.
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`Deposited oxides are typically known to create
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`voids and weak seamsin narrow width and high aspect
`ratio trenches after wet strips/cleans due to poor step
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`coverage. However, this problem is improved with
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`ozone enhanced depositions
`[6,7] and ECR
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`deposited films. Leakage current measured between
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`gate poly combsin an on-pitch array for two different
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`oxide trenchfill is shown in Figure 9. A TEM cross
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`section micrograph showing planar and defect-free
`isolation trench is shown in Figure 10.
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`In order to alleviate stress induced leakage caused
`by substrate defects due to oxidation and other
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`thermal processes in 1 um deep oxidefilled trench,
`composite thermal oxide/CVD nitride trench liner [8,9]
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`and trench fill with matched thermal coefficient
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`expansion to the substrate [6] were evaluated. Stress
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`Page 1 of 4
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`TSMC Exhibit 1048
`TSMCv. IP Bridge
`IPR2016-01246
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`Page 1 of 4
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`TSMC Exhibit 1048
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

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`IEEE 1993 Bipolar Circuits and Technology Meeting 3.3
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`[6] J. Bell, S. Fisher, K. Maeda, and S. Poon,
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`‘Characterization of Germanium Doping in
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`TEOS/Ozone Films for Trench Fill Applications’,
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`Schumacher Dielectrics and CVD Metallization
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`Symp. Proceedings, February, 1993.
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`[7] J.P. West, H.W. Fry, and S. Poon, 'The Application
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`of APCVD/Ozone Thin Films in < 0.5 um IC
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`Fabrication: Trench and Inter-metal Isolation and
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`Gap Fill’, SPIE International Symposium on
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`Microelectronic Processing, September, 1993.
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`[8] C.W. Teng, C. Slawinski, and W.R. Hunter, 'Defect
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`Generation in Trench Isolation’,
`IEDM Technical
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`Digest, pp. 586 - 589, 1984.
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`[9] S.R. Stiffler, J.B. Lasky, C.W. Koburger, and W.S.
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`Berry, ‘Oxidation-Induced Defect Generation in
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`Advanced DRAM Structures’, IEEE Trans. Electron
`Devices, vol. 37, no. 5, pp. 1253 - 1258, 1990.
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`measurement obtained on oxide trenchfill film doped
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`with GeO2 is shownin Figure 11. Leakage measured
`on butted diodes with and without nitride liner are
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`compared in Figure 12.
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`Gate oxide thinning at the trench corner which can
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`degradeintrinsic dielectric breakdown was avoided by
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`careful optimization of the process module. The
`results are shownin Figure 14.
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`SUMMARY
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`A simple trench isolation process that can
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`simultaneously satisfy several
`requirements for
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`submicron BiCMOS circuits
`is proposed and
`described. Well-behaved devices with excellent
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`isolation and parasitic characteristics are demonstrated.
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`ACKNOWLEDGEMENTS
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`The authors wish to thank Phil Tobin, Asanga
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`Perera, Fred Walczyk, David Burnett, Hsing Tseng,
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`Jeff Lutze, and Jerry Sebek for technical discussions
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`and measurements. Process support from Jung-Hui
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`Lin, Kent Cooper, and the pilot
`line personnel of
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`APRDL. Vendor support
`from Mel Hoffman of
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`Westech, Jeff Bell of QT!, Todd Curtis of Watkins-
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`Johnson, and the ECR process engineering team of
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`Lam Research are sincerely appreciated. Rick Sivan
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`and Lou Parrillo are acknowledgedfor their managerial
`support.
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`REFERENCES
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`[1] J.D. Hayden, M.P. Woo, R.C. Taft, P. Petley, B.-Y.
`
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`Nguyen, C. Mazure, P.U. Kenkare, K. Kemp, R.
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`Subrahmanyan, A.R. Sitaram, J-H. Lin, J. Ko, C.
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`King, C. Gunderson, and H.C. Kirsch,
`'A High-
`
`
`
`
`
`
`
`Performance Quadruple Well, Quadruple Poly
`
`
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`
`
`BiCMOS Process for Fast 16Mb SRAMs',
`IEDM
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`Technical Digest, pp. 819 - 822, 1992.
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`[2] G.G. Shahidi, J. Warnock, B. Davari, B. Wu, Y. Taur,
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`C. Wong, C.L. Chen, M. Rodriguez, D.D. Tang, K.
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`Jenkins, P.A. McFarland, R. Schulz, D. Zicherman,
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`P. Coane, D. Klaus, J.Y.C. Sun, M. Polcari, and T.H.
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`
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`‘A High Performance BICMOS Technology
`Ning,
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`
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`Using 0.25 um CMOS and Double Poly 47 GHz
`
`Bipolar’, VLSI Tech. Symp. Digest, pp. 28 - 29,
`1992.
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`[3] T.C. Mele, J. Hayden, F. Walezyk, M. Lien, Y.C.
`
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`See, D. Denning, S. Gosentino, and A.H. Perera, 'A
`
`
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`
`
`High Performance 0.5 um BiCMOS Triple
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`
`
`Polysilicon Technology for 4Mb Fast SRAMs', IEDM
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`Technical Digest, pp. 481 - 484, 1990.
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`[4] B. Davari, C.W. Koburger, R. Schulz, J.D. Warnock,
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`T. Furukawa, M. Jost, Y. Taur, W.G. Schwittek, J.K.
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`DeBrosse, M.L. Kerbaugh, and J.L. Mauer, ‘A New
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`Planarization Technique, Using a Combination of
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`RIE and Chemical Mechanical Polish (CMP)' IEDM
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`Technical Digest, pp. 61 - 64, 1989.
`
`
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`[5] S. Poon, A. Gelatos, A.H. Perera, and M. Hoffman,
`‘A Manufacturable Chemical-Mechanical Polish
`
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`
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`
`
`
`
`
`
`Technology with a Novel Low-Permittivity Stop-
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`
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`
`
`Layer for Oxide Polishing’, VLSI Tech. Symp.
`Digest, pp. 115 - 116, 1993.
`
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`Page 2 of 4
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`46
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`Page 2 of 4
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`

`

`PMOS
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`NMOS
`
`BIPOLAR
`
`Oxide Filled Trench
`
`Deep N+
`
`P SUBSTRATE
`
`Fig. 1 Trench Isolated BiCMOSArchitecture
`
`IEEE 1993 Bipolar Circuits and Technology Meeting 3.3
`
`Nitride/Pad Oxide
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`|
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`|
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`|
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`| Deposited Oxide |
`
`Reverse Density
`Photoresist
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`Oxide RIE
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`CMP
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`Fig. 2 Planarization Process Sequence
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`ID(A)
`1E-3
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`j
`
`1E-9
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`1E-11
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`SLOPE =
`85.3 mV/dec
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`| (A)
`
`1E-5
`
`1E-7
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`1E-9
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`1E-11
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`
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`o 1.8 8
`
`1E-1/—1E-3
`1E-5
`|
`1E-7
`
`ha
`/
`tE-13, S8.9mVideo\wH IVDI=0.1,5 V
`
`0
`-0.3
`-0.6
`-0.9
`-1.2
`-1.8
`-0.9
`0
`0.9
`1.8
`VE (V)
`VG (V)
`Fig. 3 MOS Subthreshold Characteristics
`
`INTERWELL
`
`S »
`s
`2 11
`8
`£
`5 10
`S
`2°
`>
`
`E
`&i7
`3
`£16
`£
`$15
`Su
`a
`>143
`s
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`681
`* Fieid Space(um)
`Field Space (jm)
`Fig. 5 Field Punchthrough Voltage
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`7
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`°
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`Page 3 of 4
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`Fig. 4 Bipolar Characteristics
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`(Holding
`Voltage
`<2V)
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`Fig. 6 Latch-Up Characteristics
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`47
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`IEEE 1993Bipolar Circuits and Technology Meeting 3.3
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`Ozoneoxide
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`PBL
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`Percent
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`\
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`Trench
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`12
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`08
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`09
`06
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`VB (V)
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`Fig. 7 Parasitic PNPBipolar Gain
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`15
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`Beta
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`1642
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`1E+
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`1E0
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`te
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`1E2
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`0
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`Percent
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`a 0 96 9
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` a
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`Fig, 10
`
`
`
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`
`
`
`
`TEM micrograph showing planarand defectfree trench
`
`
`
`60
`a0
`—
`
`
`
`
`Nitride Liner||No Nitride Liner Unoptimized
`
`
`
`
`
`
`
`
`Procass
`50
`
`
`
`«0
`
`
`
`
`
`
`
`4
`
`
`
`
`c
`8
`
`5 20
`a
`
`
`
`
`
`
`20
`
`
`
`
`
`1000
`
`
`
`A2
`
`
`
`
`
`
`
`800
`
`
`
`20
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`
`
`40600
`
`
`
`
`Temperature (°C}
`
`
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`
`
`Fig, 11 {n-situ Stress vs. Temp
`
`
`c
`Qo
`Q
`
`£4)
`
`
`a
`
`20
`
`
`
`4
`
`
`
`
`0.9 6
`9
`12 15 18
`
`
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`Vottage (V})
`
`
`
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`
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`Fig. 13 Gate Oxide Breakdown (Perim. = 78 cm)
`
`
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`12 15 18
`
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`Voltage (V)
`
`
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`urfent
`
`
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`4
`
`
`
`
`
`
`
`“10
`
`
`
`“ent
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`
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`Log Curren
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`
`Log G
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`Fig, 12 N+ Junction Leakage (Perim.= 40 cm}
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`Page 4 of 4
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`48
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`Page 4 of 4
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`€
`€
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