SILICON PROCESSING
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`FOR
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`THE VLSI ERA
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`VOLUME1:
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`PROCESS TECHNOLOGY
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`STANLEY WOLFPh.D. »
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`Professor, Departmentof Electrical Engineering
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`California State University, Long Beach
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`Long Beach, California
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`and
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`Instructor, Engineering Extension, University of California, Irvine
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`_
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`RICHARD N. TAUBERPh.D.
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`Manager of VLSI Fabrication
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`TRW - Microelectronics Center
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`Redondo Beach, California
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`and
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`Instructor, Engineering Extension, University of California, Irvine
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`LATTICE
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`PRESS
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`DISCLAIMER
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`Copyright©1986b) Lattice Press
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`All rights reserved. No part of this book may be reproduced or transmitted in any form or by any
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`Library of Congress Cataloging in. Publication Data
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`Wolf, Stanley
`and Tauber, Richard N.
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`Silicon Processing for the VLSI Era
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`Volume 1: Process Technology
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`Includes Index
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`1. Integrated circuits-Very large scale
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`integration.
`I. Title
`2. Silicon.
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`86-081923
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`ISBN 0-961672-3-7
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`98765 4
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`PRINTED IN THE UNITED STATES OF AMERICA
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`Page 2 of 15
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`Page 2 of 15
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`PREFACE
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`CONTENTS
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`vii
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`PROLOGUE
`xxi
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`1. SILICON: SINGLE-CRYSTAL GROWTH AND WAFERING 1.
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`- TERMINOLOGY OF CRYSTAL STRUCTURE,1
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`- MANUFACTURE OF SINGLE-CRYSTAL SILICON,5
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`From Raw Material to Electronic Grade Polysilicon
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`- CZOCHRALSKI(CZ) CRYSTAL GROWTH,8
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`Czochralski Crystal Growth Sequence
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`Incorporation of Impurities into the Crystal (Normal Freezing)
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`Modifications Encountered to Normal Freezing in CZ Growth
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`Czochralski Silicon Growing Equipment
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`Analysis of Czochralski Silicon in Ingot Form
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`Measuring Oxygen and Carbonin Silicon Using Infrared Absorbance Spectroscopy
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`_ FLOAT-ZONE SINGLE-CRYSTALSILICON,21
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`- FROM INGOTTO FINISHED WAFER:SLICING; ETCHING; POLISHING,23
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`- SPECIFICATIONS OF SILICON WAFERS FOR VLSI, 26
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`- TRENDSIN SILICON CRYSTAL GROWTH AND VLSI WAFERS,30
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`2. CRYSTALLINE DEFECTS, THERMAL PROCESSING,
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`AND GETTERING
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`36
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`- CRYSTALLINE DEFECTSIN SILICON,37
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`Point Defects
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`One-Dimensional Defects (Dislocations)
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`Area Defects (Stacking Faults)
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`Bulk Defects and Precipitation
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`INFLUENCE OF DEFECTS ON DEVICE PROPERTIES,51
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`Leakage Currents in pn Junctions
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`Collector-Emitter Leakage in Bipolar Transistors
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`Minority Carrier Lifetimes
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`Gate Oxide Quality
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`Threshold Voltage Control
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`Wafer Resistance to Warpage
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`Page 3 of 15
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`Page 3 of 15
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`xii
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`CONTENTS
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`- CHARACTERIZATION OF CRYSTAL DEFECTS,55
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`- THERMAL PROCESSING, 56
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`Rapid Thermal Processing (RTP)
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`- OXYGENIN SILICON,59
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`- GETTERING,61
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`Basic Gettering Pinciples
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`Extrinsic Gettering
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`Intrinsic Gettering
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`3. VACUUM TECHNOLOGY FOR VLSI APPLICATIONS
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`73
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`- FUNDAMENTAL CONCEPTS OF GASES AND VACUUMS,73
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`Pressure Units
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`Pressure Ranges
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`Mean Free Path and Gas Flow Regimes
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`- LANGUAGEOF GAS /SOLID INTERACTIONS, 77
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`- TERMINOLOGY OF VACUUM PRODUCTION AND PUMPS,78
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`- ROUGHING PUMPS, 85
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`Oil-Sealed Rotary Mechanical Pumps
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`Pump Oils
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`Roots Pumps
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`- HIGH VACUUM PUMPSI: DIFFUSION PUMPS, 89
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`- HIGH VACUUM PUMPSII: CRYOGENIC PUMPS,92
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`- HIGH VACUUM PUMPSIII: TURBOMOLECULAR PUMPS,95
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`- SPECIFICATION OF VACUUM PUMPSFOR VLSI, 97
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`- TOTAL PRESSURE MEASUREMENT,97
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`- MEASUREMENTSOF PARTIAL PRESSURE:Residual Gas Analyzers, 101
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`Operation of Residual Gas Analyzers (RGA)
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`RGAs and Non-High Vacuum Applications: Differential Pumping
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`Interpretation of RGA Spectra
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`RGA Specification List
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`- HIGH GAS FLOW VACUUM ENVIRONMENTSIN VLSI PROCESSING,104
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`Medium and Low-Vacuum Systems
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`Throttled High-Vacuum Systems
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`109 |
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`4. BASICS OF THIN FILMS
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`- THIN FILM GROWTH,110
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`- STRUCTURE OF THIN FILMS,111
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`- MECHANICAL PROPERTIES OF THIN FILMS, 113
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`Adhesion
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`Stress in Thin Films
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`Other Mechanical Properties
`
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`- ELECTRICAL PROPERTIES OF METALLIC THIN FILMS, 118
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`Electrical Transport in Thin Films
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`Page 4 of 15
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`Page 4 of 15
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`CONTENTS
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`5. SILICON EPITAXIAL FILM GROWTH
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`xiii
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`124
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`- FUNDAMENTALS OF EPITAXIAL DEPOSITION,125
`The Grove Epitaxial Model
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`Gas Phase Mass Transfer
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`Atomistic Model Of Epitaxial Growth
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`- CHEMICAL REACTIONS USEDIN SILICON EPITAXY, 133
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`- DOPING OF EPITAXIAL FILMS,136
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`Intentional Doping
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`Autodoping and Solid-State Diffusion
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`- DEFECTSIN EPITAXIAL FILMS, 139
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`Defects Induced During Epitaxial Deposition and their Nucleation Mechanisms
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`Techniques for Reducing Defects in Epitaxial Films
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`- PROCESS CONSIDERATIONS FOR EPITAXIAL DEPOSITION,142
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`Pattern Shift, Distortion, and Washout
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`- EPITAXIAL DEPOSITION EQUIPMENT,145
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`- CHARACTERIZATION OF EPITAXIAL FILMS, 147
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`Optical Inspection of Epitaxial Films
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`Electrical Characterization
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`Epitaxial Film Thickness Measurements
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`Infrared Reflectance Measurement Techniques
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`- SILICON ONINSULATORS,151
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`Silicon on Sapphire
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`Silicon on Other Insulators
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`- MOLECULAR BEAM EPITAXYOF SILICON, 156
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`6. CHEMICAL VAPOR DEPOSITION OF AMORPHOUS
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`AND POLYCRYSTALLINE FILMS
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`161
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`- BASIC ASPECTS OF CHEMICAL VAPOR DEPOSITION,162
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`- CHEMICAL VAPOR DEPOSITION SYSTEMS, 164
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`Components of Generic CVD Systems
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`Terminology of CVD Reactor Design
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`Atmospheric Pressure CVD Reactors
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`Low-Pressure CVD Reactors
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`Plasma-Enhanced CVD:Physics; Chemistry; and Reactor Configurations
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`Photon-Induced CVD Reactors
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`- POLYCRYSTALLINE SILICON: PROPERTIES AND CVD DEPOSITION, 175
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`Properties of Polysilicon Films
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`CVD of Polysilicon
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`Doping Techniques for Polysilicon
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`Oxidation of Polysilicon
`
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`- PROPERTIES AND DEPOSITION OF CVD SiO, FILMS, 182
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`Chemical Reactions for CVD Formation
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`Step Coverage of CVD SiO,
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`Undoped CVD SiO
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`Page 5 of 15
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`Page 5 of 15
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`xiv
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`CONTENTS
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`Phosphosilicate Glass
`
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`Borophosphosilicate Glass
`
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`- PROPERTIES AND CVD OFSILICON NITRIDE FILMS, 191
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`- OTHER FILMS DEPOSITED BY CVD (OXYNITRIDESand SIPOS), 195
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`7. THERMAL OXIDATION OF SINGLE-CRYSTAL SILICON 198
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`- PROPERTIES OF SILICA GLASS, 199
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`- OXIDATIONKINETICS, 200
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`The Linear-Parabolic Model
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`- THE INITIAL OXIDATION STAGE,207
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`Growth of Thin Oxides
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`- THERMAL NITRIDATIONOF SILICON AND SiO,, 210
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`- FACTORS WHICH AFFECT THE OXIDATION RATE,211
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`Oxidation Growth Rates: Crystal Orientation Dependence
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`Oxidation Growth Rates: Dopant Effects
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`Oxidation Growth Rates: Water (HO) Dependence
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`Oxidation Growth Rates: Chlorine Dependence
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`Oxidation growth Rates: Pressure Effects
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`Oxidation Growth Rates: Plasma and Photon Effects
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`- MASKING PROPERTIES OF THERMALLY GROWN SiO,, 219
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`- PROPERTIES OF THE Si SiO, INTERFACE AND OXIDE TRAPS, 220
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`Interface Trap Charge
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`Fixed Oxide Charge
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`Mobile Ionic Charge
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`Oxide Trapped Charge
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`Nature of the Si /SiO, Interface
`
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`- STRESS IN SiO,, 228
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`- DOPANT IMPURITY REDISTRIBUTION DURING OXIDATION,228
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`- OXIDATION SYSTEMS,230
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`Horizontal Furnaces
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`Suspended Loading Systems
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`Vertical Furnaces
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`- MEASUREMENT OF OXIDE THICKNESS,234
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`8. DIFFUSION IN SILICON |
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`242
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`- MATHEMATICS OF DIFFUSION,242
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`Ficks First Law
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`Ficks Second Law
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`Solutions to Ficks Second Law
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`Concentration Dependence of the Diffusion Coefficient
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`- TEMPERATURE DEPENDENCE OF THE DIFFUSION COEFFICIENT, 250
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`- DIFFUSION CONSTANTSOF THE SUBSTITUTIONAL
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`IMPURITIES: B; As; and P, 251
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`Arsenic Diffusion
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`Page6 of 15
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`Page 6 of 15
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`CONTENTS
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`xv
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`Boron Diffusion
`
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`Phosphorus Diffusion
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`- ATOMISTIC MODELS OF DIFFUSIONIN SILICON,256
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`The Vacancy Model
`
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`The Vacancy-Interstitial Model
`
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`- DIFFUSION IN POLYCRYSTALLINE SILICON,261
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`- DIFFUSION IN SiO,, 262
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`- ANOMALOUS DIFFUSION EFFECTSIN SILICON, 262
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`Emitter Push Effect
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`Lateral Diffusion Under Oxide Windows
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`Diffusion in an Oxidizing Ambient
`
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`- DIFFUSION SYSTEMS AND DIFFUSION SOURCES, 264
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`Gaseous Sources
`
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`Liquid Sources
`
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`Solid Sources
`
`
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`- MEASUREMENT TECHNIQUES FOR DIFFUSED LAYERS, 267
`
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`Sheet Resistivity Measurements
`Junction Depth Measurements
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`Doping Profile Measurements
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`9. ION IMPLANTATION FOR VLSI
`
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`280
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`- ADVANTAGES (AND PROBLEMS)OF ION-IMPLANTATION,282
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`- IMPURITY PROFILES OF IMPLANTEDIONS, 283
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`Definitions Associated with Ion Implantation Profiles
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`Theory of Ion Stopping
`Models for Predicting Implantation Profiles in Amorphous Solids
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`Implanting into Single-Crystal Materials: Channeling
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`Boltzmann Transport Equation and Monte-Carlo Approaches to Calculating Profiles
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`- ION IMPLANTATION DAMAGE AND DAMAGEANNEALINGIN SILICON,295
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`Implantation Damage in Silicon
`
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`Electrical Activation and Implantation Damage Annealing
`
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`- ION IMPLANTATION EQUIPMENT,309
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`Components of an Ion Implantation System
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`Ion Implanter Types
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`Ion Implantation Equipment Limitations
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`Ion Implantation Safety Considerations
`
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`- CHARACTERIZATION OF ION IMPLANTATIONS,318
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`Measurement of Implantation Dose and Dose Uniformity
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`Measurement of Implantation Depth Profiles
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`Measurement of Implantation Damage and Damage Annealing Efficacy
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`- ION IMPLANTATION PROCESS CONSIDERATIONS,321
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`Selecting Masking Layer Material and Thickness
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`Implanting Through Surface Layers
`7
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`Shallow Junction Formation by Ion-Implantation
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`Multiple Implantations
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`Page 7 of 15
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`Page 7 of 15
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`xvi
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`CONTENTS
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`10. ALUMINUM THIN FILMS AND
`
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`PHYSICAL VAPOR DEPOSITION IN VLSI
`
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`331
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`- ALUMINUM THIN FILMSIN VLSI, 332
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`- SPUTTER DEPOSITION OF THIN FILMS FOR VLSI, 335
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`Properties of Glow-Discharges
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`Physics of Sputtering
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`Sputter Deposited Film Growth
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`Radio-frequency (RF) Sputtering
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`Magnetron Sputtering
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`Bias Sputtering
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`Sputter Deposition Equipment
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`Commercial Sputtering System Configurations
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`Process Considerations in Sputter Deposition
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`Reactive Sputtering
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`Future Trends in Sputter Deposition
`
`
`
`- PHYSICAL VAPOR DEPOSITION BY EVAPORATION,374
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`
`Evaporation Basics
`
`Evaporation Methods
`
`
`
`Evaporation Process Considerations
`
`
`
`
`- METAL FILM THICKNESS MEASUREMENT,380
`
`
`
`11. REFRACTORY METALS and THEIR SILICIDESin1 VLSI
`
`
`
`
`
`
`- CANDIDATE SILICIDES FOR VLSI APPLICATIONS, 386
`
`
`
`
`
`
`
`
`Silicide Resistivities
`
`
`- SILICIDE FORMATION,388
`Direct Metallurgical Reaction.
`
`
`
`
`Co-Evaporation
`
`
`Sputter Deposition: Co-Sputtering and Sputtering from Composite Targets
`
`
`
`
`
`
`
`
`Chemical Vapor Deposition
`
`
`
`
`- STRESS IN SILICIDES, 394
`
`
`
`- OXIDATION OF SILICIDES, 395
`
`
`
`- PROCESS INTERACTION, 397
`
`
`- SELF-ALIGNEDSILICIDE (SALICIDE) TECHNOLOGY,:397
`
`
`
`
`
`- REFRACTORY METAL INTERCONNECTIONS FOR VLSI, 399
`
`
`
`
`
`
`Deposition of CVD Tungsten
`
`
`
`
`
`Selective Deposition. of Tungsten
`
`
`
`
`
`Properties of CVD Tungsten for VLSI Contacts
`
`
`
`Future Trends
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`384
`
`
`
`
`
`
`
`12. LITHOGRAPHY I: OPTICAL_PHOTORESISTS:-
`
`
`
`
`
`MATERIAL PROPERTIES AND PROCESS TECHNOLOGY 407
`
`
`
`
`
`- BASIC PHOTORESIST TERMINOLOGY, 407
`
`
`
`
`
`
`
`Page 8 of 15
`
`Page 8 of 15
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`

`

`CONTENTS
`
`
`
`xvii
`
`
`
`
`
`
`PHOTORESIST MATERIAL PARAMETERS,409
`
`Resolution
`
`Sensitivity
`
`
`
`
`Etch Resistance and Thermal Stability
`
`Adhesion
`
`
`
`
`Solids Content and Viscosity,
`
`
`
`Particulates and Metals Content
`
`
`
`
`
`Flash Point and TLV Rating
`
`
`
`
`
`Process Latitude, Consistency, and Shelf-Life
`
`
`
`
`OPTICAL PHOTORESIST MATERIAL TYPES, 418
`
`
`
`Postive Optical Photoresists
`
`
`
`Negative Optical Photoresists
`
`
`
`
`Image Reversal of Positive Resist
`
`
`
`Multilayer Resist Processes
`
`
`Contrast Enhancement Layers
`
`
`Inorganic Resists
`
`
`Dry-Developable Resists
`
`
`
`Mid-UV and Deep-UV Resists
`
`
`Photosensitive Polyimides
`
`
`
`PHOTORESIST PROCESSING, 429
`
`
`
`
`
`Resist Processing: Dehydration Baking and Priming
`
`
`
`Resist Processing: Coating
`Resist Processing: Soft-Bake
`
`
`
`
`
`Resist Processing: Exposure
`
`
`
`Resist Processing: Development
`Resist Processing: After Develop Inspection and Linewidth Measurement
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Resist Processing: Post Bake and Deep UV Hardening
`
`
`
`PHOTORESIST SELECTION,454
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`‘
`
`
`
`
`
`
`
`- 459
`
`
`
`
`
`13. LITHOGRAPHYII:
`OPTICAL ALIGNERS AND PHOTOMASKS
`
`
`
`OPTICS OF MICROLITHOGRAPHY, 460
`
`
`
`
`
`
`
`
`
`Diffraction, Coherence, Numerical Aperture, and Resolution
`
`
`
`Modulation Transfer Function
`
`
`
`
`OPTICAL METHODS OF TRANSFERRING PATTERNS
`
`
`
`
`
`
`TO A WAFER: OPTICAL ALIGNERS, 468
`Light Sources and Light Meters for Optical Aligners
`
`
`
`
`
`
`
`
`
`Contact Printing
`
`
`Proximity Printing
`
`
`
`
`
`Projection Printing: Scanning Aligners and Steppers
`
`
`
`PATTERN REGISTRATION,473
`
`
`Automatic Alignment
`MASK AND RETICLE FABRICATION,476 |
`
`
`
`
`
`
`
`
`
`Glass Quality and Preparation
`
`
`
`Glass Coating (Chrome)
`
`
`
`
`
`
`
`
`
`Page 9 of 15
`
`Page 9 of 15
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`

`

`xviii
`
`
`
`CONTENTS
`
`
`
`
`
`
`
`
`Mask Imaging (Resist Application and Processing)
`
`
`
`
`
`Pattern Generation (Optical and Electron-Beam)
`
`
`
`
`
`
`
`Mask and Reticle Defects and their Repair
`
`Pellicles
`
`
`
`
`
`
`
`
`Critical Dimension and Registration Inspection of Masks and Reticles
`
`
`
`
`
`
`
`14, ADVANCED LITHOGRAPHY
`
`
`
`493
`
`
`
`
`
`
`
`- ELECTRON BEAM LITHOGRAPHY,493
`
`
`
`Electron Beam Systems
`
`
`Writing Strategies
`
`
`
`Electron Scattering in Resists
`
`
`Resist Development
`
`
`Proximity Effects
`
`
`- X-RAY LITHOGRAPHY,504
`
`
`X-Ray Sources
`
`
`X-Ray Masks
`
`
`X-Ray Resists
`
`
`
`- ION BEAM LITHOGRAPHY,510
`
`
`
`
`
`
`
`
`
`
`
`
`
`15. WET PROCESSING: CLEANING; ETCHING; LIFT-OFF 514
`
`
`
`
`
`- WAFER CLEANING, 516
`
`
`
`Sources of Contamination
`
`
`
`
`Wafer Cleaning Procedures
`
`
`
`
`_ - TERMINOLOGY OF ETCHING, 520
`
`
`
`
`
`Bias, Tolerance, Etch Rate, and Anisotropy
`
`_ Selectivity, Overetch, and Feature-size Control
`
`
`
`
`
`
`
`
`Determining Required Selectivity with Respect to Substrate, Shs
`
`
`
`
`
`
`
`
`
`
`Determining Required Selectivity with Respect to Mask, Stim
`
`
`
`
`Loading Effects
`
`
`
`- WET ETCHING TECHNOLOGY,529
`
`
`
`Wet Etching Silicon
`
`
`
`Wet Etching Silicon Dioxide
`
`
`
`
`Wet Etching Silicon Nitride
`
`
`
`Wet Etching Aluminum
`
`
`
`
`- LIFT-OFF TECHNOLOGY FOR PATTERNING,535
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`16. DRY ETCHING FOR VLSI
`
`
`
`—
`
`§39
`
`
`
`
`
`
`
`
`- BASIC PHYSICS AND CHEMISTRY OF PLASMAETCHING,542
`
`
`
`
`
`
`
`The Reactive Gas Glow Discharge
`
`
`
`
`Electrical Aspects of Glow Discharges
`
`
`
`
`
`Page 10 of 15
`
`Page 10 of 15
`
`

`

`CONTENTS
`
`
`
`xix
`
`
`
`
`
`
`
`
`Heterogeneous (Surface) Reaction Considerations
`
`
`
`
`
`
`_
`Parameter Control in Plasma Processes
`
`
`ETCHING SILICON AND SiO, in CF, 105 H,, 547
`
`
`
`
`
`
`
`
`
`
`Fluorine-to-Carbon Ratio Model
`
`ANISOTROPIC ETCHING AND CONTROL OF EDGE PROFILE,552
`
`
`
`
`
`
`
`
`DRY ETCHING VARIOUS TYPES OF THIN FILMS, 555
`
`
`
`
`
`
`
`
`
`Silicon Dioxide (SiO05)
`
`
`Silicon Nitride
`
`Polysilicon
`
`
`
`
`Refractory Metal Silicides and Polycides
`
`
`
`
`Aluminum and Aluminum Alloys
`
`
`Organic Films
`
`
`- PROCESS MONITORING AND END POINT DETECTION,565
`
`
`
`
`
`
`
`
`
`Laser Reflectometry and Laser Reflectance
`
`
`
`Optical Emission Spectroscopy
`
`
`Mass Spectroscopy
`
`
`
`DRY ETCHING EQUIPMENT CONFIGURATIONS,568
`
`
`
`
`
`
`Commercial Dry Etch System Configurations
`
`
`
`
`
`
`
`Comparison of Single Wafer and Batch Dry Etchers
`
`
`
`
`
`PROCESSING ISSUES RELATED TO DRY ETCHING, 574
`
`
`
`
`
`
`Plasma Etching Safety Considerations
`
`
`
`Uniformity and Reproducibility Considerations
`
`
`
`
`
`
`Contamination and Damage of Etched Surfaces
`
`
`
`
`
`Process Gases for Dry Etching
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`17. MATERIAL CHARACTERIZATION TECHNIQUES
`
`
`
`FOR VLSI FABRICATION
`
`
`
`586
`
`
`
`
`
`
`
`
`
`
`
`
`- WHAT ARE WE TRYING TO DETECT, AND HOW IS IT DONE?, 586
`
`
`
`
`
`
`
`
`
`
`
`
`Energy Regimes and Energy Levels in Material Characterization
`
`
`
`
`
`Definitions of Material Characterization Terminology
`
`
`
`
`Vacuum Requirements of Compositional Analysis
`
`
`
`
`
`MICROSCOPY FOR VLSI MORPHOLOGY,589
`
`
`
`Optical Microscopes
`
`
`
`Scanning Electron Microscopes (SEM)
`
`
`
`Transmission Electron Microscopy
`
`ELECTRON /X-RAY COMPOSITIONAL ANALYSIS TECHNIQUES, 599
`
`
`
`
`
`
`Auger Emission Spectroscopy
`
`
`
`X-Ray Emission Spectrocopy
`
`
`
`
`X-Ray Photoelectron Spectroscopy (XPS, ESCA)
`
`
`X-Ray Fluorescence
`
`
`
`
`- ION BEAM EXCITED COMPOSITIONAL ANALYSIS, 606
`
`
`
`
`
`Secondary-Ion Mass Spectroscopy (SIMS)
`
`
`
`
`
`Laser Ion Mass Spectroscopy (LIMS)
`
`
`
`
`Rutherford Backscattering Spectroscopy (RBS)
`
`
`
`
`
`
`
`
`
`
`
`!
`
`Page 11 of 15
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`Page 11 of 15
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`

`

`XX
`
`
`CONTENTS
`
`
`
`
`
`
`- CRYSTALLOGRAPHIC STRUCTURE ANALYSIS, 610
`
`
`X-Ray Diffraction
`
`
`
`X-Ray Lang Topography
`
`
`
`
`Neutron Activation Analysis (NAA)
`
`
`
`
`
`
`- SUMMARYOF CHARACTERIZATION TECHNIQUE CAPABILITIES, 612
`
`
`
`
`
`
`
`
`- SUGGESTIONS FOR HOW TO ACCOMPLISH AN EFFECTIVE ANALYSIS, 614
`
`
`
`
`
`
`
`
`
`
`
`18. STRUCTURED APPROACH to DESIGN of EXPERIMENTS
`
`
`
`FOR PROCESS OPTIMIZATION
`
`
`
`618
`
`
`
`
`
`
`
`- FUNDAMENTALSOF STATISTICS, 619
`
`
`
`
`
`
`Samples, Populations, Means, Variance, and Standard Deviation
`
`
`
`
`
`
`Pooled Variance and Degrees of Freedom
`
`
`Normal Distributions ~
`
`
`
`
`
`
`Distributions of Averages, t-Distributions, and Confidence Levels
`
`
`
`
`
`
`- DESIGN OF EXPERIMENTS: BASIC DEFINITIONS,625
`
`
`
`
`- CHARACTERISTICS OF FACTORIAL EXPERIMENTS, 627
`
`
`
`
`
`- STRATEGY OF DESIGNING EXPERIMENTS,632
`
`
`
`
`
`
`- DESIGNING and ANALYZING 2-LEVEL FULL-FACTORIAL EXPERIMENTS,634
`
`
`
`
`
`
`Method for Designing 2-Level Full-Factorial Experiments
`
`
`
`
`
`Analysis of the Measured Data
`
`
`- SCREENING EXPERIMENTS,641
`
`
`
`
`- RESPONSE SURFACES, 643
`
`
`
`
`
`
`
`
`
`
`
`
`
`.
`
`647
`648
`649
`
`
`
`
`
`651
`
`
`
`APPENDICES
`
`
`
`
`
`1. MATERIAL PROPERTIESOF SILICONat 300°K
`
`
`
`
`2. PHYSICAL CONSTANTS
`
`
`
`3. ARRHENIUS RELATIONSHIP
`
`
`
`—_
`
`
`
`INDEX
`
`
`
`Page 12 of 15
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`Page 12 of 15
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`

`

`REFRACTORY METALS AND THEIR SILICIDES IN VLSI FABRICATION
`
`
`
`
`
`
`
`
`397
`
`
`
`
`PROCESS INTERACTION
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`In an MOSprocess the polycide is normally formed after the gate oxide step. Since the
`
`
`
`
`
`
`
`
`
`
`
`
`
`polycide approach to reducing interconnectresistance represents an "add on" process to the
`
`
`
`
`
`
`
`
`
`
`
`
`
`conventional Si gate process, compatibility with the original process must be maintained.
`In
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`this section, we discuss some of the propertiesof silicides that can impactthe original process.
`
`
`
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`
`
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`
`
`First there are some steps that must be added and others that must be modified, in order to
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`form, pattern, and oxidize the silicide.
`In addition, the polycide must then remain compatible
`
`
`
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`
`
`
`
`
`
`
`
`
`
`
`
`with the rest of the steps in the process sequence, including: a) the source-drain ion-implant and
`
`
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`
`
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`
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`
`
`
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`
`
`
`anneal steps; b) the flow /reflow cycles involving the CVD dielectric (e.g. PSG or BPSG); and c)
`
`
`
`
`
`
`
`
`
`
`
`
`
`the Al alloying, passivation, bonding, and package sealing steps. The subjects ofsilicide
`
`
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`
`
`
`
`
`
`formation and oxidation were covered earlier. The remaining topics will be discussed here,
`
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`
`
`The patterning of the polycide can involve several techniques, depending on how the
`
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`
`
`structure is formed. If the underlying poly-Si is patternedfirst (e.g. by dry-etching), pure metal
`
`
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`
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`
`
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`
`
`is deposited on top, and thesilicide is formed by direct metallurgical reaction. The metal thatis
`
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`
`
`not deposited on poly-Si remains unreacted, and can be subsequently removed bya selective etch.
`
`
`
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`
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`
`
`This is one method for the formation and patterning of a TiSi, /poly-Si structure. If the silicide
`
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`
`
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`
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`
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`
`
`
`is formed on an unpatterned poly-Silayer, the polycide is patterned by dry-etching. The subject
`
`
`
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`
`
`
`
`
`
`
`
`of dry-etching polycides is discussed in Chap. 16 and in Refs. 3 and 25.
`
`
`
`
`
`
`
`
`
`
`
`The highest temperature thermal steps associated with post-polycide formation can occur
`
`
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`
`
`during the annealing /drive-in of the source-drain implantations (600-900°C, depending on the
`
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`
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`implant species and conditions), oxidation of the polycide, and flow /reflow ofthe deposited glass
`
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`layer (up to 1000°C). The polycide must not exhibit any undesirable properties during these
`
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`
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`thermal steps. That is, the following characteristics must be demonstrated: a) the silicide must
`
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`
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`remain chemically stable; b) the poly-Si /silicide interface must not move, and the poly-Si
`
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`
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`thickness remain unchanged (except during oxidation); c) the silicide should not react with the
`deposited glass; d) the stress ofthesilicide film should not increase to unacceptably high levels;
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`and ¢) the resistivity of the silicide should not degrade. Reports indicate that polycides of
`MoSi,, WSi,, TaSi», and TiSi, are capable of satisfying the above process compatibility
`
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`requirements. Note that the oxidation of the silicide proceeds by the diffusion of the silicon
`from the underlying poly-Si. Therefore, sufficient poly-Si must remain underthesilicide (after
`
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`Silicide formation), to supply Si for SiO,, andstill leave an adequate poly-Si underlayer.
`
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`At the final steps of VLSI manufacture, one or more layers of aluminum are deposited and
`
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`
`
`Patterned, and the chipis passivated, bonded, and packaged. The metal annealing, chip bonding,
`4nd sealing temperatures are in the 350-500°C range. Since Al makes contact with thesilicide
`
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`layer,
`it is important that the Al /silicide
`interface remain stable at these temperatures.
`
`
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`
`
`Fortunately, the lowest temperatures at which Al and the refractory metalsilicides interact, are
`
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`
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`above the typical alloy and assembly procedure temperatures [e.g. WSi, (~500°C), TaSi,
`
`
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`
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`(SS0°c), MoSi, (S00°C), and TiSi,
`(450-600°C)]. Note that at such temperatures,
`
`
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`
`
`‘ntermetallics of Al and the metal are formed, as well as free Si, that precipitates into the A176,
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`Such interactions affect the electrical characteristics and the stability of silicide /Si contacts. A
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`In diffusion barrier (e.g. W) has been suggested to preventthis reaction, if necessary.
`
`
`
`
`SELF-ALIGNED SILICIDE (SALICIDE) TECHNOLOGY
`
`
`
`
`
`
`Asthe contact dimensions of VLSIshrink,the contact resistance increases, and in addition,
`
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`the sheet resistivity of the shallow-junctions of the source /drain regions also increases, To
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`L Page 13 of 15
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`Page 13 of 15
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`398
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`SILICON PROCESSING FOR THE VLSI ERA
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`reducethese resistance values, while simultaneously reducing the interconnect resistance Ofthe
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`polysilicon lines, self-alignedsiligide (or salicide) technology can be used2’, That is, Metal
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`is deposited over an MOSstructure, and reacted with the exposed Si areas of the source and draj
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`as well as the exposed poly-Si areas on the gate, to form a silicide. Note that side-wall oxidation
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`structures along the gate (known as oxide spacers) are used to preventthe gate and source /drain
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`areas from being electrically connected by avoiding silicide formation onthis oxide.) Followin
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`the silicide formation, a selective etch removes the unreacted metal without attacking thesilicide
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`Figure 13 shows the key processing steps and final salicide structure2®, A much lower
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`contact resistance betweensilicide and Si is achieved than with a conventional contactstructure
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`because the areaofthis interface is much larger than the area of a conventional metal-Si conta;
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`structure.
`(Thesilicide /Al contact resistance is much lower than metal /Si contact resistance),
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`The salicide structure is also formed after the source-drain implant and anneal steps, and thus
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`must only experience high-temperatures during oxidation and flow /reflow steps.
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`The most widely usedsilicide for the salicide process is TiSi,, although PtSi and MoSj
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`have also been employed?”:29,
`TiSi, is attractive for this application becauseit exhibits
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`the lowest resistivity of the refractory metalsilicides, and since it can reduce native layers,it is
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`the only knownrefractory metal that can reliably form a silicide on both poly and single-crystal
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`Si by thermal reaction. However, it also has the following drawbacks: a) the reactivity of Tj
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`with SiO, can cause unwanted reaction of Ti and the oxide spacers during the silicide formation
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`process; b) TiSi, is less stable than WSi, or MoSi,; and c) Ti films have a high propensity to
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`oxidize, and hencethesilicide reaction must be conducted in ambients thatare free of oxygen,
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`In the salicide structure, the silicide is formed both in the diffusion areas and on the poly-Sj
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`gate. The oxide spacers separate these two regions by only about 2000-3000A. Thus, any
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`lateral formationofsilicide can easily bridge this separation and cause the gate to become shorted
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`to the source /drain (and is referred to as bridging).
`It has been observedthatif TiSi, is formed
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`by conventional furnace annealing (i.e. anneal times of ~30 min) in an inert gas (e.g. Ar)
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`atmosphere, such lateral TiSi, formation rapidly occurs. By annealing in an ambientof N., the
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`Ti absorbs a significant amountof N,(e.g. >20at%) and at the sametime reacts with N. and
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`formsa nitride phase at the Ti surface. Once Tiis "stuffed with" (or reacted with) nitrogen, the
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`POLY" $i
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`a) FORM STANDARD DEVICE UP TO DIFFUSION
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`d) SELECTIVELY REMOVE UNREACTED METAL
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`POLY Si
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`— Al BASED
`ME TALLUHGY
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`CONTACT BARRIER
` ———
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`b) FORM SIDE WALL OXIDE SPACERS
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`METAL.
`SILICIDE —
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`SiO.
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`= =A)
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`e) FINAL STRUCTURE AFTEH Glt.ASS PASSIVATION,
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`REFLOW,GONTACT OPENNING ANO METALLIZATION
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`¢) DEPOSIT METAL,REACT 10 FORM SILICIDE
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`Fig. 13
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`Salicide process flow and final structure. 28. (© 1985 IEEE.
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`Page 14 of 15
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`Page 14 of 15
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`

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`REFRACTORY METALS AND THEIR SILICIDES IN VLSI FABRICATION
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`lateral silicide reaction is essentially suppressed. Thus, annealing in pure N, (i.e. oxygen and
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`moisture content of less than 10 ppma), or pure forming gas (90% N,+ 10% H,), results in
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`TiSi, formation without bridging.
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`During the TiSi, formation, the Ti and the spacer SiO, can react. Any residues of this
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`reaction can degrade device performance by compromising the oxide integrity, or by producing
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`bridging. To avoid sucheffects, it is recommended that the TiSi, formation temperature be held
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`to <700°C, and that a minimum field oxide thickness of 1000A beutilized.
`In practice, a
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`two-step formation process has been suggested. During thefirst step, the temperature is kept at
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`~650°C. After selectively etching and removing the unreacted Ti in a room temperature mixture
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`of DI H,0, H,0,, and NH,OH (5:1:1), a second temperature step of ~800°C is used to lower
`the TiSi, sheet resistance, andto stabilize the TiSi, phase*?,
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`Rapid thermal processing (RTP) has also been used to effect the silicide formation. Wang
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`and Lien report that TiSi, is formed by RTP at 600-800°C in Ar (reaction time depends onthe
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`temperature selected), After selectively removing the unreacted Ti, a stabilization anneal of
`1000°C for30 sec in Ar is conducted to reduce the TiSi, resistance?!
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`Once the TiSi,
`is formed and stabilized,
`it can be subjected to somewhat higher
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`temperatures. Because of instability of the TiSi, above ~900°C, however, it is recommended
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`that all processing steps after silicide formation be kept below 900°c?8
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`REFRACTORY METAL INTERCONNECTS FOR VLSI
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`As features shrink below 1 um, and chip sizes increase beyond 1.0 om’, polycide sheet
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`resistances of 1-5 Q /sq can still become the limiting performance factor for VLSIcircuits. ai
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`these cases it is necessary to use even lowerresistance interconnects (such as metal films)>2
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`Although aluminum metallization has been widely used for VLSI interconnects, it suffers from
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`its inability to withstand high temperatures processing, which precludesits use in self-aligned
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`MOSprocessing. This is not the ca