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`United States Patent
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`Konakaet al.
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`119
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`[11]
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`[45]
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`Patent Number:
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`Date of Patent:
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`4,651,411
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`Mar, 24, 1987
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`[54] METHOD OF MANUFACTURING A MOS
`DEVICE WHEREIN AN INSULATING FILM
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`IS DEPOSITED IN A FIELD REGION
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`Inventors: MasamiKonaka,Kawasaki; Naoynd
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`igyo;
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`Yokohama, all of Japan
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`Tokyo Shibaura Denki Kabushiki
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`Kaisha, Kawasaki, Japan
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`[21] Appl. No.: 744,899
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`[22] Filed:
`Jun, 17, 1985
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`58-73163
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`[75]
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`[73] Assignee:
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`FOREIGN PATENT DOCUMENTS
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`5/1983 Japan .
`181062 1071986 Japanerste
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`OTHER PUBLICATIONS
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`“A New Buried-Oxide Field Isolation for VLSI De-
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`vices”, K. Kurosawaet al; Jun. 22-24, 1981, 39th An-
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`nual Device Research Conference, Santa Barbara, CA.
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`“A New Bird’s-Beak Free Field Isolation Technology
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`for VLSI Devices” Kurosawa et al; Dec. 7-9, 1981,
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`IEDM Technical Digest, International Electron De-
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`vices Meeting, Washington, D.C.
`Related U.S. Application Data
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`[63]
`Continuation of Ser. No. 435,663, Oct. 21, 1982.
`Primary ExaminerBrian E. Hearn
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`Callahan
`Assistant Examiner—John
`:
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`gs
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`Attorney, Agent, or Firm—Oblon,Fisher, Spivak,
`Foreign Application Priority Data
`[30]
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`Oct. 27, 1981 [JP]. Japan seeseesssssssssssssssssssessese 56-171784|McClelland & Maier
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`[ST] It, Chet vecessseseenees HO1L 21/76; HOLL 29/78
`ABSTRACT
`[57]
`[52] US. CL. oeeeeseesssetsenscssstssaies 70/8NG A method of manufacturing a MOSdevice wherein a
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`[58] Field of Search
`29/571, 576 W: 357/49
`semiconductorsubstrate is selectively etched to form a
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`357/50 54.23CS: 156/643: 148/DIG. 50.
`groove in a field region and an element formation Te-
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`gion surrounded by the groove such that an angle 0 is
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`formed between a wall of the groove anda first imagi-
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`nary extension of a top surface of the element formation
`References Cited
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`region, the angle @ satisfying the relation, 70°=@=90°.
`U.S. PATENT DOCUMENTS
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`Then,a field insulating film is deposited in the groove,
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`aenee +1076 nonman sereseneacareanereannens mero
`and a MOStransistor is formed in the element forma-
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`3979,763 "357/23 cs.__tion region. The elementformation region has source,9/1976 Brand...
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`4,001,465. 1/1977 Graul et al. veesmnnsennnnse 357/50|drain and channel regions of a field effect transistor
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`4,013,484 3/1977 Bolekyetal.
`357/23 CS
`therein and a gate electrode formed on a gate insulating
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`5/1977 Richman .esscsssssssssssssossssessees 357/50
`4,023,195
`film on the channel region. The gate electrode extends
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`4,044,452
`8/1977 Abbos-etal......
`.. 357/23 CS_—_
`onto thesurface portionofthe field insulating film. The
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`4,104,086
`8/1978 Bondur etal. ...
`wee 29/576 W
`thickness ofan upper portion ofthe field insulating film
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`4,307,180 12/1981 Pogge ........s0
`«. 29/576 W
`above a first imaginary extension of an interface be-
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`treo a1983 Cer
`59le\
`tween the gate insulating film and the gate electrodeis
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`4,407,851 10/1983 Kurosawaetal.
`formed smaller than that of a lower portion of the field
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`4,462,847 7/1984 Thompsonet al.ee 29/576 W_insulating film below thefirst imaginary extension.
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`3/1985 Godejahn,Jr.......
`4,506,437
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`4,541,167
`9/1985 Havemannetal. ............. 29/576 W
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`[56]
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`6 Claims, 12 Drawing Figures
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`VPsoa~Pf
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`0
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`it
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`.
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`~
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`e
`e
`TSMCExhibit 1032
`TSMCv. IP Bridge
`IPR2016-01246
`
`Page 1 of 9
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`TSMC Exhibit 1032
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

`U.S. Patent Mar.24,1987
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`Sheet 1 of5
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`4,651,411
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`FIG.
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`(PRIOR ART)
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`THRESHOLDVOLTAGE VT
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`EFFECTIVE CHANNEL WIDTH
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`U.S. Patent Mar. 24, 1987
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`Sheet20f5
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`4,651,411
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`FIG 3
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`(PRIOR ART )
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`KXSGSARSNS
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`4
`ZA
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`EFFECTIVE CHANNEL WIDTH
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`weff
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`Lu
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`aa5> O
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`t2
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`U.S. Patent Mar.24,1987
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`4,651,411
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`FIG 6
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`THICKNESS RATIO ti/t2
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`U.S. Patent Mar. 24,1987
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`Sheet 4 of5
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`U.S. Patent Mar.24,1987
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`1
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`METHOD OF MANUFACTURING A MOS DEVICE
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`WHEREIN AN INSULATING FILM IS DEPOSITED
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`IN A FIELD REGION
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`SUMMARYOF THE INVENTION
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`It is an object of the present invention to provide a
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`method of manufacturing a MOS device having an
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`insulator isolation structure wherein dependence of the
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`threshold voltage on the effective channel width is
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`This application is a continuation of application Ser.
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`slight, while a substrate surface is kept as smooth as
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`No. 435,663, filed Oct. 21, 1982.
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`possible.
`BACKGROUNDOF THE INVENTION
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`In order to achieve the above object of the present
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`invention, there is provided a method of manufacturing
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`Thepresent invention relates to a method of manu-
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`a MOSdevice, comprising: selectively etching a semi-
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`facturing a MOS device having a structure where an
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`conductor substrate to form a groove in a field region
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`insulating film is deposited in a field region.
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`and an element formation region surrounded by the
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`A semiconductor device such as a memory device
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`groove such that an angle @ is formed between a wall of
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`using a MOSFETshownin FIG.1 is known which has
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`the groove andafirst imaginary extension of a top
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`a coplanar (or LOCOS)structure to increase packing
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`surface of the element formation region, with the angle
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`density and improve reliability. The semiconductor
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`6 satisfying the relation, 70°=@=90°. Then, a field
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`device comprises a p-type silicon substrate 1, a field
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`insulating film is deposited in the groove. The element
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`oxide film 2 selectively formedin the field region, a gate
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`formation region has source, drain and channel regions —
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`oxide film 3 formed on an element formation region
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`of a field effect transistor therein and a gate electrode
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`aroundthefield oxide film 2, a gate electrode 4 formed
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`formed on a gate insulating film on the channelregion.
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`on the gate oxidefilm 3, and an ion-doped layer 5 which
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`the field insulating film. The thickness of an upper por-
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`tion of the field insulating film above a first imaginary
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`coplanar structure has advantagesin that indentation of
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`the element surface is small since part of the field oxide
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`film and the gate electrode is smaller than that of a
`film 2 is formed in the silicon substrate 1, and in that
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`lowerportion ofthe field insulating film below thefirst
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`excellent step coverage is obtained in the aluminum
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`imaginary extension.
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`elements,
`wiring which connects
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`According to the above method, the threshold volt-
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`age drop which occurs due to the narrow channeleffect
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`However, lateral extrusions B of this structure which
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`MOSdevice produced according to the present inven-
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`shown in FIG.1, adversely affecting microminiaturiza-
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`tion does not significantly depend on the effective chan-
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`nel. width.
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`The narrowerthe effective channel width Weff of the
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`Furthermore, the method of the invention may in-
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`MOSFETis, the greater the adverse effect. The actual
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`thickness of the gate oxide film 3 becomes greater than
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`structure.If the permittivity of the upperinsulating film
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`portion is smaller than that of the lowerinsulating film
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`portion, the extent of projection of the insulating film
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`the gate oxide film becomes substantially the same as
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`can be decreased. Asa result, excellent step coverage of
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`path is open. As shownin FIG.2, the threshold voltage
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`VT of the MOSFETis increased when the effective
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`channel width Weff is decreased, thus resulting in the
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`angle @ formed by the wall of the groove and the imagi-
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`nary extension of the top surface of the element forma-
`FIG.3 is a schematic sectional view of a MOSFET
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`tion region may be determined to satisfy the relation
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`having a BOX (Buried-Oxide Isolation) structure which
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`77° 3090" to decrease the height of the projection. of
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`solves the problem ofthe bird’s beak encountered in the
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`the insulating film. When theinsulating film is formed of
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`coplanar structure. The MOSFET comprises a silicon
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`silicon nitride, the angle @ may be determined tosatisfy
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`substrate 1, a silicon oxide film 6 deposited by low-tem-
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`perature epitaxial growth in a groove with vertical
`BRIEF DESCRIPTION OF THE DRAWINGS
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`walls, a gate oxide film 3 formed on the element forma-
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`tion region surroundedbythe silicon oxide film 6, a gate
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`Other objects and advantages will be apparent from
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`electrode 4 formed on the gate oxide film 3, and an
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`the following description taken in conjunction with the
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`ion-doped layer 5 which functions as a channel stopper
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`accompanying drawings, in which:
`and whichis formedin the silicon substrate beneath the
`FIG.1 is a sectional view of a conventional MOS
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`silicon oxide film 6. Since the silicon oxide film 6 is
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`device having a coplanar structure;
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`formed in this MOSFET without involving high-tem-
`FIG. 2 is a graph showing the threshold voltage of
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`perature thermal oxidation, the bird’s beaks are not
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`formed. Therefore, the above structure has an advan-
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`FIG. 3 is a sectional view of a conventional MOS
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`tage in that a MOSFETis formed which has a desired
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`effective channel width. However, we found by experi-
`device having a BOX structure;
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`ments that when the gate electrode 4 extends onto the
`FIG. 4 is a graph showing the threshold voltage of
`the device shownin FIG.3 as a function of the effective
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`surface portion of the silicon oxide film 6, the threshold
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`voltage VT of the MOSFETdecreases with a decrease
`channel width thereof;
`FIG.5 is a sectional view of a MOS semiconductor
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`in the effective channel width Weff, as shownin FIG.4.
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`device according to a first embodiment of the present
`Generally, the electrical characteristics of the MOS-
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`invention;
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`FET must not depend on the effective channel width.
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`Page 7 of 9
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`15
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`3
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`FIG.6 is a graph showingthe variation in the thresh-
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`etched so as to define the thickness of the upward pro-
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`old voltage as a function of the thickness ratio t1/t2,
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`jection of the silicon oxide film 17 which must be
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`that is, as a function of an extent of projection of the
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`smaller than that of the embedded portion thereof. As
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`insulating film deposited in the groove formed in the
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`shownin FIG. 7C,a gate oxidefilm 13 is formed on the
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`field region;
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`element formation region 11. Furthermore, a polysili-
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`FIGS. 7A to 7D are sectional views for explaining
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`con gate electrode 14 is formed on the gate oxide film 13
`and on thesilicon oxide film 17.
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`the steps of manufacturing a MOS device according to
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`the present invention;
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`The structure of FIG. 7B can be provided without
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`FIG.8 is a sectional view of a MOSdevice according
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`etching the silicon substrate 10. This may be achieved
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`to a second embodiment of the present invention; and
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`by obtaining the structure of FIG. 7A without remov-
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`FIG.9 is a sectional view of a MOSdevice according
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`ing the etching mask (e.g. Al film, Si3N4 film, photore-
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`to a third embodimentof the present invention.
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`sist film, etc.) used in cutting the groove 12 and then by
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`removing the etching mask thereafter.
`DETAILED DESCRIPTION OF THE
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`A MOSdevice according to a second embodimentof
`PREFERRED EMBODIMENTS
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`the present invention will be described with reference
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`A MOSdevice accordingto a first embodiment of the
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`to FIG. 8. In this embodiment, an insulating film of
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`present invention will be described with reference to
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`silicon nitride is deposited in the groove 12. An insulat-
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`FIG. 5. A groove 12 which has a substantially vertical
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`ing films 17a and 17b having a two-layerstructure are
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`wall is formed around an element formation region 11 in
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`formed in a groove 12 ofa silicon substrate 10, The
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`20
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`MOSdevice of this embodiment is the same as that of
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`which source, drain and channel regions of the MOS-
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`FET are formed. An insulating film such asasilicon
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`the first embodiment, except that an upper layer 17ais
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`oxide film 17 is deposited in the groove 12 by low-tem-
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`formedofsilicon oxide having a relative permittivity of
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`perature epitaxial growth. An ion-doped layer 15 as a
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`3.9, and that a lower layer 17b is formed ofsilicon ni-
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`channel stopper is formed in the surface layer portion of
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`tride having a relative permittivity of about 7. The
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`the semiconductor substrate 10 beneath the silicon
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`relative permittivity of the upper layer 17a is smaller
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`oxide film 17. A gate oxide film 13 of SiO2 is formed on
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`than that of the lower layer 176. As a gate oxidefilm 13,
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`the surface of the element formation region 11. A
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`use is made ofa 1,000 A thick siliconnitride film which
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`. polysilicon gate electrode 14 is formed on the gate oxide
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`is formed by a direct nitrogenization. The samerefer-
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`film 13. The gate electrode 14 extends onto the surface
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`ence numerals used in FIG. 5 denote the sameparts in
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`- portion of the silicon oxide film 17. The silicon oxide
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`FIG.8, and a detailed description thereof will be omit-
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`film 17 projects by a thickness tl above an imaginary
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`ted. In the above structure, the thickness ratio t1/t2 for
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`extension ofthe interface between the gate oxidefilm 13
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`substantially eliminating the variation AVT in the
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`and the gate electrode 14. Thesilicon oxide film 17 is
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`threshold voltage can be smaller than if in the first em-
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`embedded to a thickness t2 under the imaginary exten-
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`bodimentthe film 17 is formed ofsilicon nitride alone,
`sion.
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`because the relative permittivity is smaller than in such
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`FIG.6 is a graph for explaining the variation AVT in
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`first embodiment. As a result, the thickness t1 can be
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`the threshold voltage as a function of the ratio t1/t2.
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`decreased, so that excellent step coverage of the wiring
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`The overall thickness (t1+12) of the silicon oxide film
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`layer can be provided anda highly reliable semiconduc-
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`17 is kept constant. Note that the variation AVT in the
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`tor device can be obtained. Morespecifically, the thick-
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`threshold voltage indicates a difference between the
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`ness t1 can be reduced to half. The structure of FIG. 8
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`threshold voltage of a transistor which has a sufficiently
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`may be provided in the following steps.
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`wide effective channel width Weff and the threshold
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`First, a silicon nitride film is deposited in place of the
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`voltage of a transistor which has an effective channel
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`silicon oxide film 17 shown in FIG. 7A. The surface
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`width Weff of 0.2 u. The above data is obtained by
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`portion ofthe silicon nitride film is then etched. On the
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`entire surface of the structure thus obtained there is
`computer simulation under the following conditions:
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`the impurity concentration Nsub ofthesilicon substrate
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`deposited a silicon oxide film. A photoresist film is
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`10 is 2X 1015 cm—3; the thickness TOX ofthe gate oxide
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`coated on the silicon oxide film. The photoresist film
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`film 13 is 1,000 A; the total thickness tl-+t2 ofthesili-
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`has a flat surface. Both the photoresist film and the
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`con oxide film 17 of the field region is 5,000 A; and the
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`silicon oxide film are etched at substantially the same
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`relative permittivities es of the gate oxide film 13 and
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`rate until the upper surface of the substrate is exposed.
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`the silicon oxide film 17 are both 3.9. If a tolerance for
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`The surface portion of the substrate is then etched. The
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`the variation AVT in the threshold voltage is +20 mV
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`surface of the substrate is nitrided, thus forming a gate
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`in the LSI design, the thickness ratio t1/t2 is preferably
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`insulating film 13. Alternatively, the surface of the sub-
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`in the range of 0.65St1/t2<1. Within this range, the
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`strate may be oxidized, thus forming a gate insulating
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`film 13 ofsilicon oxide.
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`dependency of the threshold voltage of the MOSFET
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`on the effective channel width Weff is eliminated.
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`A MOSdevice according to a third embodiment of
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`A method for manufacturing a MOSdevice accord-
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`the present invention will be described with reference
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`ing to the present invention will be described with refer-
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`to FIG. 9. The MOS device of this embodimentis the
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`ence to FIGS. 7A to 7D. As shown in FIG.7A,a silicon
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`sameas that in FIG. 5, except that the wall of a groove
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`substrate 10 is selectively etched to form a groove 12 in
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`12 ofa silicon substrate 10 is inclined to form an angle
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`the field region. The groovehas a substantially vertical
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`@ smaller than 90° with respect to the imaginary exten-
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`wail. An impurity is ion-implanted in the bottom ofthe
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`sion of the top surface of an element formation region
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`groove 12 to form a channel stopper 15. A silicon oxide
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`11. The same reference numerals used in FIG. 5 denote
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`film 17 is deposited by chemical vapor deposition in the
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`the same parts in FIG. 9, and a detailed description
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`groove 12. The abovesteps are the sameas thosein the
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`thereof is omitted. When the angle @ is set to 80°, the
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`conventional BOX structure method.
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`thickness ratio t1/t2 for substantially eliminating the
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`As shownin FIG.7B, an element formation region 11
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`variation AVT in the threshold voltage can be smaller
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`surrounded by the silicon oxide film 17 is selectively
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`than when the angle @ is set to 90°. The thickness t1 of
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`Page 8 of 9
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`

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`6
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`imaginary extension; and wherein said semiconduc-
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`tor substrate is formed ofsilicon, said field insulat-
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`ing film is formed ofsilicon oxide,and a ratio of the
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`thickness of said upper portion ofsaid field insulat-
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`ing film abovethefirst imaginary extension to that
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`of said lower portion of said field insulating film
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`below thefirst imaginary extension is greater than
`0.65 and lower than 1.
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`2. The method according to claim 1, wherein said
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`field insulating film is formed ofsilicon oxide, and the
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`angle 6 satisfies the relation:
`TT 50290".
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`3. The method according to claim 1, wherein said
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`field insulating film is formed of silicon nitride.
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`4. The method according to claim 1, comprising:
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`forming a channel stopper in a surface layer of said
`semiconductor substrate beneath of said field insu-
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`lating film.
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`5. The method according to claim 1, comprising:
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`forming said field insulating film with a two-layer
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`structure consisting of two insulating material lay-
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`ers having different relative permittivities, a per-
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`mittivity of an upper insulating material
`layer
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`abovethe first imaginary extension being smaller
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`than that of a lowerinsulating material layer below
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`the first imaginary extension.
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`6. The method according to claim 5, comprising:
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`forming said upperinsulating material layer ofsilicon
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`oxide; and
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`forming said lowerinsulating material layerofsilicon
`nitride.
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`*
`*
`*&£
`xk
`&
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`4,651,411
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`a)
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`the insulating film portion which projects above the
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`imaginary extension of the interface between a gate
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`oxide film 13 and the gate electrode 14 can be decreased
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`as compared with that in the first embodiment. As a
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`result, excellent step coverage can be provided, and the
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`reliability of the semiconductor device is greatly im-
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`proved.In the third embodimentin which thefilm 17 is
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`formedofsilicon oxide, a maximum effect is obtained
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`whenthe angle @ satisfies a relation 77°=@=90°. If the
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`insulating film 17 is formed of silicon nitride, a maxi-
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`mum effect is obtained when the angle @ satisfies a rela-
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`tion 70°=@590".”
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`What weclaim is:
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`1. A method of manufacturing a MOS device, com-
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`prising steps of: selectively etching a semiconductor
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`substrate to form a groovein a field region and an ele-
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`ment formation region surrounded by said groove with
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`an angle formed between a wall of said groove and a
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`first imaginary extension ofa top surface ofsaid element
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`formation region, the angle satisfying a relation,
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`70° S6=90°;
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`depositing a field insulating film in said groove by
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`chemical vapor deposition; and
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`forming a gate electrode on a gate insulating film on
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`said substrate, said gate electrod extending onto the
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`surface portionof said field insulating film, a thick-
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`ness of an upperportion ofsaid field insulating film
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`above a first imaginary extension of an interface
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`betweensaid said gate insulating film and said gate
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`electrode having a predetermined value greater
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`than zero and being smaller than that of a-lower
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`portion of said field insulating film below thefirst
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`Page 9 of 9
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