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`The evolution
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`of IBM CMOS
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`DRAM
`technology
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`byE.Adier
`E.
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`J.
`K. DeBrosse
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`S.
`F. Geissler
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`S.
`J. Holmes
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`D. Jaffe
`M.
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`B. Johnson
`J.
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`W. KoburgerIII
`C.
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`B. Lasky
`J.
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`Lloyd
`B.
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`G.
`L. Miles
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`S. Nakos
`J.
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`P. Noble, Jr.
`W.
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`H. Voldman
`S.
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`M.
`Armacost
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`R, Ferguson
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`The development of DRAM at IBM produced
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`many novel processes and sophisticated
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`analysis methods. Improvementsin
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`lithography and innovative process features
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`reducedthecell size by a factor of 18.8 in the
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`time between the 4Mb and 256Mb generations.
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`The original substrate plate trench cell used in
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`the 4Mb chipis still the basis of the 256Mb
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`technology being developed today. This paper
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`describes some of the more important and
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`interesting innovations introduced in IBM
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`CMOS DRAMs.Among them, shallow-trench
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`isolation,I-line and deep-UV (DUV) lithography,
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`titanium salicidation, tungsten stud contacts,
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`retrograde n-well, and planarized back-end-of-
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`line (BEOL) technology are core elemenis of
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`current state-of-the-art logic technology
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`described in other papersin this issue.
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`The DRAM specific features described are
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`borderless contacts, the trench capacitor,
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`trench-isolated cell devices, and the ‘‘strap.”’
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`Finally, the methods for study and control of
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`leakage mechanisms which degrade DRAM
`retention time are described.
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`Introduction
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`The 4Mb DRAM generation saw a revolutionary change in
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`technology at IBM, with the introduction of CMOS,trench
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`capacitor storage, and other new processes and structures.
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`Although rapid progress continues, the basic cell structures
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`and many of the processes developed then are being used
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`in the 64Mb and 256Mb DRAMsbeing developed today. In
`addition, much of the technology developed for the 4Mb
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`and 16Mb DRAMsis now used in CMOSlogic technology.
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`This paper describes the DRAM cell used by IBM
`beginning with the 4Mb generation, and tracesits evolution
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`to the 256Mbcell being developed today. We then describe
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`the development of some key technology elements, and
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`explain how key DRAM device problems were solved.
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`Dynamic random access memory has been a good
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`vehicle for technology development, because there is a
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`predictable demandfor a large numberof chips of standard
`design. The density of the array, a well-understood
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`benchmark which determines cost, is a very effective
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`driver of technology development. The addressability and
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`repetitive character of the array makeit possible to find
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`and solve technology problemsin the product. The high
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`volume allows employment of the team of experts required
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`to do a thorough development job. Thus, DRAM is the
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`©Copyright 1995 by International Business Machines Corporation. Copying in printed form for private use is permitted without payment of royalty provided that (1) each
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`reproduction is done without altcration and (2) the Journal reference and IBM copyright notice are included on thefirst page. The title and abstract, but no other portions, of
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`this paper may be copied ordistributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any other
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`portion of this paper must be obtained from the Editor.
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`0018-8646/95/$3.00 © 1995 IBM
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`167
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`TBM J. RES. DEVELOP.
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`VOL. 39 NO. 1/2 JANUARY/MARCH 1995
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`E. ADLER ET AL.
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`Page 1 of 22
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`TSMCExhibit 1025
`TSMCv. IP Bridge
`IPR2016-01246
`
`Page 1 of 22
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`TSMC Exhibit 1025
`TSMC v. IP Bridge
`IPR2016-01246
`
`

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`capacitor
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`single transistor through which it is accessed.
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`performance. As a result, there has been a trend toward
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`increased process complexity, as reflected in the number
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`of masking steps used in the process, which has increased
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`from 13 in the 4Mb generation to 25 in the 256Mb
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`generation.
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`The increase in the complexity of DRAM technology has
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`driven up the cost of DRAM development, resulting in the
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`formation of alliances between companies to reduce the
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`expense to individual companies. The IBM 64Mb DRAM
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`is being developed by an alliance between IBM and
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`Siemens, and the 256Mb bya triple alliance including
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`IBM,Toshiba, and Siemens.
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`DRAMexternal power supplies follow industry
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`standards. Because the chip poweris low enough, DRAM
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`can use on-chip power supply regulation to reduce the
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`internal circuit power supply swings. IBM hasled the
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`industry in reduction of power supply voltages for CMOS
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`logic and memory. DRAMtechnology resists power supply
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`scaling more than logic technology because of the need
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`for storage of charge. Table 1 illustrates this trend.
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`Power supply voltage reduction will come rapidly, since
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`the market for battery-operated equipment is growing
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`faster than previously anticipated. Also, performance
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`competition in microprocessors demands ever-shorter
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`channel lengths, which in turn require reduction in power
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`because of device scaling. DRAM chips and technology
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`will be similarly forced to operate at lower power supply
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`voltages in the near future.
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`The market for battery-operated equipmentalso creates
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`a need for longer DRAMretention times, to reduce the
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`powerassociated with refreshing the data. The data
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`retention time specification is currently 64-256 ms, making
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`very low leakage current a requirement, along with a large
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`cell capacitance.
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`The cell capacitor was a simple planar structure through
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`the 1Mb generation. At and beyond the 4Mbgeneration, as
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`the cell size decreased, the effective surface area of the
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`capacitor was maintained by placing the capacitor on the
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`sides of a narrow trench etchedinto the silicon, or by putting
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`the capacitor on top of the other elementsof the cell.
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`The next section begins by explaining the development
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`of the IBM 4Mbsubstrate plate trench (SPT) DRAM cell,
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`at a cell size of 11.3 um. We next show how important
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`features were added for succeeding generations to reduce
`the cell size to 0.6 m’, where it now stands for the
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`256Mb chip. Succeeding sections trace in more detail the
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`developmentof certain technology elements essential to
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`DRAM.Westart with the strap connection between the
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`storage trench polysilicon and the node diffusion, a unique
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`SPT DRAMrequirement, which is a challenge for process
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`integration. Then we discuss device isolation, retrograde
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`n-well, salicidation,lithography, and metallization. Finally,
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`solutions for various cell device design and retention time
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`problems encountered during DRAM developmentare
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`Cell
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`The one-transistor cell, consisting of a storage capacitor and a
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`product that has driven the state of the art of silicon
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`device technology up to the present day.
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`The one-device DRAM cell [1], invented at IBM by
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`R. Dennard, consists of a cell transistor with the drain
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`connected to one nodeofthe cell storage capacitor, the
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`source connected to a bit line, and the gate connected
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`to the word line, which runs orthogonal to the bit line
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`(Figure 1). The requirement to have a large capacitor in a
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`small space with low leakage is the main driver of DRAM
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`technology. A brief description of the cell operation will
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`help to explain why. To write, the bit line is driven to a
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`high or low logic level with the cell transistor turned
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`on, and then the cell transistor is shut off, leaving the
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`capacitor charged high or low. Since charge leaks off the
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`capacitor, a maximum refresh interval is specified. To
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`read, or refresh the data in the cell, the bit line is left
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`floating when the cell transistor is turned on, and the
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`small changein bit-line potential is sensed and amplified
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`to a full logic level. The ratio of cell capacitancetobit-line
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`capacitance, called the transfer ratio, which ranges from
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`about 0.1 to 0.2, determines the magnitude of the change
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`in bit-line potential. A large cell capacitance is needed to
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`deliver an adequate signal to the sense amplifier.
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`The evolution of technology has followed the following
`overall trends.
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`DRAM cell size has decreased from 11.3 ym’ for
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`the first 4Mb cell to 0.6 ym? for the first 256Mb cell.
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`Improvements in lithography were responsible for much
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`butnot all of the size reduction. New process features
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`were also necessary to shrink the cell and to improve array
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`168
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`E. ADLER ET AL.
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`Page 2 of 22
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`IBM J. RES. DEVELOP. VOL. 39 NO. 1/2 JANUARY/MARCH 1995
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`roeVD
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`4 a
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`NJ
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`Folded bit-line cell configuration, which places two adjacent bit
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`described. Included are gate-induced drain leakage
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`(GIDL), three-dimensional device effects, dislocation-
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`related leakage, and the variable retention time
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`phenomenon.
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`DRAMcell structure evolution
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`The folded bit-line cell array configuration (Figure 2) has
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`been used universally in the industry since the 1Mb time
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`frame. In the folded bit-line configuration, a cell is crossed
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`by two word lines and onebit line. One of the word lines
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`(WL1in Figure 2) is the “active word line’ for the cell,
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`and formsthe gate of the cell device. The second word
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`line (WL2), the “‘passing word line,”’ is the gate of the cell
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`device on the adjacentcell. Thus, the bit line (BL) and
`referencebit line (BL) can be adjacent, leading to better
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`matching and noise rejection, as well as providing a wider
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`pitch for the layout of the sense amplifier. Although the
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`cell now contains two wordlines (active and passing), this
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`does not require more cell area than an openbit-line cell,
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`since the additional area is also generally the same area
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`used for the storage capacitor.
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`IBM adopted CMOStechnology for DRAM at the 4Mb
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`generation. Previously, DRAM had been implemented in
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`simple n-MOStechnology because the latter was relatively
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`inexpensive. However, logic applications, which were
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`sensitive to active power, had already migrated to CMOS.
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`Integration of a DRAM cell structure into a CMOS
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`technology brought with it some fundamental issues which
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`had to be resolved before tackling the cell structure in
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`detail. For an integrated DRAM technology, the doping
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`types and profiles from the starting substrate up to the
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`device gates had to be chosen and optimized to the best
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`trade-off of cost, reliability, function, and speed. The
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`most fundamental issue, however, was the one of choice
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`between n-well CMOSon a p-type substrate and p-well on
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`an n-type substrate. Two important conditions were set
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`which the technology had to meet, and which still obtain
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`for current and future generations:
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`1. The array must be isolated from the substrate by
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`building it within a well of opposite doping to take full
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`advantage of CMOS. This benefits cell retention time by
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`eliminating all leakage current sources associated with
`the substrate wafer. It reduces the incidence of soft
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`
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`
`
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`errors due to ionizing radiation by confining the
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`effective minority carrier collection length within the
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`well and sending many of the generated minority
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`carriers to the substrate, where they do notaffect
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`the storage node diffusion.
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`
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`2. The well potential must be stable despite the impact
`
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`ionization that accompanies FET operation. This
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`ionization is largest for an n-channel device. Therefore,
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`n-MOSdevices should not be positioned in a well
`
`
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`whose conductivity is reduced by light doping or
`
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`
`Power supplies by memory generation.
`Table 1
`
`
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`
`
`
`Memory
`generation
`
`
`
`Memory PS
`
`(V)
`
`
`
`
`Logic PS
`
`(V)
`
`
`
`External
`
`
`
`Internal
`
`
`
`
`3.6
`4 Mb
`5, 3.6
`3.6, 5
`
`
`
`
`
`
`
`5, 3.6, 3.3, 2.5
`3.3, 3.6
`3.3, 5
`16 Mb
`
`3.6, 3.3, 2.5
`3.3
`64b
`3.3
`
`
`
`
`
`
`
`
`
`
`
`
`
`3.3, 2.5 2.5256 Mb 3.3, 2.5, 1.8
`
`
`
`
`PS = powersupply voltage
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`constrained depth. This constraintis satisfied by an
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`n-well CMOStechnology on a heavily doped p-type
`substrate.
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`A p-MOSDRAM arraybuilt in an n-well CMOS
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`technology meets these conditions and was chosen for the
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`4Mb generation. The cell choice was then made within that
`framework.
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`Thecriteria for cell choice are density, process
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`simplicity, adequate storage capacitance for detectable
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`signal, and low parasitic capacitances for performance and
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`minimization of noise. Each generation of DRAM must
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`compete with prior generations by providing an ultimate
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`lower cost per bit. This is accomplished by decreasingcell
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`size with each generation, while minimizing the increase in
`
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`processing cost. The industry trend [2] is to reduce cell
`
`
`
`169
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`IBM J. RES. DEVELOP. VOL. 39 NO. 1/2 JANUARY/MARCH 1995
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`Page 3 of 22
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`E. ADLER ET AL.
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`Page 3 of 22
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`generation plotted together with the square of the
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`minimum lithographic image. This shows that technological
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`innovation, involving a changein cell structure, is needed
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`in addition to lithographic scaling to reduce the cell size by
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`a multiple of one third for each generation. Also, technical
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`advances are required to implement dimensional scaling
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`(reduced heat cycles,film thicknesses, defect levels, etc.)
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`and to mitigate electrical limitations arising from such scaling.
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`At the transition from 1Mb to 4Mb [3], planar capacitors
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`did not provide enough cell capacitance, and were replaced
`
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`by three-dimensional capacitors throughout the industry.
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`These took the form of either trench capacitors buried
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`within etched holes in the silicon [4-7] or stacked
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`capacitors built abovethe silicon [8-12] in the region
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`of the interconnect-levelfilms.
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`The planar capacitor in the 1Mb and prior generations in
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`IBM used an oxide/nitride/oxide (ONO) storage insulator
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`consisting of a sandwich of thermally grown oxide,
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`followed by deposited silicon nitride, which is subjected
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`to oxidation to seal any weak spots in the nitride. Early
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`experiments with deep-trench capacitors produced
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`excellent results using the same ONO storage node
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`insulator used in the 1Mb generation. Since the defect
`
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`levels per unit area were much lower than predicted by
`
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`experience with planar capacitors, trench capacitors
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`were chosen for the 4Mb DRAM generation.
`
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`100.0 94
`
`
`
`Cellsize
`
`SS
`
`
`
`(am?) =Q 0.1
`
`IMb
`
`
`
`4Mb
`
`
`
`16Mb
`
`
`
`64Mb
`
`
`
`
`256Mb
`
`DRAM generation
`
`
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`
`
`DRAMcell size and square of minimum lithographic image vs.
`generation.
`
`
`
` polysilicon
`
`
`
`
`
`All
`
`
`Cross section of 4Mb substrate plate trench (SPT) DRAM cell.
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`size by a factor of 0.33 for each generation. The industry
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`trend in lithography is to reduce the minimum image size
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`by a factor of 0.7 for each generation, so the use of
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`lithography alone would reduce the cell area by 50% for
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`each generation. Figure 3 shows the cell size vs.
`
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`170
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`®@ The 4Mb generation
`
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`The cross section of the IBM 4Mb cell is shownin Figure 4.
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`The capacitor consists of the polysilicon storage node
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`electrode whichfills the trench, the ONO node dielectric
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`on the trench walls, and the p+ substrate which forms
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`the storage plate. Thus, there is no need for the separate
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`plate wiring layer found in other cell types. The trench
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`polysilicon node is connected to the array device diffusion
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`pocket by a selective silicon epitaxy surface strap, which
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`bridges the thin oxide separating the active area and the
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`top surface of the storage node. This cell structure is
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`referred to as the substrate plate trench (SPT)cell [13].
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`This type of cell differs from the standard industry trench
`
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`cells, which either form the storage node in the silicon
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`substrate outside the trench, or stack two polysilicon
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`electrodes separated by the insulator inside the trench.
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`Active device areas are formed in a p-epitaxial layer
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`grown on the p+ substrate. As shownin the layout
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`of Figure 5(a), the active regions are separated by
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`conventional isolation. Because the cell is in a well, a
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`vertical parasitic p-FET is formed between the p+ storage
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`node diffusion and the p+ substrate, with the trench
`
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`polysilicon as the gate. This parasitic device is never
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`turned on because the gate is tied to the p+ storage node
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`diffusion, which is always the source of the p-FET, and
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`the array n-well is back-biased at about 1 V above the
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`power supply voltage.
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`E. ADLER ET AL.
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`Page 4 of 22
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`IBM J. RES, DEVELOP. VOL. 39 NO. 1/2 JANUARY/MARCH 1995
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`Page 4 of 22
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`

`

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`
`© The 16Mb generation
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`In the 4Mbcell, a localized oxidation of silicon (LOCOS)
`
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`isolation region must separate a trench from an adjacent
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`active device area to avoid parasitic sidewall currents
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`gated by the storage node polysilicon, and the automatic
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`strapping of all adjacent nodes and trenches which would
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`otherwise occur. In the 16Mbcell, this limitation was
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`overcome by a modification of the trench structure.
`
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`
`Figure 6 is a cross section of the 16Mbcell, showing
`
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`that the insulator lining the trench now contains a thick
`
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`(approximately 100-nm) SiO, collar which extends from the
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`silicon surface to a point below the n-well. The thick SiO,
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`collar prevents unwanted bridging of exposed nodesilicon
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`and diffusion surfaces. It also has the function of isolating
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`the node trench polysilicon from the cell device edge unde
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`the word line, which was the role of the LOCOSisolation
`
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`in the 4Mbcell. To further isolate the storage trench
`
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`polysilicon from the abutting cell device region and the
`
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`word line, the top of the trench polysilicon must also be
`recessed below the active device area wafer surface and
`
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`covered by a thick oxide. The storage trench can now be
`
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`
`placed in the space betweencell devices, as shownin
`
`
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`
`
`Figure 5(b). This increases the efficiency of the cell layout
`
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`by decreasing the area devoted to thick oxide isolation and
`
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`increasing the area available for storage capacitance.
`
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`Electrical connection between the trench polysilicon
`
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`node and the array device across the thick collar is made
`
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`by a deposited polysilicon surface strap using a novel
`
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`
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`process to be described in a subsequent section of
`
`
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`
`
`this paper. This strap is borderless to the dielectric-
`
`
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`
`
`encapsulated word line. This reduces the active-to-passing
`
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`word-line space, which was determined by the overlay
`
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`tolerance of the trench, isolation, and word-line layers in
`
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`the 4Mb cell. The 16Mbcell is referred to as the merged
`
`
`
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`
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`isolation and node trench (MINT) SPTcell [14].
`
`
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`
`
`© The 64Mb generation
`
`
`
`
`
`
`
`Along with the density increases, improvements in
`
`
`
`
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`
`
`performance werealso realized as a consequence of
`
`
`
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`
`
`
`scaling. During the 4Mb and 16Mb generations, the lower
`
`
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`
`
`
`performance of a p-MOSceil device relative to n-MOS
`
`
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`was not a problem. With the 64Mbgeneration, the time
`
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`required to move data in and outof cells could be
`
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`significant. Therefore, an n-MOSarray was desired. The
`
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`simplest structural change to achieve this would be simply
`
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`
`to interchange n-material for p-material relative to the 4Mb
`
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`and 16Mb generations. Thus, the starting material would
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`be n-type, with implanted p-wells in which thecell arrays
`
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`would be formed. However, this structure forfeited the
`
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`noise immunity advantages of n-well technology as argued
`
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`
`for the 4Mb and 16Mbgenerations. The benefits of an
`
`
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`
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`n-well CMOStechnology on a p-type substrate could be
`
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`
`retained at the cost of some increased process complexity.
`
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`The array p-well and the substrate would have to be
`
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`
`
`Relative scale
`
`
`
` (a)
`AUTH TaND :ueAN 4
`
`
`
`
`
`in
`NT
`f
`TI
`
`ty
`
`
`
`
`crocLLLee
`
`
`amTO
`
`
`
` (©)
`
`
`
`
`
`(d)
`
`
`
`ii Bit-line contact
`
`
`
`Storage trench
`
`
`NY Word line
`
`
`
`
`Cl] Strap
`
`
`{JJ tsotation
`
`
`i
`(a) 4Mb, (b) 16Mb, (c) 64Mb, and
`Layouts of DRAM cells:
`i
`(d) 256Mb. Layouts are shown in both same-size and scaled-
`1
`size drawings.
`
`
`
`
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`
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`electrically isolated. This allowed the array well to be
`
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`
`reverse-biased (—1 V) for low leakage, low parasitic
`
`
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`
`
`
`capacitance, and maximum signal, while the substrate
`
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`
`
`was at ground for low noise and best performance.
`
`
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`
`
`Figure 7 shows the cell configuration which achieves
`
`
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`
`
`
`this for the 64Mb generation. The array p-well is isolated
`
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`
`
`from the substrate by an underlying n-type layer which is
`
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`
`
`formed by outdiffusion from a source deposited within the
`
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`
`
`trenches. In a dense array, the trenches are close enough
`
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`
`
`
`
`together that diffused regions form a continuous n-type
`
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`
`layer. Since the n-type region extends to the bottom of the
`
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`trenches, it also serves as a capacitor plate. Connection of
`
`
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`
`
`this n-type plate to the top surface is formed by an n-well
`
`
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`
`
`
`
`
`ring which surrounds the array. This cell configurationis
`
`
`
`
`
`
`
`
`called the buried plate trench (BPT)cell [15].
`
`
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`
`
`
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`
`
`The overall cell layout is similar to that of the 16Mb
`
`
`
`
`
`
`
`
`
`generation, as shown by Figure 5(c), with the addition of a
`
`““borderless contact.”’ This feature reducesthe cell size
`
`
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`
`by eliminating the diffusion border required between the
`
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`bit-line contact and the adjacent word line. This requires
`
`
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`
`
`
`
`
`
`a special contact structure made by imposing a film
`
`171
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`IBM J. RES. DEVELOP. VOL. 39 NO. 1/2 JANUARY/MARCH 1995
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`Page 5 of 22
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`E. ADLER ET AL.
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`Page 5 of 22
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`

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`
`
`1 Cross section of 64Mb buried plate trench (BPT) DRAM cell.
`
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`
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`
`
`deposition of the etch-stop film, so that the contact hole
`
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`
`
`can be opened without exposing any portion of the word
`
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`line which may be within the contact image.
`
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`
`
`®@ The 256Mb generation
`
`
`
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`
`
`
`
`Scaling of the 64Mb surface strap to 256Mb dimensions
`
`
`
`
`
`presented formidable challenges, because the strap-to-
`
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`
`
`trench overlay is critical to the width of the cell, and the
`
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`
`strap must be built in the narrow opening between the
`
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`active and passing word lines. For these reasons, a new
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`strap structure, the “‘buried strap,”’ and a differentcell
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`layout were used as shown in Figure 8 and Figure 5(d).
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`The buried strap is fabricated early in the process and. has
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`a diffused connection formed by creating a sidewall contact
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`on one edge of the trench capacitor. It saves the cost of
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`the strap mask and avoids the high-aspect-ratio processing
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`in the active-to-passing word-line space. Unfortunately,
`this cell layout produces a relatively smaller trench than
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`its predecessor, but this is compensated for by scaling the
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`node dielectric thickness to increase the cell capacitance
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`and biasing the plate at V/2 to reduce maximumfield in the
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`dielectric. Otherwise, the well/substrate configuration is as
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`described for the 64Mb generation. This cell is referred to
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`as the buried strap trench (BEST) cell [16].
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`Table 2 summarizes the process sequence as it evolved
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`from the 4Mb generation through the 256Mb generation.
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`It shows that a large number of processes were kept from
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`generation to generation, while additions were also made.
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`The strap connection between the node trench polysilicon
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`fill and the node diffusion was changedsignificantly for
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`each generation. We now discuss the technology elements
`in more detail.
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`Strap process development
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`The ‘‘strap”’ which connects the drain of the array transfer
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`device to the storage trench polysilicon is an essential part
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`of the STP cell. This strap adds small cost and requires
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`little additional area; it should not degrade the retention
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`time of the cell. It is a special DRAM-oriented process
`that demands the utmost in inventiveness to be
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`successful.
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`The strap process for the 4Mb DRAM relies on the fact
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`that the diffusion and polysilicon in the storage trench are
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`coplanar and are separated only by the 10-nm ONOlayer
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`on the trench sidewall (Figure 4). After the spacers on the
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`gate conductor are formed and the junctions implanted, a
`thin (70-nm)layer of intrinsic selective silicon is grown.
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`This bridges the ONOinsulating layer [17]. The next step
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`is salicide formation, which consumesthe selective silicon
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`and forms a low-resistance strap. Both selective silicon
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`deposition and salicidation are needed to form such a
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`strap. This process uses no extra masks for the strap, but
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`increases the word pitch because the passing word line
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`cannot pass over the strap contact.
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`Cross section of 16Mb merged isolation and node trench (MINT)
`DRAMcell.
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`underneath the interlevel oxide, which can act as an etch
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`stop during formation of the hole for the contact stud.
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`The word line must be insulator-encapsulated prior to the
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`172
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`E. ADLER ET AL.
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`Page6 of 22
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`IBM ]. RES. DEVELOP. VOL. 39 NO. 1/2 JANUARY/MARCH 1995
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`Page 6 of 22
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`In the 16Mb cell, the strap must bridge the 160-nm-wide
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`oxide collar and a 160-nm step from the trench top to the
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`node diffusion (Figure 6). Selective silicon was not used,
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`because the thickness required would cause spurious
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`nucleation on insulators and bridging of the storage trench
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`to the ‘‘wrong”’ diffusion.
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`To produce a manufacturable strap, a novel process,
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`called “‘boron out-diffused surface strap,”’ or BOSS, was
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`developed. After source—drain implantation, a thin layer of
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`silicon nitride is deposited on the chip. A contact hole is
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`etched through thesilicon nitride and trench top oxide in
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`each cell, exposing the boron-doped trench polysilicon and
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`p+ diffusions that are to be connected. A thick SiO, cap
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`and sidewall spacer are required on the gate electrode to
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`avoid exposure of the gate electrode surface during this
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`etch. A blanket layer of intrinsic polysilicon is deposited,
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`and the wafer is annealed to diffuse boron up into the
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`intrinsic polysilicon from the trench and diffusion tops.
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`The result is a boron-doped polysilicon layer bridging the
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`trench and diffusion within each hole. The remaining
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`intrinsic polysilicon is then removed by a selective wet
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`etch, isolating the cells from one another. Finally, an oxide
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`is grown over the strap polysilicon, and the blanketnitride
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`contact
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` Borderless
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`isolation
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`Storage node
`trench
`polysilicon
`fill
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`RO
`Cross section of 256Mb buried strap trench (BEST) DRAMcell.
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`Table 2 Process sequence for IBM DRAM products.
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`Process flow through Metal 1 by DRAM generation
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`4 Mb
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`16 Mb
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`64 Mb
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`—
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`Buried plated
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