IPR2016-01246; IPR2016-01247
`U.S. Patent No. 7,126,174
`
`
`Filed on behalf of Godo Kaisha IP Bridge 1
`
`
`
`
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Case IPR2016-012461
`U.S. Patent No. 6,538,324
`____________
`
`DECLARATION OF AMANDA DOVE
`
`
`
`
`
`
`
`Mail Stop PATENT BOARD, PTAB
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`1 Case IPR2016-01247 has been consolidated with this proceeding.
`
`
`
`Page 1 of 11
`
`IP Bridge Exhibit 2020
`TSMC v. IP Bridge
`IPR2016-01246
`
`
`U.S. Patent No. 7,126,174
`
`
`Filed on behalf of Godo Kaisha IP Bridge 1
`
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Case IPR2016-012461
`U.S. Patent No. 6,538,324
`____________
`
`DECLARATION OF AMANDA DOVE
`
`
`
`
`
`
`
`Mail Stop PATENT BOARD, PTAB
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`1 Case IPR2016-01247 has been consolidated with this proceeding.
`
`
`
`Page 1 of 11
`
`IP Bridge Exhibit 2020
`TSMC v. IP Bridge
`IPR2016-01246
`
`
`
`IPR2016-01246; IPR2016-01247
`U.S. Patent No. 7,126,174
`
`
`I, Amanda Dove, declare as follows:
`
`1.
`
`2.
`
`I am a paralegal at the law firm of Greenblum & Bernstein, P.L.C.
`
`I provide this Declaration in connection with the above-identified
`
`Inter Partes Review proceedings.
`
`3.
`
`Exhibit 2002 is a true copy of Schematic illustration of the Chemical
`
`Mechanical Polishing process from Steigerwald, Murarka, and Gutmann, Chemical
`
`Mechanical Planarization of Microelectronic Materials (1997). An exhibit label
`
`and pagination labels have been added. On March 23, 2017,
`
`https://catalog.loc.gov/ was accessed, and a copy of the Library of Congress Online
`
`Catalog Record of this book under LC Control No. 96006198 from
`
`https://lccn.loc.gov/96006198 was printed using the “Print Record” feature on this
`
`webpage. The copy of the record is now Exhibit 2034.
`
`4.
`
`Exhibit 2003 is a true copy of Schematic illustration of the Chemical
`
`Mechanical Polishing process from the Motorola Company. SCSolutions.com.
`
`Accessed September 30, 2016. http://www.scsolutions.com/chemical-mechanical-
`
`planarization-cmp-controllers-0. An exhibit label and pagination labels have been
`
`added.
`
`5.
`
`Exhibit 2004 is a true copy of Photograph of a Chemical Mechanical
`
`Polishing Tool from the Applied Materials Company. BusinessWire.com.
`
`Accessed October 5, 2016. http://www.businesswire.com/news/home/
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`1
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`Page 2 of 11
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`IPR2016-01246; IPR2016-01247
`U.S. Patent No. 7,126,174
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`20040711005007/en/Applied-Materials-Revolutionizes-Planarization-Technology-
`
`Breakthrough-Reflexion. An exhibit label and pagination labels have been added.
`
`6.
`
`Exhibit 2005 is a true copy of Troxel, Boning, McIlrath
`
`“Semiconductor Process Representation.” Wiley Encyclopedia of Electrical and
`
`Electronics, pp.139 –147 (1999). An exhibit label and pagination labels have been
`
`added. The paper is available online on the Wiley Online Dictionary website at
`
`http://onlinelibrary.wiley.com/doi/10.1002/047134608X.W7034/abstract.
`
`7.
`
`Exhibit 2008 is a true copy of Hunt, “Low Budget Undergraduate
`
`Microelectronics Laboratory.” University Government Industry Microelectronics
`
`Symposium, pp.81-87 (2006). An exhibit label and pagination labels have been
`
`added. The paper is available online on the IEEE Xplore Digital Library website at
`
`http://ieeexplore.ieee.org/document/4286358/.
`
`8.
`
`Exhibit 2010 is a true copy of Burckel, “3D-ICs created using oblique
`
`processing.” Advanced in Patterning Materials and Processes XXXIII, pp. 1–12
`
`(2016). An exhibit label and pagination labels have been added. The paper is
`
`available online on the SPIE Digital Library at
`
`http://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=2506082.
`
`9.
`
`Exhibit 2013 is a true copy of Thompson, L. F. “An Introduction to
`
`Lithography.” Introduction to Microlithography, ACS Symposium Ser., American
`
`Chemical Society, pp. 1-13 (1983). An exhibit label and pagination labels have
`
`2
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`Page 3 of 11
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`IPR2016-01246; IPR2016-01247
`U.S. Patent No. 7,126,174
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`been added. Relevant portions of this exhibit have been highlighted. The chapter is
`
`available online on the ACS Publications website at
`
`http://pubs.acs.org/doi/abs/10.1021/bk-1983-0219.ch001. On March 23, 2017,
`
`https://catalog.loc.gov/ was accessed, and a copy of the Library of Congress Online
`
`Catalog Record of the print version of this book under LC Control No. 83005968
`
`from https://lccn.loc.gov/ 83005968 was printed using the “Print Record” feature
`
`on this webpage. The copy of the record is now Exhibit 2035.
`
`10. Exhibit 2014 is a true copy of CA1275846 C to Roland et al.,
`
`downloaded from the European Patent Office’s Espacenet Patent Search website.
`
`An exhibit label and pagination labels have been added. Relevant portions of this
`
`exhibit have been highlighted.
`
`11. Exhibit 2015 is a true and correct copy of U.S. Patent No. 5,314,843.
`
`An exhibit label and pagination labels have been added. Relevant portions of this
`
`exhibit have been highlighted.
`
`12. Exhibit 2016 is a true and correct copy of U.S. Patent No. 5,231,306.
`
`An exhibit label and pagination labels have been added. Relevant portions of this
`
`exhibit have been highlighted.
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`13. Exhibit 2017 is a true and correct copy of U.S. Patent No. 4,529,621.
`
`An exhibit label and pagination labels have been added. Relevant portions of this
`
`exhibit have been highlighted.
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`3
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`Page 4 of 11
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`14. Exhibit 2018 is a true and correct copy of U.S. Patent No. 5,310,624.
`
`IPR2016-01246; IPR2016-01247
`U.S. Patent No. 7,126,174
`
`
`An exhibit label and pagination labels have been added. Relevant portions of this
`
`exhibit have been highlighted.
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`15. Exhibit 2019 is a true and correct copy of U.S. Patent No. 5,097,422.
`
`An exhibit label and pagination labels have been added. Relevant portions of this
`
`exhibit have been highlighted.
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`16. Exhibit 2021 is a true and correct copy of U.S. Patent No. 4,952,524.
`
`An exhibit label and pagination labels have been added. Relevant portions of this
`
`exhibit have been highlighted.
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`17. Exhibit 2022 is a true copy of Bryant, A.; Haensch, W.; Geissler, S;
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`Mandelman, Jack; Poindexter, D.; and Steger, M. “The Current-Carrying Corner
`
`Inherent to Trench Isolation.” IEEE Electron Device Letters, Vol. 14, No. 8, pp.
`
`412-414 (1993). An exhibit label and pagination labels have been added. Relevant
`
`portions of this exhibit have been highlighted. On March 23, 2017,
`
`https://catalog.loc.gov/ was accessed, and a copy of the Library of Congress Online
`
`Catalog Record of this journal under LC Control No. 81643614 from
`
`https://lccn.loc.gov/81643614 was printed using the “Print Record” feature on this
`
`webpage. The “Older receipts” section of the record indicates that Nos. 4-10 of
`
`Volume 14 of this journal were published in 1993. The copy of the record is now
`
`Exhibit 2036.
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`4
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`Page 5 of 11
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`18. Exhibit 2023 is a true copy of Ohe, Kikuyo; Odanaka, Shinji;
`
`IPR2016-01246; IPR2016-01247
`U.S. Patent No. 7,126,174
`
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`Moriyama, Kaori; Hori, Takashi; and Fuse, Genshu. “Narrow-Width Effects of
`
`Shallow Trench-Isolated CMOS with n+-Polysilicon Gate.” IEEE Transactions on
`
`Electron Devices, Vol. 36, No. 6, pp. 1110-1116 (1989). An exhibit label and
`
`pagination labels have been added. Relevant portions of this exhibit have been
`
`highlighted. On March 23, 2017, https://catalog.loc.gov/ was accessed, and a copy
`
`of the Library of Congress Online Catalog Record of this journal under LC Control
`
`No. sn 78000467 from https://lccn.loc.gov/sn78000467 was printed using the
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`“Print Record” feature on this webpage. The “Older receipts” section of the record
`
`indicates that No. 7 of Volume 35 through No. 12 of Volume 36 of this journal
`
`were published between July 1988 and December 1989. The copy of the record is
`
`now Exhibit 2037.
`
`19. Exhibit 2024 is a true copy of Shigyo, N.; Wada, T.; Fukuda, S.;
`
`Hieda, K., Hamamoto, T.; Watanabe, H.; Sunouchi, K.; and Tango, H. “Steep
`
`Subthreshold Characteristic and Enhanced Transconductance of Fully-Recessed
`
`Oxide (Trench) Isolated 1/4 µ m Width MOSFETs.” 1987 International Electron
`
`Devices Meeting, pp. 636-639 (1987). An exhibit label and pagination labels have
`
`been added. Relevant portions of this exhibit have been highlighted. The paper is
`
`available online on the IEEE Xplore Digital Library website at
`
`http://ieeexplore.ieee.org/document/1487466/. The front cover and table of
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`5
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`Page 6 of 11
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`IPR2016-01246; IPR2016-01247
`U.S. Patent No. 7,126,174
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`contents of the original publication from the meeting were downloaded from
`
`http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9953, which is now
`
`Exhibit 2038. Page 21 of 27 of Exhibit 2038 indicates the above paper as Item
`
`28.3 at page 636.
`
`20. Exhibit 2025 is a true copy of Furukawa, T., and Mandelman, J.A.
`
`“Process and Device Simulation of Trench Isolation Corner Parasitic Device.”
`
`Journal Of The Electrochemical Society, Vol. 135, No. 8, p. 358C, Item 236
`
`(1988). An exhibit label and pagination labels have been added. A frame was
`
`added where appropriate.
`
`21. Exhibit 2026 is a true copy of “Structural Analysis Sample Report”
`
`downloaded from
`
`https://www.chipworks.com/TOC/Structural_Analysis_Sample_Report.pdf. An
`
`exhibit label and pagination labels have been added. Page 1-5 indicates that the
`
`document was current as of January 2008.
`
`22.
`
` Exhibit 2027 is a true and correct copy of U.S. Patent No. 4,776,922.
`
`An exhibit label and pagination labels have been added. Relevant portions of this
`
`exhibit have been highlighted.
`
`23. Exhibit 2028 is a true copy of Subbanna, S.; Ganin, E.; Crabbé, E.;
`
`Comfort, J.; Wu, S.; Agnello, P.; Martin, B.; McCord, M.; Newman, H. Ng. T.;
`
`McFarland, P.; Sun, J.; Snare, J.; Acovic, A.; Ray, A.; Gehres, R.; Schulz, R.;
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`6
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`Page 7 of 11
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`IPR2016-01246; IPR2016-01247
`U.S. Patent No. 7,126,174
`
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`Greco, S.; Beyer, K.; Liebmann, L.; DellaGuardia, R.; Lamberti, A. “200 mm
`
`Process Integration for a 0.15 µm Channel-Length CMOS Technology Using
`
`Mixed X-Ray / Optical Lithography.” Proceedings of 1994 IEEE International
`
`Electron Devices Meeting, pp. 695-698 (1994). An exhibit label and pagination
`
`labels have been added. Relevant portions of this exhibit have been highlighted.
`
`The paper is available online on the IEEE Xplore Digital Library website at
`
`http://ieeexplore.ieee.org/document/383318/. The front cover of the original
`
`publication from the meeting was downloaded from
`
`http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=3058, which is now
`
`Exhibit 2039.
`
`24. Exhibit 2029 is a true copy of Chung, J.; Jeng, M.-C.; Moon, J.E.;
`
`Wu, A.T.; Chan, T.Y.; Ko, P.K.; Hu, Chenming. “Deep-Submicrometer MOS
`
`Device Fabrication Using a Photoresist-Ashing Technique.” IEEE Electron Device
`
`Letters, Vol. 9. No. 4, pp. 186-188 (1988). An exhibit label and pagination labels
`
`have been added. Relevant portions of this exhibit have been highlighted. The
`
`paper is available online at the IEEE Xplore Digital Library website
`
`http://ieeexplore.ieee.org/Xplore/home.jsp.
`
`25. Exhibit 2030 is a true copy of Tanaka, Tetsu; Suzuki, Kunihiro; Horie,
`
`Hiroshi; Sugii, Toshihiro. “Ultrafast Low-Power Operation of p+-n+ Double-Gate
`
`SOI MOSFETS.” 1994 Symposium on VLSI Technology Digest of Technical
`
`7
`
`Page 8 of 11
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`
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`IPR2016-01246; IPR2016-01247
`U.S. Patent No. 7,126,174
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`Papers, pp. 11-12 (1994). An exhibit label and pagination labels have been added.
`
`Relevant portions of this exhibit have been highlighted. The paper is available
`
`online on the IEEE Xplore Digital Library website at
`
`http://ieeexplore.ieee.org/document/324402/.
`
`26. Exhibit 2031 is a true copy of WIPO Publication No. WO 90/05377 to
`
`Lowrey downloaded from the European Patent Office’s Espacenet Patent Search
`
`website. An exhibit label and pagination labels have been added. Relevant
`
`portions of this exhibit have been highlighted.
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`27. Exhibit 2032 is a true copy of Kaufman, F. B.; Thompson, D. B.;
`
`Broadie, R. E.; Jaso, M. A.; Guthrie, W. L.; Pearson, D. J.; and Small, M. B.
`
`“Chemical‐Mechanical Polishing for Fabricating Patterned W Metal Features as
`
`Chip Interconnects.” Journal of The Electrochemical Society, Vol. 138, No. 11, pp.
`
`3460-3465 (1991). An exhibit label and pagination labels have been added (so as
`
`not to obscure information). The paper is available online on the ECS Digital
`
`Library website at http://jes.ecsdl.org/content/138/11.toc.
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`28. Exhibit 2033 is a true copy of Landis, H.; Burke, P.; Cote, W.; Hill,
`
`W.; Hoffman, C.; Kaanta, C.; Koburger, C.; Lange, W.; Leach, M.; and Luce, S.
`
`“Integration of chemical-mechanical polishing into CMOS integrated circuit
`
`manufacturing.” Thin Solid Films, Vol. 220, No. 1-2, pp.1-7 (1992). An exhibit
`
`label and pagination labels have been added. The paper is available online on the
`
`8
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`Page 9 of 11
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`IPR2016-01246; IPR2016-01247
`U.S. Patent No. 7,126,174
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`Elsevier’s ScienceDirect website at
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`http://www.sciencedirect.com/science/journal/00406090/220.
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`IPR2016-01246; IPR2016-01247
`U.S. Patent No. 7,126,174
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` I
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` declare that all statements made herein of my knowledge are true, and that
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`all statements made on information and belief are believed to be true, and that
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`these statements were made with the knowledge that willful false statements and
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`the like so made are punishable by fine or imprisonment, or both, under Section
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`1001 of Title 18 of the United States Code.
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`
`
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`
`
` March 24, 2017
`Date
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`
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`By: /Amanda Dove/
`Amanda Dove
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`10
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`Page 11 of 11
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