Case IPR2016-1246
`U.S. Patent No. 7,126,174
`
`Filed on behalf of Godo Kaisha IP Bridge 1
`
`By: Neil F. Greenblum (ngreenblum@gbpatent.com)
`Greenblum & Bernstein, P.L.C.
`1950 Roland Clarke Place
`Reston, VA 20191
`Tel: 703-716-1191
`Fax: 703-716-1180
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Case IPR2016-01246
`U.S. Patent No. 7,126,174
`____________
`
`PATENT OWNER’S PRELIMINARY RESPONSE
`PURSUANT TO 37 C.F.R. §42.107
`
`Mail Stop PATENT BOARD, PTAB
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`

`
`Case IPR2016-1246
`U.S. Patent No. 7,126,174
`
`TABLE OF CONTENTS
`
`I.
`
`II.
`
`REQUESTED RELIEF ...................................................................................1
`
`INTRODUCTION ...........................................................................................1
`
`A.
`
`Dispositive Issue In IPR2016-01246 And IPR2016-01247..................2
`
`B.
`
`Background ...........................................................................................3
`The Premise Of The Petitioner’s Argument Is Legally Insufficient...10
`III. RELEVANT CASE LAW.............................................................................13
`
`C.
`
`A.
`
`B.
`
`C.
`
`There Must Be A Likelihood Of Invalidity.........................................13
`
`The Burden Of Persuasion ..................................................................13
`
`The Petitioner Bears The Burden Of Establishing A Rationale For
`Combining The Prior Art ....................................................................14
`
`The PTO is Bound by Record Arguments Petitioner has Made .........15
`D.
`THE CLAIMED INVENTION OF THE ‘174 PATENT .............................16
`LEVEL OF ORDINARY SKILL ..................................................................18
`
`IV.
`
`V.
`
`A.
`
`B.
`C.
`
`VI. CLAIM CONSTRUCTION ..........................................................................18
`VII. THE ‘174 PATENT – RIGHT OF PRIORITY............................................20
`VIII. PRIOR ART...................................................................................................20
`U.S. Patent No. 5,153,145 (“Lee”)......................................................21
`U.S. Patent No. 5,539,229 (“Noble”) ..................................................22
`U.S. Patent No. 4,506,434 (“Ogawa”) ................................................24
`IX. ARGUMENT: LEE & NOBLE......................................................................25
`Claim 1 Of The ‘174 Patent ................................................................25
`Petitioner’s Rejection Of The Claims Over Lee In View Of Noble
`Has No Merit .......................................................................................26
`
`A.
`
`B.
`
`C.
`D.
`
`The Initial Processing Sequence Of Noble Is Opposite From Lee......27
`Lee And Noble Processes Are Not Compatible ..................................33
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`Case IPR2016-1246
`U.S. Patent No. 7,126,174
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`E.
`
`A Lee-Noble Rejection Fails On Further Grounds..............................38
`
`1.
`
`2.
`
`There is No Disclosure Of How L-Shaped Sidewalls Can Be
`Formed ......................................................................................38
`
`Salicidation Of Lee....................................................................39
`
`F.
`
`Conclusions Regarding The Lee-Noble Combination ........................39
`
`X.
`
`ARGUMENT: LEE & OGAWA ....................................................................41
`
`A.
`
`B.
`
`C.
`
`D.
`
`Lee & Ogawa.......................................................................................42
`
`Initial Processing Sequence Of Ogawa Is Opposite From Lee...........43
`
`Lee And Ogawa Processes Are Not Compatible ................................46
`
`Conclusions Regarding The Lee-Ogawa Combination ......................52
`
`XI. CONCLUSION..............................................................................................54
`
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`Case IPR2016-1246
`U.S. Patent No. 7,126,174
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`TABLE OF AUTHORITIES
`
`CASES
`
`Allied Erecting and Dismantling Co., Inc. v. Genesis Attachments, LLC,
`
`825 F.3d 1373, 1381 (Fed. Cir. 2016). .................................................................14
`
`Arendi S.A.R.L. v. Apple Inc.,
`
`No. 2015-2073, 2016 WL 4205964, *9 (Fed. Cir. Aug. 10, 2016) ......................15
`
`Dynamic Drinkware, LLC v. Nat'l Graphics, Inc.,
`
`800 F.3d 1375, 1378 (Fed. Cir. 2015). .................................................................13
`
`In re Giannelli,
`
`739 F. 3d 1375, 1380 (Fed. Cir. 2014) .................................................................15
`
`In re Lee,
`
`277 F.3d 1338, 1345 (Fed. Cir. 2002) ..................................................................14
`
`In re Warsaw Orthopedic, Inc.,
`
`2016 U.S. App. LEXIS 14560, *18 (Fed. Cir. 2016) .................................... 14, 15
`
`In re: Lemay,
`
`2016 U.S. App. LEXIS 17041, *5 (Fed. Cir. 2016). ............................................15
`
`In Re: Magnum Oil Tools International, Ltd.,
`
`119 U.S.P.Q.2D (BNA) 1541, 1548, 1552, 1553 (Fed. Cir. 2016). ........ 13, 14, 15
`
`Pfizer, Inc. v. Apotex, Inc.,
`
`480 F.3d 1348, 1361 (Fed. Cir. 2007) ..................................................................14
`
`Phillips v. AWH Corp.,
`
`415 F.3d 1303 (Fed. Cir. 2005) .................................................................... 18, 19
`
`Synopsys, Inc. v. Mentor Graphics Corp.,
`
`814 F.3d 1309, 1322 (Fed. Cir. 2016) ..................................................................14
`
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`Case IPR2016-1246
`U.S. Patent No. 7,126,174
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`STATUTES
`
`35 U.S.C. §313...........................................................................................................1
`
`REGULATIONS
`
`37 C.F.R. § 42.100(b) ..............................................................................................18
`
`37 C.F.R. §42.107 ......................................................................................................1
`
`37 C.F.R. §42.108 ................................................................................................1, 13
`
`37 C.F.R. §42.108. ...................................................................................................13
`
`37 C.F.R. §42-100 et seq. ..........................................................................................1
`
`iv
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`

`
`Exhibit 2001:
`
`Exhibit 2002:
`
`Exhibit 2003:
`
`Exhibit 2004:
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`Case IPR2016-1246
`U.S. Patent No. 7,126,174
`
`EXHIBIT LIST
`
`Declaration of Dr. E. Fred Schubert, Ph.D. in support of
`Patent Owner’s Preliminary Response
`
`Schematic illustration of the Chemical Mechanical Polishing
`process from Steigerwald, Murarka, and Gutmann, Chemical
`Mechanical Planarization of Microelectronic Materials (1997).
`
`Schematic illustration of the Chemical Mechanical Polishing
`process from the Motorola Company. SCSolutions.com.
`Accessed September 30, 2016.
`http://www.scsolutions.com/chemical-mechanical-
`planarization-cmp-controllers-0
`
`Photograph of a Chemical Mechanical Polishing Tool from the
`Applied Materials Company. BusinessWire.com. Accessed
`October 5, 2016.
`http://www.businesswire.com/news/home/20040711005007/en/
`Applied-Materials-Revolutionizes-Planarization-Technology-
`Breakthrough-Reflexion
`
`Exhibit 2005:
`
`Troxel, Boning, McIlrath “Semiconductor Process
`Representation.” Wiley Encyclopedia of Electrical and
`Electronics, pp.139 –147 (1999).
`
`Exhibit 2006:
`
`U.S. Patent No. 6,052,319 to Jacobs
`
`Exhibit 2007:
`
`U.S. Patent No. 6,952,656 to Cordova et al.
`
`Exhibit 2008:
`
`Hunt, “Low Budget Undergraduate Microelectronics
`Laboratory.” University Government Industry Microelectronics
`Symposium, pp.81-87 (2006).
`
`Exhibit 2009:
`
`U.S. Patent No. 7,074,709 to Young
`
`Exhibit 2010:
`
`Burckel, “3D-ICs created using oblique processing.” Advanced
`in Patterning Materials and Processes XXXIII, pp. 1–12 (2016).
`
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`

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`Case IPR2016-1246
`U.S. Patent No. 7,126,174
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`I. REQUESTED RELIEF
`
`Pursuant to 35 U.S.C. §313 and 37 C.F.R. §42.107, Patent Owner Godo
`
`Kaisha IP Bridge 1 respectfully requests that the Patent Trial and Appeal Board
`
`(“PTAB” or “Board”) decline to institute an inter partes review under 35 U.S.C.
`
`§314 based on the Petition for Inter Partes Review of U.S. Patent No. 7,126,174
`
`pursuant to 37 C.F.R. §42-100 et seq. (IPR2016-01246, “Petition”) filed by Taiwan
`
`Semiconductor Manufacturing Company, Ltd. (“Petitioner”) on June 24, 2016.
`
`II.
`
`INTRODUCTION
`
`The Petition requests review of Claims 1-3, 5-7, 9-12, and 14-18
`
`(“challenged claims”) of U.S. Patent No. 7,126,174 (“the ‘174 Patent”)(Exhibit
`
`1001) Petition, p. 17. Claim 1 is the only challenged independent claim. The
`
`Petition asserts that the challenged claims are unpatentable for obviousness over
`
`(1) U.S. Patent No. 5,153,145 (“Lee”)(Exhibit 1002) in view of U.S. Patent No.
`
`5,539,229 (“Noble”)(Exhibit 1015), or (2) Lee in view of U.S. Patent No.
`
`4,506,434 (“Ogawa”)(Exhibit 1010). The ‘174 patent expired on July 24, 2016.
`
`As explained herein, the Petition fails to demonstrate that there is a
`
`reasonable likelihood that at least one of the claims challenged in the Petition is
`
`unpatentable. 37 C.F.R. §42.108. Specifically, the Petition fails to establish that it
`
`would have been obvious to a person of ordinary skill in the art (“POSITA”) to
`
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`U.S. Patent No. 7,126,174
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`modify the semiconductor device formed by LOCOS (Local Oxidation of Silicon)
`
`disclosed in Lee with the semiconductor device formed by shallow trench isolation
`
`(STI) disclosed in Noble or Ogawa, to arrive at the invention recited in the
`
`challenged claims. The Petition’s obviousness arguments of Lee in view of Noble
`
`and Lee in view of Ogawa fail to demonstrate that there is a reasonable likelihood
`
`that at least one of the claims as challenged in the Petition is unpatentable. Thus,
`
`for at least the reasons set forth herein, the PTAB should deny institution of this
`
`IPR proceeding.
`
`A.
`
`Dispositive Issue In IPR2016-01246 And IPR2016-01247
`
`Petitioner has concurrently filed two IPR Petitions challenging the ‘174
`
`patent: IPR2016-01246 and IPR2016-01247.
`
`In IPR2016-01246, the Petition asserts that the challenged claims are
`
`unpatentable over Lee in combination with Noble or Ogawa, and in IPR2016-
`
`01247, the Petition asserts that the challenged claims are unpatentable over Lowrey
`
`in combination with Noble or Ogawa.
`
`There are various reasons why each of the proposed rejections is
`
`insufficient, however, there is at least one dispositive issue applicable to all four of
`
`the proposed rejections.
`
`The four proposed rejections are needlessly redundant of one another. In
`
`each of the four proposed rejections, the Petition asserts that the primary reference
`
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`(Lee or Lowrey) teaches every limitation of the challenged claims except trench
`
`isolation. The Petitions then both assert that Noble or Ogawa discloses trench
`
`isolation, and that as a general proposition it would have been obvious to substitute
`
`trench isolation for the LOCOS isolation disclosed in the primary references.
`
`Neither the Petition in IPR2016-01246 nor the Petition in IPR2016-01247
`
`describes how the fabrication processes disclosed in the prior art references could
`
`be combined to form the subject matter recited in the challenged claims. For
`
`example, neither Petition addresses the fact that to form a trench isolation,
`
`“planarization” of the substrate is necessary. Planarization removes material and
`
`evens out any irregular topography, making the wafer flat or planar. The primary
`
`references (Lee and Lowrey) each have structural features that will be disrupted
`
`and/or removed by planarization if a trench isolation is attempted to be formed,
`
`and the Petitions fail to describe how such a substitution would even be possible,
`
`let alone have been obvious. For at least this reason, neither Petition establishes a
`
`reasonable likelihood of unpatentability of any of the challenged claims. As such,
`
`both Petitions should be denied.
`
`B.
`
`Background
`
`Integrated circuits (ICs) are highly complex electrical systems located on a
`
`small microstructured silicon chip (Si chip). An integrated circuit can have
`
`millions of transistors that serve to process, store, and transport information.
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`Exhibit 2001, ¶33. The core element of an integrated circuit is the transistor,
`
`specifically the field-effect transistor (FET) that uses an electric field (“field
`
`effect”) in order to create charge carriers in the transistor’s channel region. The
`
`channel region connects the transistor’s source (S) with the transistor’s drain (D).
`
`The source and drain are separated by the gate (G) that controls the flow of charge
`
`in the channel between the source and drain. Exhibit 2001, ¶34.
`
`The transistor’s gate typically has a three-layer stack consisting of (top to
`
`bottom) a gate metal or metal-like material (M), a gate dielectric or oxide (O), and
`
`a semiconductor (S), thereby forming the MOS layer stack or gate layer stack.
`
`Accordingly, transistors based on the MOS layer stack are called MOSFETs.
`
`Exhibit 2001, ¶35. The circuit layout is the result of (i) the circuit functionality
`
`designed by design engineers and (ii) the designed circuit’s implementation on a Si
`
`IC chip fabricated by a processing sequence devised by process engineers. Exhibit
`
`2001, ¶37.
`
`The processing sequence takes place in a fabrication facility, also
`
`abbreviated as “fab” or “IC fab”, including a first group of fabrication processes
`
`called front end of line (FEOL) processes, and a second group of fabrication
`
`processes called back end of line (BEOL) processes. The FEOL processes include
`
`the fabrication of the transistors (MOSFETs) including the salicidation of source,
`
`gate, and drain. The BEOL processes include the fabrication of metal-based
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`interconnect lines and associated dielectric layers (interlayer dielectrics or ILDs)
`
`that electrically insulate the metal interconnects from each other. Exhibit 2001,
`
`¶38.
`
`IC processing requires (i) high spatial precision during lithography (to attain
`
`very small patterns) and (ii) cleanliness (to avoid contaminations). The processing
`
`of Si wafers proceeds in a strict sequence of processing steps (or processing
`
`modules) that are carefully chosen in sequence and content. Exhibit 2001, ¶40. For
`
`example, the gate stack of a transistor requires the availability of an Si substrate,
`
`followed by the deposition or growth of the gate dielectric (commonly an oxide),
`
`which in turn is followed by the deposition of the gate conductor. This processing
`
`sequence is fixed, and it would become ineffectual if altered. That is, certain
`
`elements of an IC may require the preexistence of other elements and rely on their
`
`presence for the proper functioning of the ensemble of elements. Exhibit 2001,
`
`¶¶40-41. For example, the source/drain dopant implant requires the presence of
`
`the gate so that the gate can mask the channel region from the implantation ion
`
`beam. That is, the gate enables the proper definition of the source/drain implanted
`
`regions. Such an implantation in which the source/drain regions are automatically
`
`aligned with the gate electrode is referred to as a “self-aligned implantation
`
`process.” Exhibit 2001, ¶41.
`
`A series of individual processing steps constitute a “processing module.” It
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`is generally not possible to reverse the sequence of processing steps within a
`
`module. Exhibit 2001, ¶42. For example, the formation of shallow trench isolation
`
`(STI) constitutes a processing module that involves the following processing steps:
`
`(i) trench etching, (ii) trench refill with silicon dioxide, and (iii) planarization.
`
`These steps are the major steps of the trench isolation module.1 Exhibit 2001, ¶42.
`
`Planarization is a process by which the top surface of the wafer is made flat
`
`or planarized. It can occur at various stages of the fabrication, and as is relevant
`
`here, it occurs after formation of the trench refill process. Exhibit 2001, ¶¶51-52.
`
`Each processing step (or processing module) is intended and is implemented
`
`for a specific initial configuration of the Si wafer. Each processing step (or
`
`processing module including a plurality of steps) transforms the Si wafer from an
`
`1 In addition to the major steps of trench formation, there are minor steps not
`
`mentioned above. A more complete series of steps employed for trench formation
`
`may include: oxide pad deposition; nitride pad deposition; resist coating; photo
`
`lithography; nitride etching; oxide etching; trench etching by means of a dry etch;
`
`resist strip; liner-oxide growth; trench refill with CVD silicon dioxide; annealing
`
`to improve quality of oxide; planarization by CMP (chemical mechanical
`
`planarization); and/or various cleaning steps and rinsing steps used throughout the
`
`module (major steps emphasized). Exhibit 2001, ¶43.
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`initial configuration to a final configuration associated with this specific
`
`processing step. Similarly, each processing module (with each processing module
`
`consisting of a sequence of multiple processing steps) transforms the Si wafer
`
`from an initial configuration to a final configuration associated with this specific
`
`processing module. Exhibit 2001, ¶¶45-46.
`
`When taking a specific processing step (within one processing module) out
`
`of its intended sequence and inserting it at another point in the sequence of
`
`processing steps, one must ensure the following:
`
`First, the sequence of processing steps preceding a specific processing step
`
`that is being inserted must provide an initial configuration compatible with the
`
`specific processing step. Second, the final configuration resulting from the specific
`
`processing step must be compatible with the subsequent processing step and
`
`beyond. Exhibit 2001, ¶47.
`
`In other words, given the initial and final configuration of an Si wafer, a
`
`specific processing step must be compatible with the overall fabrication process.
`
`As would be understood by a POSITA (as well as by an unskilled person with
`
`common sense), a random change in the sequence in processing steps may well not
`
`lead to the desired result. If such random change is implemented nonetheless, it
`
`would likely lead to a non-functioning IC device. Exhibit 2001, ¶48. Changing the
`
`sequence of processing steps requires that the fabrication process be re-engineered,
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`e.g., the entire front-end-of-line (FEOL) fabrication process may need to be re-
`
`engineered, which may lead to substantial changes in the fabrication of the Si IC
`
`device. Exhibit 2001, ¶48.
`
`The same principle discussed above for processing steps also applies to the
`
`sequence of processing modules. When taking a specific processing module out of
`
`its intended sequence and inserting it at another point in the sequence of processing
`
`modules, one must ensure the following:
`
`First, the sequence of processing modules preceding a specific processing
`
`module that is being inserted must provide an initial configuration compatible with
`
`the specific processing module. Exhibit 2001, ¶49. Second, the final configuration
`
`resulting from the specific processing module must be compatible with the
`
`subsequent processing module and beyond. Exhibit 2001, ¶49.
`
`The same conclusion that was drawn above for a specific processing step
`
`can be drawn for a specific processing module. As would be understood by a
`
`POSITA (as well as by an unskilled person having common sense), a random
`
`change in the sequence of processing modules would not lead to the desired result.
`
`If such a change were implemented nonetheless, it would in all likelihood lead to a
`
`non-functioning IC device. Exhibit 2001, ¶50.
`
`Planarization must be performed at a specific point in the sequence of the
`
`fabrication process. Petitioner’s Dr. Banerjee declaration (Exhibit 1004) never
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`addresses the planarization process (e.g. the CMP process) that is inextricably
`
`associated with STI. He never once acknowledges the process re-design and re-
`
`engineering which would be necessary when combining the pairs of prior art
`
`references to create a trench isolation involving planarization. Dr. Banerjee’s
`
`declaration gives no consideration how and whether the planarization process
`
`could be made to work on a non-planar surface topology of a wafer. The
`
`implementation of the STI process on a wafer having a non-planar surface
`
`topology will generally result in a non-functioning IC device unless the fabrication
`
`process is comprehensively re-engineered. Exhibit 2001, ¶69. Dr. Banerjee never
`
`says how this could be done while still achieving the final structure recited in the
`
`challenged claims of the ’174 patent.
`
`Dr. Banerjee’s declaration never addresses whether it would even be
`
`possible to fabricate the combinations of the elements that he proposes would be
`
`obvious to combine. He asserts in a conclusory fashion that such fabrication
`
`would be obvious without providing an appropriate analysis of how the fabrication
`
`could be accomplished, if it could be accomplished at all. Exhibit 2001, ¶¶54-55.
`
`Integrated circuit fabrication is highly complex, and it is certainly no
`
`coincidence that every prior art reference upon which Petitioner relies, as well as
`
`the ‘174 patent itself, provides an extensive sequence of detailed fabrication
`
`process steps including relevant engineering details. It is precisely this type of
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`critical information which would be needed to establish obviousness in this
`
`complex technology and which Petitioner has elected not to provide to show how
`
`and whether the proposed combinations could ever be achieved. Exhibit 2001,
`
`¶53. As a matter of law the Petition is insufficient.
`
`C.
`
`The Premise Of The Petitioner’s Argument Is Legally Insufficient
`
`Petitioner asserts that “Lee teaches every limitation of the challenged claims
`
`except trench isolation.” Petition, p. 21. Petitioner devotes a great deal of effort
`
`attempting to explain that although Lee does not teach or disclose STI, a POSITA
`
`would have understood that Noble’s or Ogawa’s STI was a known substitute for
`
`Lee’s LOCOS isolation. Petition, pp. 21, 70.
`
`LOCOS isolation refers to the selective local oxidation of a silicon substrate
`
`to form an isolation region. Exhibit 2001, ¶58. Trench isolation, such as shallow
`
`trench isolation (STI) involves selectively etching a substrate to form trenches
`
`which are subsequently filled with an insulating material followed by planarization
`
`of the wafer. Exhibit 2001, ¶¶59-63.
`
`The Petition fails to address the fact that when combining references relating
`
`to semiconductor devices, the process (“process sequence”) by which the
`
`integrated circuit (IC) devices are formed is inseparable from their final structure
`
`as claimed. Exhibit 2001, ¶78. As such, simply substituting a component from one
`
`device, e.g., STI, for a different component in another device, e.g., LOCOS
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`isolation, can provide unworkable results, both in terms of how the substituted
`
`component cooperates with other components, and how the changed
`
`manufacturing sequence, which is required to effectuate such substitution, can be
`
`implemented. Exhibit 2001, ¶78. This is particularly true for Si ICs where a single
`
`film can serve multiple purposes, and where a multitude of different functional
`
`features are condensed into a minimum number of layers and processing steps.
`
`Exhibit 2001, ¶78.
`
`Petitioner’s obviousness arguments simply swap out the LOCOS isolation
`
`(Lee) for the STI (Noble and Ogawa) without describing how such a substitution
`
`could be accomplished and without giving due consideration to the strong
`
`interconnectedness and interdependency of the Si IC fabrication process. A
`
`LOCOS isolation is formed using a very different process sequence than the
`
`process sequence used to form an STI. Exhibit 2001, ¶79. To produce an operative
`
`device, their very different respective fabrication processes must be merged,
`
`integrated, and made compatible with their respective gate stack and interconnect
`
`stack fabrication processes. If this is not possible, a merged structure will not be
`
`possible. Exhibit 2001, ¶79.
`
`Petitioner never once addresses how and when Noble’s and Ogawa’s STI
`
`can be substituted in for Lee’s LOCOS isolation. Indeed, it would have been
`
`apparent to a POSITA at the time of invention that the incompatible process
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`sequences for forming the STI disclosed in Noble or Ogawa would not have been
`
`substitutable for the LOCOS isolation of Lee, and as such, there would have been
`
`no motivation for the POSITA to substitute the LOCOS isolation of Lee with the
`
`STI of Noble or Ogawa. Exhibit 2001, ¶80.
`
`Petitioner’s expert Dr. Banerjee barely addresses the issue. For example, Dr.
`
`Banerjee baldly states:
`
`replacing Lee’s LOCOS with Ogawa’s trench would have been
`entirely compatible and had no impact on the processes used for
`
`gate formation, silicide formation, and any other aspect of the
`
`claims.
`
`Exhibit 1004, ¶198.
`
`No citation is provided for this baseless statement. This mistaken and
`
`unsupported assertion seems to form the entire basis for the asserted combination.
`
`Dr. Banerjee further states:
`
`Other references further demonstrate that replacing Lee’s
`LOCOS with Ogawa’s trench isolation would have constituted
`a simple substitution of one known element for another
`
`according to known methods to achieve predictable results.
`
`Exhibit 1004, ¶201.
`
`Again, this statement is unsupported.
`
`Incompatibility and unworkability negate any motivation to modify Lee by
`
`replacing its LOCOS isolation with Noble’s or Ogawa’s STI. This lack of
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`12
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`Case IPR2016-1246
`U.S. Patent No. 7,126,174
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`motivation renders Lee ineffective as the starting point of a validity challenge of
`
`the claims of the ‘174 patent, and any resulting combination of references is legally
`
`insufficient to justify initiating inter partes review of the ‘174 patent.
`
`III. RELEVANT CASE LAW
`
`A.
`
`There Must Be A Likelihood Of Invalidity
`
`Inter partes review shall not be instituted for a ground of unpatentability
`
`unless the Board decides that the petition supporting the ground would demonstrate
`
`that there is a reasonable likelihood that at least one of the claims challenged in the
`
`petition is unpatentable. 37 C.F.R. §42.108.
`
`B.
`
`The Burden Of Persuasion
`
`The Petition must demonstrate that there is a reasonable likelihood that at
`
`least one of the claims challenged in the petition is unpatentable. 37 C.F.R.
`
`§42.108. “The burden of persuasion is on the Petitioner to establish the
`
`unpatentability of the claims, and that burden never shifts.” In Re: Magnum Oil
`
`Tools International, Ltd., 119 U.S.P.Q.2D 1541, 1548 (Fed. Cir. 2016).
`
`“In an inter partes review, the burden of persuasion is on the petitioner to
`
`prove ‘unpatentability by a preponderance of the evidence,’ 35 U.S.C. § 316(e),
`
`and that burden never shifts to the patentee.” Dynamic Drinkware, LLC v. Nat'l
`
`Graphics, Inc., 800 F.3d 1375, 1378 (Fed. Cir. 2015). Indeed, “the Supreme Court
`
`has never imposed nor even contemplated a formal burden- shifting framework in
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`13
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`Case IPR2016-1246
`U.S. Patent No. 7,126,174
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`the patent litigation context.” In Re: Magnum Oil Tools International, Ltd., 119
`
`U.S.P.Q.2D (BNA) 1541, 1548 (Fed. Cir. 2016).
`
`C.
`
`The Petitioner Bears The Burden Of Establishing A Rationale For
`Combining The Prior Art
`
`The test is “whether ‘a skilled artisan would have been motivated to
`
`combine the teachings of the prior art references to achieve the claimed
`
`invention.’” Pfizer, Inc. v. Apotex, Inc., 480 F.3d 1348, 1361 (Fed. Cir. 2007);
`
`Allied Erecting and Dismantling Co., Inc. v. Genesis Attachments, LLC, 825 F.3d
`
`1373, 1381 (Fed. Cir. 2016).
`
`“To satisfy its burden of proving obviousness, a petitioner cannot employ
`
`mere conclusory statements. The petitioner must instead articulate specific
`
`reasoning, based on evidence of record, to support the legal conclusion of
`
`obviousness.” In Re: Magnum Oil Tools International, Ltd., 119 U.S.P.Q.2D 1541,
`
`1552 (Fed. Cir. 2016).(emphasis added).
`
`“The PTAB’s conclusory assertion that Figure 5 of Jacobson ‘appears to’
`
`support its finding does not equate to the reasoned explanation needed to support it
`
`conclusion.” Synopsys, Inc. v. Mentor Graphics Corp., 814 F.3d 1309, 1322 (Fed.
`
`Cir. 2016); see also In re Lee, 277 F.3d 1338, 1345 (Fed. Cir. 2002) (“The [PTAB]
`
`cannot rely on conclusory statements when dealing with…prior art and specific
`
`claims, but must set forth the rationale on which it relies.”) (emphasis added); In re
`
`14
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`Case IPR2016-1246
`U.S. Patent No. 7,126,174
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`Warsaw Orthopedic, Inc., 2016 U.S. App. LEXIS 14560, *18 (Fed. Cir. 2016);
`
`Arendi S.A.R.L. v. Apple Inc., No. 2015-2073, 2016 WL 4205964, *9 (Fed. Cir.
`
`Aug. 10, 2016) (“reversing the PTAB’s determination [...] because the PTAB’s
`
`decision was ‘conclusory and unsupported by substantial evidence’”); In re
`
`Giannelli, 739 F. 3d 1375, 1380 (Fed. Cir. 2014) (“reversing affirmance of
`
`examiner’s rejection where the PTAB analysis ‘contained no explanation why or
`
`how a person having ordinary skill in the art would modify’ the prior art to arrive
`
`at the claimed invention”). In re: Lemay, 2016 U.S. App. LEXIS 17041, *5 (Fed.
`
`Cir. 2016) (emphasis added).
`
`D.
`
`The PTO is Bound by Record Arguments Petitioner has Made
`
`“We find no support for the PTO’s position that the Board is free to adopt
`
`arguments on behalf of petitioners that could have been raised, but were not raised
`
`by the petitioner during an IPR. Instead, the Board must base its decision on
`
`arguments that were advanced by a party, and to which the opposing party was
`
`given a chance to respond”.
`
`In Re: Magnum Oil Tools International, Ltd., 119
`
`U.S.P.Q.2D 1541, 1552 (Fed. Cir. 2016). The PTAB’s “authority is not so broad
`
`that it allows the PTO to raise, address, and decide unpatentability theories never
`
`presented by the petitioner and not supported by record evidence.” Id.1553.
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`15
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`Case IPR2016-1246
`U.S. Patent No. 7,126,174
`
`IV. THE CLAIMED INVENTION OF THE ‘174 PATENT
`
`The ‘174 patent is directed to a semiconductor device comprising a trench
`
`isolation surrounding an active area of a semiconductor substrate. A gate
`
`insulating film is formed over the active area, and a gate electrode is formed over
`
`the gate insulating film. First L-shaped sidewalls are formed over the side surfaces
`
`of the gate electrode with first silicide layers formed on regions located on the
`
`sides of the first L-shaped sidewalls within the active area an interconnection
`
`formed on the trench isolation. Second L-shaped sidewalls are formed over the
`
`side surfaces of the interconnection.
`
`The ‘174 patent contains 21 figures. Figures 17-21 are identified as prior
`
`art, and are contrasted with Figures 1-16 which illustrate various embodiments of
`
`the invention. Trench isolation appears both in the prior art Figures and the
`
`Figures of the invention such that it is apparent that the inclusion of trench
`
`isolation per se was never portrayed as being something new or unique to the ‘174
`
`patent.
`
`The claims are exemplified in Figure 15(f)2 (colorized and annotated):
`
`2 The claims are not to be construed as being limited to only the embodiment
`
`shown in this Figure.
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`16
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`Case IPR2016-1246
`U.S. Patent No. 7,126,174
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`Fig. 15(f) above illustrates a semiconductor device comprising a trench
`
`isolation (blue) surrounding an active area of a semiconductor substrate; a gate
`
`insulating film formed over the active area (blue); a gate electrode formed over the
`
`gate insulating film (pink); first L-shaped sidewalls formed over the side surfaces
`
`of the gate electrode (green); first silicide layers formed on regions located on the
`
`sides of the first L-shaped sidewalls within the active area (dark pink); an
`
`interconnection formed on the trench isolation (pink); and second L-shaped
`
`sidewalls formed over the side surfaces of the interconnection (green). As is clearly
`
`seen silicide layers are located on the sides of the L-shaped sidewalls within the
`
`active area.
`
`A complicated and intricate process is necessary to fabricate the device
`
`shown Fig. 15(f). Thus, referring to the ‘174 specification, it is seen that Fig. 15(f)
`
`is identified as Embodiment 10. Exhibit 1001, 26:35 e