(12)
`
`United States Patent
`Young
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 7,074,709 B2
`Jul. 11, 2006
`
`US007074709B2
`
`(54) LOCALIZED DOPING AND/OR ALLOYING
`01: METALLIZATION FOR INCREASED
`INTERCONNECT PERFORMANCE
`
`7/2002 Farrar ...................... .. 438/652
`6,420,262 B1
`6/2002 Marieb et a1.
`2002/0076925 A1
`2003/0203617 A1 * l0/2003 Lane et a1. ............... .. 438/627
`
`(75) Inventor: Bradley Scott Young, Irving, TX (US)
`
`(73) Assignee: Texas Instruments Incorporated,
`Dallas, TX (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U'S'C' 154(1)) by 258 days'
`
`(21) APP1- NOJ 10/288s974
`(22) Filed
`NOV 6 2002
`'
`l
`a
`Prior Publication Data
`Us 200 4 /000221 1 Al Jan‘ 1, 2004
`
`(65)
`
`I Related US. Application Data
`I
`(60) Pr0v1s10nal applicatlon No. 60/392,715, ?led on Jun. 28,
`2002'
`(51) Int_ CL
`[1011, 21/4763
`H01L 21/44
`
`(200601)
`(2006.01)
`
`(52) US. Cl. ..................... .. 438/625; 438/626; 438/638;
`438/654; 438/687
`(58) Field of Classi?cation Search ............... .. 438/ 625,
`438/626, 638, 654, 687; 385/100, 135, 136,
`385/ 137, 123; 242/159, 47, 176
`See application ?le for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,955,688 A * 9/1990 Chapin et a1. ............ .. 385/123
`4,995,698 A * 2/1991 Myers .................. .. 385/147
`5,221,060 A * 6/1993 Couvillion et a1. ....... .. 242/159
`5,594,829 A * 1/1997 LoStracco et a1. ........ .. 385/134
`5,822,065 A * 10/1998 Market a1. ............... .. 356/465
`6,023,100 A
`2/2000 Tao et a1.
`6,268,291 B1
`7/2001 Andricacos et 31.
`6,376,353 B1 * 4/2002 Zhou et a1. ............... .. 438/612
`6,387,806 B1 * 5/2002 Wang et a1. .............. .. 438/687
`
`FR
`JP
`W0
`W0
`
`FOREIGN PATENT DOCUMENTS
`2816758 A1
`5/2002
`2000150522
`5/2000
`W0 0197283 A 12/2001
`W0 0245142
`6/2002
`
`OTHER PUBLICATIONS
`C. P. Wang et al., Binary cuialloy layersfor cuiintercon
`nections reliability improvement (3 pp.).
`E. T. OgaWa et al., Stressilnduced Voiding Under Was
`Connected To Wide Cu Metal Leads (10 pp.).
`Development of electroless copper metallisation, [online]
`Retrieved from the Internet:<URL: http://WWW.hut.?/Units/
`Electron/Research/res2000/ElectrolessCu/electrolessicop
`per.html (3 pp.).
`* Cited by examiner
`
`Primary Examineriwilliam M. Brewster
`(74) Attorney, Agent, or Firmilacqueline J. Garner; W.
`James Brady, III; Frederick J. Telecky, Jr.
`(57)
`ABSTRACT
`
`Methods and compositions are disclosed for modifying a
`semiconductor interconnect layer to reduce migration prob
`lems While minimizing resistance increases induced by the
`modi?cations. One method features creating trenches in the
`interconnect layer and ?lling these trenches With composi
`tions that are less susceptible to migration problems. The
`trenches may be ?lled using traditional vapor deposition
`methods, or electroplating, or alternately by using electro
`less plating methods. Ion implantation may also be used as
`another method in modifying the interconnect layer. The
`methods and compositions for modifying interconnect lay
`ers may also be limited to the via/interconnect interface for
`improved performance. Athin seed layer may also be placed
`on the semiconductor substrate prior to applying the inter
`connect layer. This seed layer may also incorporate similar
`dopant and alloying materials in the otherwise pure metal.
`
`17 Claims, 3 Drawing Sheets
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`....... .,
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`Page 1 of 10
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`Sheet 1 of3
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`US 7,074,709 B2
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`FIG. 2
`(PRIORART)
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`FIG. 5
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`FIG. 6
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`Page 4 of 10
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`US 7,074,709 B2
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`1
`LOCALIZED DOPING AND/OR ALLOYING
`OF METALLIZATION FOR INCREASED
`INTERCONNECT PERFORMANCE
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is entitled to the bene?t of a provisional
`patent application Ser. No. 60/392,715 ?led Jun. 28, 2002.
`
`STATEMENT REGARDING FEDERALLY
`SPONSORED RESEARCH OR DEVELOPMENT
`Not applicable.
`
`BACKGROUND OF THE INVENTION
`
`1. Technical Field of the Invention
`The present invention generally relates to semiconductor
`processing techniques. More particularly, the present inven
`tion relates to selective modi?cation of the interconnects of
`an integrated circuit to achieve improved mechanical and
`electrical properties.
`2. Description of Related Art
`The semiconductor technology central to the modern
`integrated circuit (“IC”) has been developing for over a
`century. In the late nineteenth century, the special properties
`of the semiconductor selenium Were ?rst observed and
`recogniZed. The ?eld of semiconductor physics advanced
`rapidly and the ?rst transistor Was proposed in the 1930s.
`HoWever, not until the late 1940s Was a functional point
`contact transistor constructed. The IC, Which employs a
`plurality of circuit elements in a monolithic semiconductor
`substrate rather than using discrete components, Was ?rst
`developed in the late 1950s by Jack Kilby at Texas
`Instruments, Inc. and by Robert Noyce at Fairchild Semi
`conductor Corporation.
`Since the late 1950s, IC technology has evolved rapidly
`and has revolutioniZed virtually every industry and capacity
`in Which ICs are used. Today’s ICs frequently employ
`hundreds of thousands or even millions of transistors and
`highly complex, multi-layered architectures. The prolifera
`tion of electronics in general, and ICs in particular, has
`resulted in large part from the ability to increase circuit
`functionality While simultaneously reducing device cost and
`siZe. An important catalyst for these improvements has been
`advances in semiconductor processing technologies.
`Although a Wide array of semiconductor companies and
`products exist, for the most part, semiconductor processing
`is completed through a series of common steps. Semicon
`ductor processing begins With a Wafer or substrate, upon
`Which various processing techniques are used to construct
`circuit elements such as transistors, resistors and capacitors.
`The formation of circuit elements comprises a process called
`dopingiie, deliberately introducing impurities into certain
`regions of the monolithic crystalline substrate. After the
`circuit elements are formed, a series of conductive and
`insulating layers are used to form connections, called
`interconnects, betWeen the appropriate circuit elements.
`As increasingly complex ICs utiliZe an increasing number
`of circuit elements, more electrical interconnects betWeen
`circuit elements and a greater number of conductor-insulator
`layers are required. A chief objective of semiconductor
`processing is the minimiZation of interconnect electrical
`resistance. Increased resistance is undesirable because as the
`interconnect resistance betWeen tWo electrical devices
`increases, so too does the amount of time it takes a signal to
`propagate betWeen the devices. This, in turn, decreases the
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`overall speed at Which the IC functions. Additionally,
`increased resistance also increases the amount of overall
`poWer consumed by the IC.
`Another important consideration is the mechanical stabil
`ity of the interconnects, Which is negatively impacted by a
`phenomenon knoWn as electromigration, the migration of
`atoms in the interconnect induced by applying an electric
`potential across the interconnect. The principle of electromi
`gration is depicted graphically in FIGS. 1A, 1B and 2. FIG.
`1A shoWs an electron How 14 in a conductor 10 due to a
`potential di?‘erence supplied by a battery 12. The momen
`tum of the electrons in the electron How 14 causes atoms in
`the conductor 10 to migrate in the same direction as the
`electron How 14. Grain boundaries occur at the intersection
`betWeen tWo crystalline grains. The intersection of three or
`more crystalline grains may be susceptible to electromigra
`tion. Consequently, grain boundary 16 and intersection point
`18 are likely places for electromigration damage, but usually
`at higher activation energy than surface dilfusion in the case
`of Cu metalliZation.
`FIG. 1B shoWs electron How 14 through grain boundary
`intersection points 18A and 18B. In intersection point 18A,
`electron How 14 from tWo grains is merging into a single
`grain, resulting in the formation of void 20. In intersection
`point 18B, in contrast, electron How 14 from a single grain
`is diverging into two different grains, resulting in the for
`mation of hillock 21.
`Conductors are often processed using aluminum With a
`small concentration (i.e., less than about 2% by Weight), of
`Copper (“Cu”). More recently, pure Cu has been the metal
`of choice for producing metal interconnect on ICs. To
`contain the Cu and keep it from entering and moving Within
`the glass dielectric layers and the active areas of the
`substrate, barrier layers surround the Cu. These barriers are
`carefully chosen so as to not cause adhesion problems
`betWeen the metalliZation and the encapsulating/insulating
`dielectric layers. With the advancement of technology, neW
`materials are sought to reduce parasitic capacitance and
`resistance for greater circuit performance and loWer poWer
`consumption. These neW materials possess loWer dielectric
`constants but also loWer thermal conductance. This reduces
`the ef?ciency With Which heat is transferred to the substrate.
`Also, these material are more brittle and mechanically less
`robust than the more traditional silicone dioxide. LoWer
`mechanical strength means less resistance to cracking and
`possibly a greater tendency toWard electromigration, due to
`tensile forces on the metalliZation or loWer strength in
`general. The surface betWeen the Cu lead and the barrier is
`observed to be a path for metal movement of relatively loW
`activation energy. Voids can nucleate and/or groW at this
`surface, and the other interfacial surfaces. Metal Will
`electromigrate, that is, drift or dilfuse in the direction of
`electron ?oW under electrical bias. Voids, depletion of metal
`in an area, can form near the electron source. These voids are
`usually paired doWnstream With hillocks, an accumulation
`of metal. Hillocks can cause the formation of metal ?laments
`into the dielectric, that is, unWanted paths of current leakage,
`and even cracking of the barrier and/or dielectric.
`The impact on circuit performance of void 20 and hillock
`21 in FIG. 1 is depicted graphically in FIG. 2. FIG. 2 shoWs
`interconnect 23 and parallel interconnect 24, Which is desir
`ably electrically isolated from interconnect 23. Proper cir
`cuit performance requires not only high electrical conduc
`tance along interconnect 23 and interconnect 24 but a high
`electrical resistance betWeen them. Void 20 and hillock 21
`can impact both the electrical conductance along a single
`interconnect and the electrical resistance betWeen tWo dif
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`Page 5 of 10
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`US 7,074,709 B2
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`3
`ferent interconnects. For example, void 20 in interconnect
`23 can signi?cantly decrease the electrical conductance
`along interconnect 23. Similarly, hillock 21 can create a
`short betWeen interconnect 23 and interconnect 24, thereby
`destroying the electrical isolation betWeen the tWo intercon
`nects.
`Voids can also arise from stress. Interconnects frequently
`abut adjacent layers formed at different temperatures. For
`example, a copper interconnect deposited at room tempera
`ture may adjoin a carbide layer formed at around 4000 C.,
`thereby causing an inherent stress. Tensile stresses in the
`interconnect tend to pull the interconnect material apart
`(causing voids) as the interconnect changes temperatures,
`further exacerbating migration problems. This effect is more
`prevalent at the interface betWeen adjacent layers.
`Furthermore, this stress voiding at the interfacial surfaces is
`even more problematic at elevated temperatures and/or
`under heavy current ?oW.
`Until recently, aluminum Was the interconnect conductor
`of choice in IC processing. The popularity of aluminum
`stemmed from a variety of factors. First, techniques for
`depositing thin aluminum ?lms are Well established.
`Second, because aluminum can be etched effectively in
`chlorine plasmas, the formation of patterned aluminum ?lms
`is relatively straightforward. Unfortunately, though, alumi
`num interconnects have several drawbacks. First, from an
`electrical perspective, aluminum is relatively poor conductor
`relative to other metals. Consequently, aluminum negatively
`impacts circuit speed and poWer usage. Second, from a
`mechanical perspective, aluminum is particularly suscep
`tible to structural problems resulting from electromigration
`and stress. For years, the semiconductor industry has been
`moving aWay from aluminum metalliZation. Initial e?forts
`included adding trace amounts of copper to the aluminum,
`because the copper had a loWer resistivity and Was less
`susceptible to electromigration. With each successive gen
`eration of ICs more copper Was added.
`Currently, the semiconductor industry is transitioning to
`pure4or relatively pureicopper as the electrical conductor
`of choice for establishing interconnections betWeen circuit
`elements. Copper has a signi?cantly higher conductivity
`than aluminum and is inherently more resistant to electromi
`gration. Procedures such as chemical mechanical polishing
`(“CMP”) are facilitating the shift to copper metalliZation. In
`general, CMP involves planariZing surface layers that have
`been deposited on a semiconductor Wafer.
`While the shift to copper interconnects has alleviated
`some of the problems associated With aluminum
`metalliZation, it has not eliminated them. Although less
`susceptible, copper also suffers from electrically-induced
`and stress-induced migration problems. Electromigration
`problems With copper Were recently discussed in “Binary
`Cu-Alloy Layers for Cu-Interconnections Reliability
`Improvement” by Connie P. Wang et al. (hereinafter
`“Wang”). According to Wang, current techniques for dealing
`With electromigration problems in copper interconnects
`include the use of copper alloys that exhibit improved
`structural stability over pure copper. In general, Wang’s
`approach involves selecting copper alloys, rather than
`copper, to ?ll the interconnect trench. Because copper alloys
`frequently exhibit increased electrical resistance to current
`?oW, Wang focused on those copper alloys possessing
`suitably loW electrical resistance. Using this criteria, Wang
`limited the copper alloy materials to CuSn, CuIn, and CuZr,
`for Which the additional sheet resistance ranges from l.l*l 8
`uQ-cm.
`The use of copper alloys rather than copper creates
`several problems. First, copper interconnects comprised
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`entirely of these copper alloys (e.g., CuSn, CuIn, CuZr, etc.)
`exhibit larger sheet resistances than pure copper intercon
`nects. This added electrical is especially problematic for
`long thin metal interconnects.
`Second, the copper alloys disclosed by Wang are not
`conventionally used in other manufacturing steps.
`Consequently, these materials raise process integration
`issues and likely Would lead to signi?cantly increased manu
`facturing costs.
`A need still exists for improved copper metalliZation that
`possesses improved mechanical stability Without increased
`electrical resistance.
`
`BRIEF SUMMARY OF THE PREFERRED
`EMBODIMENTS
`The preferred embodiments of the present invention
`involve modi?cations to the interconnects that enhance their
`mechanical stability. Unlike the disclosure of Wang,
`hoWever, the surface of the interconnect is modi?ed rather
`than the bulk interconnect. Consequently, the interconnect
`bene?ts from the mechanical stability of a robust modi?ed
`exoskeleton While retaining the electrical properties of the
`unmodi?ed interconnect material.
`According to one preferred embodiment of the present
`invention, an interconnect layer is modi?ed by implanting
`ions in the vicinity of the via/interconnect interface. After
`the interconnect is deposited and planariZed by CMP, an ion
`implantation step is performed in the area patterned by a
`mask. Preferably, the mask restricts ion implantation to the
`vicinity of the interconnect/via interface. In one embodiment
`the interconnect is copper and the chemical species intro
`duced is selected from the group consisting of arsenic,
`antimony, chromium, palladium, tin, magnesium,
`aluminum, cobalt, and Zirconium, and combinations thereof.
`Preferably, modi?cation depth varies betWeen about 50 and
`500 Angstroms and the composition of chemical species in
`this depth range vanes betWeen about 0.1 and about 10
`percent by Weight.
`According to another preferred embodiment of the present
`invention, an alloy layer is deposited on top of an intercon
`nect after a trench has been formed in the interconnect
`(possibly by etching). In using an etch step, the etch step
`may be selectiveii.e., con?ned to a speci?c area in the
`vicinity of the interconnect/via interfaceior may apply
`generally to the entire interconnect. The trench may also be
`formed in the interconnect layer by using over-polishing
`during a CMP step. In one embodiment, interconnect is
`copper, and the alloy layer is a copper alloy comprising
`copper and a material selected from the group consisting of
`arsenic, antimony, chromium, palladium, tin, magnesium,
`aluminum, cobalt, and Zirconium, or combinations thereof.
`Preferably, the thickness of alloy layer, or the depth of the
`trench in interconnect, varies betWeen 50 and 500
`Angstroms, and the percent composition of the material
`added to the copper varies betWeen about 0.1 and about 10
`percent by Weight.
`Various techniques exist for depositing the alloy layer.
`One embodiment includes electroless plating, Where metal
`deposition occurs through a chemical reduction reaction
`from an aqueous metal salt solution, Which also contains a
`reducing agent. The semiconductor Wafer is immersed in a
`plating bath, Wherein metal ions react With reducing agents
`on a catalytic surface, thereby enabling selective plating on
`interconnects that are electrically isolated.
`Other preferred embodiments for depositing alloy layer
`include vapor deposition techniques such as Chemical Vapor
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`5
`Deposition (“CVD”) and Physical Vapor Deposition
`(“PVD”). These techniques are referred to as gross deposi
`tion techniques because there is no selectivity of deposition
`and a ?lm of the material to be deposited forms over the
`Whole surface of the Wafer. Accordingly, one embodiment
`that uses vapor deposition techniques to form the alloy layer
`may involve a CMP step after depositing the alloy layer in
`order to maintain electrical isolation betWeen interconnects.
`Another method of maintaining electrical isolation betWeen
`interconnects While using vapor deposition techniques
`includes employing a mask to limit the deposition of the
`desired material to only the exposed interconnect layers.
`More particularly, the mask may limit the deposition of the
`desired material to the vicinity of the interconnect/via inter
`face.
`Another embodiment of the present invention involves
`selective application of a thin seed layer, on the order of
`about 10 to 50 Angstroms thick, in the trench prior to
`application of an interconnect layer. In this manner, the Walls
`of the trench are coated With the thin seed layer. In one
`embodiment, the interconnect is copper and thin seed layer
`is a copper alloy comprising copper and a material selected
`from the group consisting of arsenic, antimony, chromium,
`palladium, tin, magnesium, aluminum, cobalt, and Zirco
`nium and combinations thereof Preferably, the deposition of
`alloy layer is accomplished using the selective electroless
`plating techniques described above. Another embodiment
`includes depositing the alloy layer using atomic layer
`groWth methods.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`For a more detailed description of the present invention,
`reference Will noW be made to the accompanying draWings,
`Wherein:
`FIG. 1A shoWs a conductor including grain boundaries;
`FIG. 1B shoWs grain boundary intersection points;
`FIG. 2 shoWs possible failure modes resulting from
`atomic migration;
`FIG. 3A shoWs a single damascene structure;
`FIG. 3B shoWs a dual damascene structure;
`FIG. 4 shoWs modifying an interconnect layer using ion
`implantation;
`FIG. 5 shoWs modifying an interconnect layer by ?lling a
`trench; and
`FIG. 6 shoWs modifying an interconnect layer by apply
`ing a thin seed layer.
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`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS
`The preferred embodiments of the present invention stem
`from the realiZation that interconnect mechanical stability
`can be increasediand, therefore, interconnect susceptibility
`to electromigration and stress migration decreasediWithout
`compromising interconnect electrical conductivity by selec
`tively modifying the periphery of the individual metal lead.
`The modi?ed periphery limits void and hillock formation
`While the inner core of the interconnect serves as a high
`conductance pathWay for current ?oW. As Would be evident
`to a person of ordinary skill, numerous methods exist for the
`selective modi?cation of interconnects. Therefore, Without
`limiting the scope of the present invention, some preferred
`embodiments involve modi?cation of the interconnect
`periphery selectively implanting or diffusing one or more
`desired chemical species into the exterior surface of an
`interconnect. According to some other preferred embodi
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`ments of the present invention, the modi?ed periphery is
`generated by depositing one or more chemical species onto
`the exterior surface of an interconnect.
`The preferred embodiments of the present invention are
`generally applicable to interconnects in any type of inte
`grated circuit processing and construction. Therefore, With
`out limiting the scope of the invention, the preferred
`embodiments involve modi?cations to a CMP process for
`damascene construction.
`Damascene Construction
`Damascene interconnect construction derives its name
`from the ancient artisans of Damascus, Who created intricate
`patterns using metal inlays. Akin to its ancient origins,
`damascene construction in semiconductor processing cre
`ates interconnect lines by etching a recess or trench in a
`planariZed insulator layer, ?lling the trench With a
`encapsulating/containment barrier metal and the lead metal
`(e.g., aluminum or copper), and then removing excess metal
`material by planariZation to yield a damascene structure.
`FIGS. 3A and 3B shoW cross sections of an IC employing
`damascene construction. FIG. 3A shoWs “single damascene”
`construction Whereas FIG. 3B shoWs “dual damascene”
`construction.
`FIG. 3A depicts a semiconductor substrate 25 having
`disposed thereon patterned insulator and interconnect layers.
`Inter-layer dielectric (“ILD”) 26 contacts semiconductor
`substrate 25 and provides electrical insulation betWeen semi
`conductor substrate 25 and ?rst interconnect 30. Barrier
`layer 28 limits diffusion of chemical species betWeen ILD 26
`and ?rst interconnect 30. Capping layer 32, typically an
`insulator, covers ILD 26 and ?rst interconnect 30 except
`Where via 34 and barrier layer 36 connect ?rst interconnect
`30 to second interconnect 38. ILD 35 provides additional
`electrical isolation betWeen ?rst interconnect 30 and second
`interconnect 38. Capping layer 40 provides both electrical
`isolation and surface protection to the completed integrated
`circuit.
`Damascene construction typically begins With semicon
`ductor substrate 25. ILD 26 is deposited on semiconductor
`substrate 25 and planariZed using CMP. Numerous materials
`can be employed effectively as ILDs in semiconductor
`processing. Therefore, Without limiting the scope of the
`present invention, the preferred embodiments of the present
`invention employ silica-containing materials such as orga
`nosilica glasses or doped silica such as ?uorine-doped silica
`glasses.
`After planariZation of the ILD 26, a trench is etched in
`ILD 26 and a barrier layer 28 is deposited in the trench
`folloWed by ?rst interconnect 30. In general, barrier layers
`serve to hinder the metal (e.g., copper) from diffusing into
`adjacent ILDs. The material deposited to form barrier layer
`28 generally depends on the chemical composition of the
`interconnect. For example, When ?rst interconnect 30 com
`prises tungsten (W), barrier layer 28 typically comprises
`titanium (Ti)ie.g., Ti, titanium nitride (TiN), or a Ti/TiN
`stack. HoWever, When ?rst interconnect 30 comprises cop
`per (Cu), barrier layer 28 typically comprises tantalum
`(Ta)4e.g., Ta, tantalum nitride (TaN) or a Ta/TaN stack.
`According to one preferred embodiment, ?rst interconnect
`30 comprises copper and barrier layer 28 comprises Ta or
`TaN or Ta/TaN bilayer, and possibly another layer to
`increase adhesion betWeen the TaN and the dielectric.
`FolloWing the application of the barrier layer 28, ?rst
`interconnect 30 is deposited and then planariZed using CMP.
`As mentioned above, metal interconnects typically comprise
`aluminum or copper but may be any material, including
`metal alloys, that exhibit satisfactory electrical and mechani
`cal properties.
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`7
`Capping layer 32 preferably is deposited on ?rst inter
`connect 30 and ILD 26 following planariZation. Capping
`layer 32 typically comprises an insulating capping ?lm,
`silicon nitride or silicon carbide, and may be patterned using
`photolithography techniques so as to leave an opening for
`via 34. As shoWn in FIG. 3A, via 34 may be surrounded by
`barrier layers. Via 34 may comprise the same type of metal
`used in ?rst interconnect 30 or may be a different material
`altogether.
`ILD layer 35 (Which may or may not be of the same
`composition as ILD 26) is then deposited on top of capping
`layer 32, and preferably is further patterned (or etched) to
`alloW for via 34, barrier layer 36, and second interconnect
`38. The patterning step for ILD 35 and the patterning step for
`capping layer 32 may be combined in order to speed up
`fabrication time. The composition of barrier layer 36, like
`barrier 28, is typically selected based upon the materials
`surrounding it (i.e., via 34), and may therefore comprise the
`same material as barrier 28 described above.
`Second interconnect 38 ?lls the remaining trench created
`in ILD 35. Second interconnect 38 may be of the same
`material as ?rst interconnect 30 and/or via 34, or may be a
`completely different material altogether. For example, ?rst
`interconnect 30 and second interconnect 38 may be com
`prised of copper While via 34 may be comprised of tungsten.
`Capping layer 40 is applied above second interconnect 38
`folloWing planariZation. Although not speci?cally shoWn in
`FIG. 3A, capping layer 40 may be patterned, like capping
`layer 32, in anticipation of subsequent interconnect layers.
`The semiconductor structure shoWn in FIG. 3A is referred to
`as a “single damascene” or damascene structure because via
`34 and second interconnect 38 are formed in separate steps.
`FIG. 3B, in contrast to FIG. 3A, depicts a “dual dama
`scene” structure in Which via 34 and second interconnect 38
`are formed in a single step and there is no barrier separating
`them. In this case, via 34 and second interconnect 38
`typically comprise the same material (e.g., copper). Note
`that the term “trench” and “recess” are used synonymously
`herein to indicate a void that may be created in any layer.
`Furthermore, a recess may include additional trenches, for
`example, in FIG. 3A the electrically-insulating layer 35 may
`have a recess that comprises a secondary trench created for
`via 34 and a primary trench created for interconnect 38.
`Interconnect Failure Due to Migration
`When current ?oWs in the interconnect, the momentum
`due to electron ?oW cause the atoms of the interconnect to
`migrate in the direction of electron ?oW along grain bound
`aries. This migration pattern sometimes results in voids
`(depletions in the conductor at grain boundary intersection
`point) and hillocks (accumulation of atoms in the conductor
`at grain boundary intersection points). The voids and hill
`ocks produced by electromigration may lead to the failure of
`an IC by causing open circuits and short circuits of
`interconnects, respectively.
`Interconnect migration failure may also be the result of
`stress induced voiding as observed in “Stress Induced Void
`ing Under Vias Connected to Wide Cu Metal Leads” by E.
`T. OgaWa et al., Which is hereby incorporated by reference.
`In general, interfacial surface stress, or the stress that exists
`at the seam of tWo adjacent layers, is thermally induced and
`is further exacerbated by electrical stresses. As temperatures
`and electric stresses ?uctuate, the inherent interfacial stress
`can cause voids at the seam of adjacent layers.
`Voiding resulting from both stress migration and elec
`tromigration is especially problematic Where the via surface
`meets the interconnect surface in damascene construction. It
`is believed that many migration failures occur in the vicinity
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`8
`of the via/interconnect interface. From an electromigration
`standpoint, as electrons ?oW from the via to the interconnect
`or vice versa, the electrons are required to “tum the
`corner”ii.e., to abruptly change their direction of How to a
`narroWer path. The reduction of electron path Width
`increases electrical resistance and current croWding, result
`ing in the heating of the via/interconnect interface and
`increasing the susceptibility of the interface to migration
`problems. From a stress-induced migration standpoint,
`because the barrier, via, and interconnects are typically
`deposited under different pressures and temperatures, an
`inherent stress mismatch exists betWeen these adjacent lay
`ers that is agitated by increases in temperature. Thus, elec
`tromigration and stress-induced migration combine syner
`gistically to accelerate failure conditions at via/interconnect
`interface.
`Operation
`To combat the susceptibility of interconnects to stress
`induced migration and electromigration, the preferred
`embodiments of the present invention involve modi?cations
`to the interconnects that enhance their mechanical stability.
`The surface of the interconnect is modi?ed rather than the
`bulk interconnect. Consequently, the interconnect bene?ts
`from mechanical stability While retaining the electrical prop
`erties of the unmodi?ed interconnect material. A number of
`preferred embodiments are disclosed herein that relate in
`general to damascene construction and more particularly to
`speci?c surfaces on interconnects. Additionally, as Will be
`understood by a person of skill, the techniques and modi
`?cations described herein are applicable to any interconnect
`in an integrated circuit.
`According to one preferred embodiment of the present
`invention, an interconnect layer is implanted With ions in the
`vicinity of the via/interconnect interface. Referring to FIG.
`4, the dual damascene structure of FIG. 3B is shoWn prior to
`application of the capping layer 40. After the second inter
`connect 38 is deposited and planariZed by CMP, an ion
`implantation step is performed in the area patterned by mask
`42. Preferably, mask 42 restricts ion implantation to the
`vicinity of the interconnect/via interface. Alternatively, a
`chemical species may be introduced into second intercon
`nect 38 by diffusion or by sputtering. In one embodiment,
`second interconnect 38 is copper and the implanted material
`is selected from the group consisting of arsenic, antimony,
`chromium, palladium, tin, magnesium, aluminum, cobalt,
`and Zirconium, and combinations thereof. Preferably,
`implantation depth varies betWeen about 50 and 500 Ang
`stroms and the composition of implanted material in this
`depth range varies betWeen about 0.1 and about 10 percent
`by Weight.
`According to another preferred embodiment of the present
`invention, an alloy layer is deposited on top of second
`interconnect 38 as shoWn in FIG. 5. Referring noW to FIG.
`5, the dual damascene structure of FIG. 3B is shoWn in
`Which second interconnect 38