US006952656B1
`
`(12)
`
`United States Patent
`C0rd0va et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,952,656 B1
`Oct. 4, 2005
`
`(54) WAFER FABRICATION DATA ACQUISITION
`AND MANAGEMENT SYSTEMS
`
`5,444,632 A
`5,497,331 A
`
`8/1995 Kline et al. ............... .. 364/468
`3/1996 Iriki et al. ................ .. 364/468
`
`(75) Inventors: Sherry C0rd0va, Sunnyvale, CA (US);
`Terry L- Doyle, Portola Valley, CA
`(US); Natalia Kroupnova, Sunnyvale,
`CA (Us); Evgueni Lobovski, San Jose,
`CA (US); Inna Louneva, Palo Alto, CA
`(US); Richard C. Lyon, Boulder Creek,
`CA (US); Yukari Nishimura,
`ilitnnyvale’ CA_(US)’ Clar} Nolet’ LOS
`os, CA (US), Terry Relss, San Jose,
`_
`CA (US)’ Woon Young Toh’ San Jose’
`CA (US); Michael E. Wilmer, Portola
`Valley, CA (US)
`
`_
`(73) Asslgnee: Applied Materials, Inc., Santa Clara,
`CA (Us)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/561,440
`_
`(22) Flled:
`
`Apr‘ 28’ 2000
`
`7
`(51) Int. Cl. ............................................. .. G06F 19/00
`(52)
`------ -~ 702/117; 700/121
`(58) Field of Search ...................... .. 702/122, 117, 188;
`710/1; 700/121, 117, 96; 701/1
`
`(56)
`
`References Cited
`
`U_S_ PATENT DOCUMENTS
`
`4,890,239 A 12/1989 Ausschnitt et a1~ ------- ~~ 364/491
`570637494 A * 11/1991 Davidowski ct a1~ ~~~~~ ~~ 395/800
`5,108,570 A
`4/1992 Wang .................... .. 204/1923
`5,236,868 A
`8/1993 Nulman ' ' ' ' ' ' '
`' ' ' " 437/190
`5,260,868 A 11/1993 Gupta 6.‘ ‘11' ~
`364/402
`5’293’216 A
`3/1994 Moslehl ' ' ' ' ' ' '
`' ' ' " 356/371
`5367 624 A 11/1994 C00 ei ..................... .. 395/157
`’
`’
`p
`5,398,336 A
`3/1995 Tantry et al. ............. .. 395/600
`5,408,405 A
`4/1995 MoZumder et al. ....... .. 364/151
`5,410,473 A
`4/1995 Kaneko et al. ...... .. 364/41306
`
`(Con?rmed)
`FOREIGN PATENT DOCUMENTS
`
`EP
`
`0877308 A 11/1998
`(Continued)
`
`....... .. GOSB 19/418
`
`OTHER PUBLICATIONS
`SEMI Draft Doc. 2817, New Standard: Provisional Speci
`.
`.
`.
`?cation for CIM Framework Domain Architecture, pub
`lished by Semiconductor Equipment and Materials Interna
`?onal (SEMI) pp 153 1998
`’
`'
`’
`'
`
`(Continued)
`Primary Examiner—Marc S. Hoff
`Assistant Examiner—Paul Kim
`(74) Attorney, Agent, or Firm—LaW Of?ce of Albert J.
`Dalhllisen
`
`(57)
`
`ABSTRACT
`
`The present invention provides a semiconductor processing
`device (800) including a tool (802) having one or more
`sensors, a primary data communication port (804) and a
`Secondary data Communication port (806)' A Sensor data
`acquisition subsystem (808) acquires sensor data from the
`tool via the secondary port (806). The data acquisition
`subsystem (808) acquires MES operation messages via the
`primary port (804). Sensor data are communicated to a
`sensor processing unit (828) of a sensor data processing
`subsystem (810). The sensor processing unit (828) processes
`and analyzes the sensor data. Additionally, the processing
`unlt (828) can be adapted for maklng product or processlng
`related decisions, for example activating an alarm if the
`process is not operating Within control limits. In another
`embodiment, the present invention provides a method and
`apparatus for processing data from a Wafer fab facility
`(1000) including a plurality of tools (1004-1010) each
`havin a rimar data communication ort (1012-1018) and
`g p
`y
`.
`.
`p
`dar data communlcatlon ort (1042-1048).
`a Sewn y
`p
`
`9 Claims, 11 Drawing Sheets
`
`[510
`
`MES
`INPUT
`DEVICE
`
`EDAS
`INPUT
`DEVICE
`
`642
`
`NETI ORK
`SERIAL
`FORT
`
`645
`
`r _ _ _ _ __
`
`61 B
`
`___ —s2_4___§is_ ——_:
`
`EDAS
`ACQUIRED DATA
`ENVIRONMENT
`
`INFORMATION
`PROCESSING AND
`ANALYZING
`ENVIRONMENT
`
`DECISION
`MAKING
`ENVIRONMENT
`
`l
`I
`[
`I
`
`RESPONSE
`ENVIRONMENT
`
`2a
`
`532
`
`634
`
`NETWORK
`SERIAL
`PORT
`
`Page 1 of 24
`
`

`
`US 6,952,656 B1
`Page 2
`
`US. PATENT DOCUMENTS
`
`5,586,041 A 12/1996 Mangrulkar ......... .. 364/474.16
`5,629,216 A
`5/1997 Wi]aranakula et a1.
`438/502
`5,698,989 A 12/1997 Nulman ........... ..
`324/719
`5,711,843 A *
`1/1998 Jahns ....................... .. 156/345
`
`10/2001 Nulman ..................... .. 438/14
`6,303,395 B1
`1/2002 Cho ......................... .. 700/121
`6,336,055 B1
`9/2OO2 Davidow et a1‘
`438/71O
`674557437 131*
`6456 894 B1 * 90002 N 1
`700
`,
`,
`u man .................... ..
`/121
`6 535 779 B1 *
`3 2003 B.
`700 121
`1
`7
`7
`/
`‘rang eta' """"""" "
`/
`
`
`
`5,715,181 A 5,719,495 A
`
`5,740,429 A
`5,754,297 A
`5,761,064 A
`5,783,342 A
`5,787,000 A
`5,808,303 A
`
`
`
`2/1998 HOISI ....................... .. 364/554 2/1998 Moslehi 324/158.1
`
`
`
`395/615
`4/1998 Wang et al.
`356/381
`5/1998 Nulman
`. 364/468.17
`6/1998 La et al. ....... ..
`......... .. 430/30
`7/1998 Yamashita et al
`7/1998 Lilly et al. ........... .. 364/468.01
`9/1998 Schlagheck et al. ...... .. 250/330
`
`JP
`JP
`JP
`JP
`
`HEI 11-67853
`HEI 1-283934
`HEI 8-149583
`HEI 9-34535
`
`7/1989
`11/1989
`6/1996
`2/1997
`
`.......... .. H04Q 9/00
`........ .. G05B 23/02
`
`OTHER PUBLICATIONS
`
`-
`-
`-
`-
`rd
`ge?zr van Zandt, Microchip Fabrication, 3 ed., McGraW
`1 ’ PP' 472'478’ 1997'
`.
`.
`SEMI E_10'96> Sim/‘1W1 F0’ DQ114190” And Measflrenfem
`OF Equipment Reliabiltiy, Availability And Maintainability
`(RAM), published by semiconductor Equipment and Materi
`als (SEMI), pp. 1-23, 1996.
`W.R. Runyan et al. Semiconductor Integrated Circuit
`
`5,826,236 A 10/1998 Narimatsu et a1. ........... .. 705/8
`5,838,566 A * 11/1998 Conboy et a1‘
`7OO/115
`5,859,964 A *
`1/1999 Wang et al
`...... .. 714/48
`5,862,054 A
`1/1999 Li ......... ..
`. 364/468.28
`5,864,483 A
`1/1999 Brichta ________ __
`_ 364/468_16
`5,883,437 A
`3/1999 Maruyama et a1. ....... .. 257/773
`5,905,032 A
`5/1999 Walton et al. ......... .. 435/173.2
`5,910,011 A
`6/1999 Cruse - - - - - - - - -
`- - - - - -- 436/16
`5,914,879 A
`6/1999 Wang et a1
`Processing Technology, Addison-Wesley Publ. Corn/ Inc. p.
`364/468-18
`48, 1994
`5,956,251 A
`9/1999 Atkinson et a1. .... .. 364/468.16
`R~ Zorich, Handbook of Quality Integrated Circuit
`5,987,398 A 11/1999 Halverson et a1. ........ .. 702/179
`6,054,379 A
`4/2000 Yau et al. ..... ..
`438/623 M
`. A d . P
`I
`464_498 1991
`6,128,588 A 10/2000 Chacon ....................... .. 703/6
`anufacmmg’ .621 emlc r555 nc"pp'
`’
`_'
`6,138,143 A 10/2000 Gigliotti et a1. .......... .. 700/203
`Prasad Rampalh 9t 91» CEPT—_A Computer-A1916?‘
`6,201,999 B1
`3/2001 Jevtic .......... ..
`700/100
`Manufacmnng APPhCaHOH for Managlng Eqlllpment R611
`6,223,091 B1
`4/2001 Powell
`700/80
`ability and Availability in the Semi-Conductor Industry”,
`6,226,563 B1
`5/2001 Lim
`700/121
`IEE Transactions on Components, Hybrids, and
`700/121
`Manufacturing Technology, IEEE Inc. NeW York, vol. 14,
`6,240,331 El *
`5/2001 Yun ------ -
`6,249,712 B1
`6/2001 Boiquaye .
`.. . 700/31
`NO_ 3, pp 499-506, (1991)_
`6,263,255 B1 *
`7/2001 Tan et al. ................. .. 700/121
`6,269,279 B1 *
`7/2001 Todate et al. ............. .. 700/121
`
`* cited by examiner
`
`Page 2 of 24
`
`

`
`U.S. Patent
`
`0a. 4, 2005
`
`Sheet 1 0f 11
`
`US 6,952,656 B1
`
`—I
`
`CLEAN WAFER
`
`METALLIZE
`
`I
`
`43~ GROW FIELD OXIDE
`
`PATTERN METAL
`
`I
`45~ SOURCE-DRAIN
`OXIDE REMOVAL
`I
`47~ SOURCE-DRAIN
`B DIFFUSION
`I
`
`GATE OXIDE
`REMOVAL
`
`I
`
`CLEAN PREGATE
`
`I
`
`GROW GATE
`OXIDE
`
`ION IMPLANT
`THRESHOLD
`ADJUST
`
`I
`
`I
`
`CONTACT OXIDE
`REMOVAL
`
`I
`
`ETCH METAL
`
`I
`
`ANNEAL
`
`DEPOSIT
`PROTECTIVE
`OVERCOAT
`
`I
`PATTERN
`PROTECTIVE
`OVERCOAT
`
`I
`
`ETCH
`PROTECTIVE
`OVERCOAT
`
`I
`
`MULTIPROBE
`WAFER
`
`FIG-1
`(PRIOR ART)
`
`Page 3 of 24
`
`

`
`U.S. Patent
`
`0a. 4,2005
`
`Sheet 2 0f 11
`
`US 6,952,656 B1
`
`PRE-HEAT THE
`a1~ WAFER SUPPORT
`
`PLATFORM
`
`80
`
`/
`
`83~ POSITION THE WAFER
`ON THE PLATFORM
`
`85~ CLAMP THE WAFER
`IN POSITION
`
`87'»
`
`I
`
`EVACUATE THE
`CHAMBER TO A
`PRE-DETERMINED
`VACUUM
`
`I
`
`HEAT THE WAFER TO
`89~ A PRE-DETERMINED
`TEMPERATURE
`
`91~
`
`FLOW SPUTTER GAS INTO
`THE CHAMBER WITHIN A
`PRE-DETERMINED FLOW RANGE
`AND PRESSURE RANGE
`
`I
`
`CARRY OUT A FIRST SPUTTER
`93~ DEPOSITION AT PRE-DETERMINED
`FIRST SPUTTER
`DEPOSITION CONDITIONS
`
`I
`
`CARRY OUT A SECOND SPUTTER
`95~ DEPOSITION AT PRE-DETERMINED
`SECOND SPUTTER
`DEPOSITION CONDITIONS
`
`I
`
`OPTIONALLY, CARRY OUT A
`97~ THIRD SPUTTER DEPOSITION
`AT PRE-DETERMINED THIRD
`SPUTTER DEPOSITION CONDITIONS
`
`‘PIZRg'ARUZ
`
`-—
`
`Page 4 of 24
`
`

`
`U.S. Patent
`
`0a. 4,2005
`
`Sheet 3 0f 11
`
`US 6,952,656 B1
`
`~ NON-SCHEDULED
`'02
`TIME
`
`104“,
`
`UNSCHEDULED
`DOWNTIME
`
`106“,
`
`SCHEDULED
`DOWNTIME
`
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`STmDEBY
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`
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`
`J
`
`J
`
`FIG. — 3
`(PRIOR ART)
`
`TOTAL TIME $114
`
`NON-SCHEDULED [102
`TIME
`
`OPERATIONS
`TIME
`
`I116
`
`UNWORKED
`SHIFTS
`
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`
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`
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`
`I/—134
`
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`
`[13G
`
`FIG. — 4
`(PRIOR ART)
`
`Page 5 of 24
`
`

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`U.S. Patent
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`Page 9 of 24
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`
`

`
`U.S. Patent
`
`OCt. 4, 2005
`
`Sheet 8 0f 11
`
`US 6,952,656 B1
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`Page 10 of 24
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`

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`U.S. Patent
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`Oct. 4, 2005
`
`Sheet 9 of 11
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`U.S. Patent
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`0a. 4,2005
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`Sheet 10 0f 11
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`US 6,952,656 B1
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`

`
`U.S. Patent
`
`Oct. 4, 2005
`
`Sheet 11 0f 11
`
`US 6,952,656 B1
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`US 6,952,656 B1
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`1
`WAFER FABRICATION DATA ACQUISITION
`AND MANAGEMENT SYSTEMS
`
`FIELD OF THE INVENTION
`
`The present invention relates to devices, techniques and
`methods for semiconductor processing.
`
`BACKGROUND OF THE INVENTION
`
`Asemiconductor device such as an IC (integrated circuit)
`generally has electronic circuit elements such as transistors,
`diodes and resistors fabricated integrally on a single body of
`semiconductor material. The various circuit elements are
`connected through conductive connectors to form a com
`plete circuit Which can contain millions of individual circuit
`elements. Integrated circuits are typically fabricated from
`semiconductor Wafers in a process consisting of a sequence
`of processing steps. This process, usually referred to as
`Wafer fabrication or Wafer fab, includes such operations as
`oxidation, etch mask preparation, etching, material deposi
`tion, planariZation and cleaning.
`Asummary of an aluminum gate PMOS (p-channel metal
`oxide semiconductor transistor) Wafer fab process 40 is
`schematically shoWn in FIG. 1, illustrating major processing
`steps 41 through 73, as described in W. R. Runyan et al.,
`Semiconductor Integrated Circuit Processing Technology,
`Addison-Wesley Publ. Comp. Inc., p. 48, 1994. Each of
`these major processing steps typically include several sub
`steps. For example, a major processing step such as metal
`liZation to provide an aluminum layer by means of sputter
`deposition in a Wafer fab chamber is disclosed in US. Pat.
`No. 5,108,570 (R. C. Wang, 1992). This sputter deposition
`process is schematically shoWn in sub steps 81 through 97
`of process 80, see FIG. 2.
`FIGS. 1 and 2 shoW sequential Wafer fab processes. It is
`also knoWn to utiliZe Wafer fab sub systems Which provide
`parallel processing steps. Such sub systems typically include
`one or more cluster tools. A cluster tool as de?ned herein
`includes a system of chambers and Wafer handling equip
`ment Wherein Wafers are processed in the cluster tool
`chambers Without leaving a controlled cluster tool environ
`ment such as vacuum. An example of a cluster tool is
`disclosed in US. Pat. No. 5,236,868 (J. Nulman, 1993)
`Which employs a vacuum apparatus having a central cham
`ber and four processing chambers. AWafer handling robot in
`the central chamber has access to the interior of each the
`processing chambers in order to transfer Wafers from the
`central chamber into each of the chambers While keeping the
`Wafers in a vacuum environment. In one example, Wafers in
`the ’868 cluster are ?rst transferred for processing to a
`cleaning chamber, then to a PVD (physical vapor deposi
`tion) chamber, folloWed by transfer to an annealing chamber
`and subsequently to a degassing chamber, thus utiliZing a
`sequential process. It is also knoWn to use cluster tools such
`as those disclosed in the ’868 patent to process Wafers in
`chambers Which are used in parallel. For example, if a sloW
`processing step is folloWed by a fast processing step, three
`chambers can be used in parallel for the sloW process While
`the fourth chamber is used for the fast process.
`It is Well knoWn to those of ordinary skill in the art that
`one or more processing parameters of a typical Wafer fab
`process step need to be controlled Within a relatively narroW
`range in order to obtain a product Which has the desired
`characteristics. For example, US. Pat. No. 5,754,297 (J.
`Nulman, 1998) discloses a method and apparatus for moni
`toring a deposition rate during Wafer fab metal ?lm depo
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`sition such as sputtering. The ’297 patent teaches that the
`metal deposition rate decreases With increasing age of the
`sputter target if the input sputter poWer level is maintained
`at a constant level. As a consequence, critical processing
`characteristics, such as the metal deposition rate, may vary
`from run to run for a given Wafer fab processing chamber in
`Ways that can affect the yield and quality of devices pro
`cessed in that chamber. As disclosed in the ’297 patent, the
`deposition system can be more readily maintained near
`desired levels When processing variables, such as the poWer
`input to the sputtering source, are adjusted in response to
`observed variations in the metal deposition processing char
`acteristics. This requires in-situ measurement of processing
`characteristics, using for example a deposition rate monitor
`based on the optical attenuation of light passing through the
`deposition environment, thereby detecting the rate at Which
`material is ?oWing from the deposition source to the depo
`sition substrate, as described more fully in the ’297 patent.
`Advances in semiconductor materials, processing and test
`techniques have resulted in reducing the overall siZe of the
`IC circuit elements, While increasing their number on a
`single body. This requires a high degree of product and
`process control for each processing step and for combina
`tions or sequences of processing steps. It is thus necessary
`to control impurities and particulate contamination in the
`processing materials such as process gases. Also, it is
`necessary to control processing parameters such as tempera
`ture, pressure, gas ?oW rates, processing time intervals and
`input sputter poWer, as illustrated in the ’570 and ’297
`patents. As illustrated in FIGS. 1 and 2, a Wafer fab includes
`a complex sequence of processing steps Wherein the result of
`any particular processing step typically is highly dependent
`on one or more preceding processing steps. For example, if
`there is an error in the overlay or alignment of etch masks
`for interconnects in adjacent IC layers, the resulting inter
`connects are not in their proper design location. This can
`result in interconnects Which are packed too closely, forming
`electrical short defects betWeen these interconnects. It is also
`Well knoWn that tWo different processing problems can have
`a cumulative effect. For example, a misalignment of inter
`connect etch masks Which is not extensive enough to result
`in an electrical short, can still contribute to causing an
`electrical short if the process is slightly out of speci?cation
`for alloWing (or not detecting) particulate contamination
`having a particle siZe Which Would not have caused an
`electrical short if the interconnect masks had been in good
`alignment.
`Processing and/or materials defects such as described
`above generally cause a reduced Wafer fab yield, Wherein the
`yield is de?ned as the percentage of acceptable Wafers that
`are produced in a particular fab. In-process tests and moni
`toring of processing parameters are utiliZed to determine
`Whether a given in-process product or process problem or
`defect indicates that intervention in the process run is
`necessary, such as making a processing adjustment or abort
`ing the run. Consequently, product and process control
`techniques are used extensively throughout a Wafer fab.
`When possible, yield problems are traced back to speci?c
`product or processing problems or defects to ultimately
`improve the yield of the Wafer fab. High yields are desirable
`for minimiZing manufacturing costs for each processed
`Wafer and to maximiZe the utiliZation of resources such as
`electrical poWer, chemicals and Water, While minimiZing
`scrap re-Work or disposal.
`It is knoWn to use SPC (statistical process control) and
`SQC (statistical quality control) methods to determine suit
`able Wafer fab control limits and to maintain the process
`
`Page 14 of 24
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`US 6,952,656 B1
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`Within these limits, see for example R. Zorich, Handbook Of
`Quality Integrated Circuit Manufacturing, Academic Press
`Inc., pp. 464—498, 1991. SPC and SQC methodologies
`suitable for a Wafer fab include the use of control charts, see
`for example R. Zorich at pp. 475—498. As is Well known to
`those of ordinary skill in the art, a control chart is a graphical
`display of one or more selected process or product variables,
`such as chamber pressure, Which are sampled over time. The
`target value of a particular variable and its upper and loWer
`control limits are designated on the chart, using Well knoWn
`statistical sampling and computation methods. The process
`is deemed out of control When the observed value of the
`variable, or a statistically derived value such as the average
`of several observed values, is outside the previously deter
`mined control limits. Control limits are typically set at a
`multiple of the standard deviation of the mean of the target
`value, such as for example 20 or 30. The target value is
`derived from a test run or a production run Which meets such
`Wafer fab design criteria as yield, process control and
`product quality. SPC and SQC are considered synonymous
`When used in the above context, see R. Zorich at p. 464.
`Many components or sub-systems of a Wafer fab are
`automated in order to achieve a high degree of processing
`reliability and reproducibility and to maximiZe yields. Wafer
`fab tools such as chambers are typically controlled by a
`computer using a set of instructions Which are generally
`knoWn as a recipe for operating the process Which is
`executed by the tool. HoWever, it is recogniZed that a high
`degree of automation Wherein various processes and
`metrologies are integrated, is dif?cult to achieve due to the
`complexity and inter dependency of many of the Wafer fab
`processes, see for example Peter van Zandt, Microchip
`Fabrication, 3rd ed., McGraW-Hill, pp. 472—478, 1997.
`It is knoWn to acquire processing data from multiple
`sensors Within a semiconductor processing system and to
`utiliZe the acquired data for process monitoring, see for
`example US. Pat. No. 5,910,011 (J. P. Cruse, 1999). As
`shoWn in the ’011 patent, data regarding multiple process
`parameters are acquired from the sensors. A statistical
`engine correlates the relevant process parameters to aid in
`detecting a speci?c change in the processing characteristics.
`The correlated data can be compared to data de?ning a
`decision threshold in order to assist in making processing
`decisions, such as stopping the process When the correlated
`data shoW that the processing endpoint has been reached, or
`providing an alarm signal indicating for example that the
`process should be stopped. Correlated process parameters
`data are stored to determine a Wafer-to-Wafer correlation
`trend. Overall signal-to-noise ratios are reduced by means of
`the ’011 correlation of tWo or more signals or parameters,
`thus improving detection of a decision threshold.
`Aunit of semiconductor manufacturing equipment, such
`as a Wafer fab tool, commonly employs an on-board com
`puter to identify and/or regulate equipment, processing or
`material parameters in connection With the tool and the
`manufacturing process. The communication interface
`betWeen the on-board computer of the manufacturing unit
`and a host computer typically includes a protocol such as
`SECS II (SEMI Equipment Communication Standard). It is
`Well knoWn to those of ordinary skill in the art that conven
`tional communication protocols such as SECS II have
`limitations including a maximum baud rate of 19200. The
`limited data transfer capacity of this type of communication
`protocol imposes a restriction on communications betWeen
`a computer and a tool, thereby limiting the types of data and
`the data transfer speed. For example, it is Well knoWn to
`those of ordinary skill in the art that conventional tool
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`communication protocols, such as SECS II are, not suitable
`protocols for communicating extensive tool metrology data
`from a tool to a computer, particularly Where this concerns
`extensive collection and use of SPC related data, or SEMI
`E10-96 data (see beloW).
`It is Well knoWn to those of ordinary skill in the art that
`the functions of semiconductor manufacturing equipment,
`including for example a Wafer fab, can be de?ned in basic
`equipment states such as the six states schematically illus
`trated in FIG. 3, see SEMI E10-96, Standard For De?nition
`Ana' Measurement Of Equipment Reliability, Availability,
`Ana' Maintainability (RAM), published by Semiconductor
`Equipment and Materials International (SEMI), pp. 1—23,
`1996. The semiconductor industry typically uses these six
`equipment states to measure and express equipment RAM
`(reliability availability and maintainability), based on func
`tional equipment issues Which are independent of Who
`performs the function. These six basic equipment states
`include non-scheduled time 102 (FIG. 3), unscheduled
`doWntime 104, scheduled doWntime 106, engineering time
`108, standby time 110 and productive time 112. Non
`scheduled time 102 represents the time period Wherein the
`equipment is not scheduled to be used, for example
`unWorked shift. Unscheduled doWntime 104 concerns time
`periods Wherein the equipment is not in a condition to
`perform its intended function, eg during equipment repair.
`Scheduled doWntime 106 occurs When the equipment is
`capable of performing its function but is not available to do
`this, such as process setup or preventive maintenance.
`Engineering time 108 concerns the time period Wherein the
`equipment is operated to conduct engineering tests, for
`example equipment evaluation. Standby time 110 is a time
`period Wherein the equipment is not operated even though it
`is in a condition to perform its intended function and is
`capable of performing its function, for example no operator
`is available or there is no input from the relevant information
`systems. Productive state 112 represents the time period
`Wherein the equipment is performing its intended function,
`such as regular production and reWork.
`Total time period 114, see FIG. 3, is the total time during
`the period being measured; this includes the six equipment
`states 102, 104, 106, 108, 110 and 112. Operations time 116
`concerns the total time period of states 104, 106, 108, 110
`and 112. Operations time 116 includes equipment doWntime
`118 consisting of states 104 and 106, and equipment uptime
`120. Equipment uptime 120 includes engineering time 108
`and manufacturing time 122 Which consists of standby time
`110 and productive time 112.
`FIGS. 4 and 5 provide more detailed schematic illustra
`tions of the six equipment states shoWn in FIG. 3, see SEMI
`E10-96, at pp. 1—6. As depicted in FIG. 4, total time 114
`consists of non-scheduled time 102 and operations time 116.
`Non-scheduled time 102 includes unWorked shifts 130,
`equipment installation, modi?cation, rebuilding or upgrad
`ing 132, off-line training 134 and shutdoWn or start-up time
`period 136. Operations time 116, as schematically illustrated
`in FIG. 5, consists of equipment doWntime 118 and equip
`ment uptime 120. Equipment doWntime 118 consists of
`unscheduled doWntime 104 and scheduled doWntime 106.
`Unscheduled doWntime 104 includes doWntime for mainte
`nance delay 140, repair time 142, changing consumables/
`chemicals 144, out of speci?cation input 146 or facilities
`related doWntime 148. Scheduled doWntime 106 concerns
`doWntime for maintenance delay 150, production test 152,
`preventive maintenance 154, changing consumables/chemi
`cals 156, setup 158 or facilities related 159.
`
`Page 15 of 24
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`US 6,952,656 B1
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`5
`Equipment uptime 120, depicted in FIG. 5, consists of
`engineering time 108 and manufacturing time 122. Engi
`neering time 108 includes process experiments 160 and
`equipment experiments 162. Manufacturing time 110 con
`sists of standby time 110 and productive time 112. Standby
`time 110 includes time during Which there is no operator
`180, no product 182, no support tool 184 or When an
`associated cluster module is doWn 186. Productive time 112
`concerns a time period during Which there is regular pro
`duction 190, Work for a third party 192, reWork 194 or an
`engineering run 196. The various equipment states as
`described in connection With FIGS. 3—5 provide a basis for
`communicating and evaluating RAM related equipment
`information in the semiconductor industry. RAM related
`equipment information includes topics Which are Well
`knoWn to those of ordinary skill in the art such as: equipment
`reliability, equipment availability, equipment maintainabil
`ity and equipment utiliZation, see for example SEMI E10-96
`at pp. 6—11.
`Accordingly, a need exists for methods and techniques
`Which provide improved data transfer capacity betWeen a
`tool and a host computer, as Well as improved process
`control, quality, yield and cost reduction. Also, there is a
`need to integrate Wafer fab equipment time states With
`improved maintenance and process scheduling.
`
`SUMMARY OF THE INVENTION
`
`The present novel techniques for data acquisition and
`management systems of semiconductor processing devices
`and Wafer fabs provide the needed improvement in data
`acquisition, process control, quality, yield and cost reduc
`tion.
`In one embodiment of the present invention, a semicon
`ductor fabricating tool and processing methods are provided
`Wherein the tool includes a primary communication port and
`a secondary communication port. The tool also includes a
`sensor for sensing process, product and equipment param
`eters that are then communicated to a sensor data acquisition
`unit via the secondary port. The primary port is employed to
`communicate MES messages and queries to the tool.
`In another embodiment a method and apparatus are pro
`vided for processing data from a Wafer fab facility including
`a plurality of tools each having a primary and a secondary
`communication port as Well as a sensor communicating With
`the secondary communication port. The facility additionally
`includes a host database and host computer as Well as a data
`base management system and Wafer fab management soft
`Ware. Tool operating instructions are executed employing
`legacy softWare communicating via the primary port of each
`tool. Sensor data are acquired via the secondary port of each
`tool.
`In yet another embodiment of the present invention, a
`computer executable process for operating a Wafer fab
`management system is provided. The system derives a
`model for the system by de?ning Wafer fabrication data
`structures, and by de?ning relationships betWeen these
`structures. System con?guration data are selected for oper
`ating the system. The con?guration data are then adjusted
`according to a user input. Operational data are subsequently
`gathered When the system is activated. The operational data
`are gathered and then formatted to form updated data
`structures. A database management system is utiliZed to
`manage the gathered data and to insure consistency With the
`system data structures and the relationships betWeen the data
`structures.
`
`6
`In still another embodiment of the present invention a
`netWork distributed database for semiconductor fabricating
`is provided utiliZing a plurality of semiconductor processing
`devices each having a tool including a primary and second
`ary data communication port. A netWork is provided for
`interconnecting the plurality of semiconductor devices and a
`data base management system.
`In another embodiment of the present invention a com
`puter executable data structure is provided for operating one
`or more tools of a Wafer fab. The data structure includes
`control system data.
`In yet another embodiment of the present invention a data
`structure is provided Wherein data, organiZed in relational
`tables, are adapted for being accessed by one or more
`applications for semiconductor fabricating. For example, a
`recipe manager application can access a recipe manager
`relational table or a recipe step relational table to add
`information to these tables, or to change the content of these
`tables.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a ?oWchart schematically