Ulllted States Patent [19]
`Jacobs
`
`[54] APPARATUS AND METHOD FOR
`CONTROLLING EXPERIMENTAL
`INVENTORY
`
`[75] Inventor: Marc A. Jacobs, San Mateo, Calif.
`
`[73] Assignee: Cypress Semiconductor Corp., San
`Jose, Calif.
`
`[21] Appl' NO': 08/984’722
`[22] Filed;
`Dec, 4, 1997
`
`7
`[51] Int. Cl. ................................................... .. G11C 29/00
`[52] US. Cl. .................. .. 365/201; 365/103; 365/185.09;
`324/765
`[58] Field Of Search ................................... .. 365/201, 103,
`365/185-09; 324/765; 371/211, 22-1
`_
`References Clted
`US' PATENT DOCUMENTS
`
`[56]
`
`4,510,673
`4,931,997
`
`4/1985 Shils et a1. .............................. .. 29/574
`6/1990 Mitsubishi et a1~
`365/218
`1(1);
`gltiublsinlet al'
`573607747 11/1994 Larson et a1‘
`5 406 566 4/1995 Obara
`5:457:408 10/1995 Leung ' ' ' ' ' ' ' '
`
`,
`
`,
`
`or ey e a.
`
`. 437/8
`371/21 2
`_ _ _ _ __ 326/3'8
`
`US006052319A
`[11] Patent Number:
`[45] Date of Patent:
`
`6,052,319
`Apr. 18, 2000
`
`5,867,714
`2/1999 Todd et a1. ............................ .. 395/712
`5,892,683
`4/1999 Sung ~~~~~~ ~-
`~
`5,905,887
`5/1999 Wu et a1
`.
`5,917,833
`6/1999 Sato ..................................... .. 371/211
`Primary Examiner_Tan T_ Nguyen
`Arr AtF'—K'L.Dff'ClR&
`Tayoggey gen ’ Or Wm evm
`a er’ on 6y’ 056
`
`ABSTRACT
`[57]
`An integrated circuit, apparatus, and a method is provided
`for programming and reading manufacturing information
`upon non-volatile storage elements of the integrated circuit.
`The manufacturing information includes the particular pro_
`Cessing recipe and layout of the integrated Circuit, each
`recipe or layout indicative of a speci?c hardware revision.
`The Storage elements may be programmed prior to assem
`bling the integrated circuit Within a semiconductor package,
`and the programmed elements are read prior to shipping the
`packaged integrated circuit to a customer. If the read hard
`Ware revision is not quali?ed for release, the product Will be
`placed in a staging area and prevented from shipping to a
`customer or end user, Thus, the programmed hardware
`revision serves to gate product at test before shipping that
`product to a customer. The manufacturing information is
`programmed by the manufacturer and' is inaccessible by a
`customer since the address space WhlCh contains product
`engineering bits is knoWn only to the manufacturer.
`
`-
`
`-
`
`-
`
`5,642,307
`5,664,093
`
`365/103
`6/1997 Jernigan ...... ..
`9/1997 Barnett et a1. ................... .. 395/183.07
`
`18 Claims, 3 Drawing Sheets
`
`14 \
`
`16
`
`/] PRODUCT REW] PROGRAM REV# ] PROGRAM TOOL?
`
`Page 1 of 10
`
`

`
`U.S. Patent
`
`Apr. 18,2000
`
`Sheet 1 0f 3
`
`6,052,319
`
`14 \
`
`16
`
`34 \ 36
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`CORE
`E
`
`A/D DECODE +
`w
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`
`Page 2 of 10
`
`

`
`U.S. Patent
`
`Apr. 18,2000
`
`Sheet 2 of3
`
`6,052,319
`
`>
`N3
`>4
`N2
`><
`54\ + N1
`PRODUCT REV# PROGRAM REV# PROGRAM TOOL#
`@
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`- I I I I I _ I/ ADDRESS
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`SPACE
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`
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`/ 130
`
`PROD. REV#
`PROG. REV#
`PROG. TOOL# CDMPARATOR
`
`PROG. COMPATABILITY SIG.
`
`FIG. 5
`
`Page 3 of 10
`
`

`
`U.S. Patent
`
`Apr. 18,2000
`
`Sheet 3 0f 3
`
`6,052,319
`
`ETEST H
`
`BAKE
`§_Q
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`
`Page 4 of 10
`
`

`
`1
`APPARATUS AND METHOD FOR
`CONTROLLING EXPERIMENTAL
`INVENTORY
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This invention relates to integrated circuit manufacture
`and, more particularly, to an apparatus and method for
`identifying and preventing improper shipment of integrated
`circuits from the circuit manufacturer to a customer or user.
`2. Description of the Related Art
`An integrated circuit is often referred to as a die or chip.
`Those terms are henceforth interchangeably used. A die may
`contain several thousand active and passive devices formed
`on a monolithic substrate. Those devices can be intercon
`nected to form an overall circuit. Active devices include
`transistors, Whereas passive devices include resistors and
`capacitors, for example.
`Active and passive devices are formed and interconnected
`across the substrate using numerous fabrication steps, mate
`rials and equipment. To achieve precise placement of fea
`tures Which form an integrated circuit, a carefully carried out
`sequence of processing steps (e.g., deposition, etch,
`lithography, implant and/or heat cycles must be folloWed).
`Any deviation from the pre-set fabrication “recipe” Will
`modify characteristics of the resulting product. In addition,
`any changes Whatsoever to equipment used to implement the
`various steps Will also modify the resulting product. For
`example, an ion implant concentration and/or energy from a
`speci?c ion implanter may be desired over other
`concentrations, energies or implanters. For this reason,
`many fabrication processes require speci?c types of equip
`ment used to perform the various processing steps.
`In addition to tracking the sequence and equipment used
`during the fabrication sequence, there may also be a desire
`to promote a particular arrangement of features Which form
`the various active and passive devices. In this instance, the
`features are produced according to What is often called a
`“layout”. There may be numerous layout arrangements used
`for a speci?c integrated circuit depending upon the number
`of revisions that must be undertaken to achieve optimal
`performance, or performance Which is more suitable to a
`speci?c application. As the layout changes, the various
`masks Which form the integrated circuit also change.
`Typically, the revision number on each mask is imprinted on
`the resulting integrated circuit. The imprint is usually placed
`in a non-functional region of the integrated circuit and can
`be visually detected. Unfortunately, once the integrated
`circuit is removed from the Wafer and encapsulated in a
`package, the revision number of the layout can no longer be
`discerned.
`It Would be desirable to track not only the particular
`processing recipe but also the layout revision, both of Which
`are generically referred to henceforth as the manufacturing
`or “hardware” revision. It is intended that hardWare revision
`encompass one or more, or a grouping of select parameters
`(e.g., processing steps, processing equipment, processing
`materials and/or layouts, etc.) used in forming active and
`passive devices on an integrated circuit. The tracking
`mechanism must be one Which can detect a hardWare
`revision attributable to an integrated circuit after the inte
`grated circuit is removed from the Wafer, placed in a package
`and possibly shipped to a customer. The mechanism of
`tracking hardWare revisions after the integrated circuit
`leaves the manufacturing site proves bene?cial, for example,
`in determining Why or hoW the integrated circuit failed in the
`?eld.
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`6,052,319
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`2
`HardWare revisions (i.e., revision to the processing recipe,
`processing equipment, or layout) used to produce a dissimi
`lar version of integrated circuit product, are generally
`needed in order to perform changes to the ?nal hardWare
`product or possibly to experiment With changes to the
`product. Experimental results may help identify possible
`future enhancements to the hardWare product.
`Experimental Wafer lot runs are often referred to as
`non-quali?cation lots used by product engineers to ascertain,
`for example, possible causes of yield loss. By performing
`experiments on one or more Wafers or one or more Wafer
`lots, the product engineer can gather information useful in
`improving the integrated circuit performance or yield. Peri
`odic experiments prove useful but only if packaged inte
`grated circuits formed from those experiments are not inad
`vertently shipped to a customer. While a non-quali?cation
`Wafer lot may pass ?nal tests procedures, it may nonetheless
`be prudent not to ship integrated circuits derived from that
`lot. For example, if the experimental Wafers demonstrate
`reliability problems, then the shipped integrated circuits
`may, over time, fail. It is not until the non-quali?ed Wafers
`are quali?ed is it desirable to release that product to a
`customer. For this reason, it Would be bene?cial to not only
`track each and every hardWare revision used to produce all
`the various parameters Which involve integrated circuit
`manufacture, but also to prevent shipping non-quali?ed
`hardWare revisions to a customer.
`In addition to tracking hardWare revisions, it may also be
`desirable to track softWare revisions. For example, many
`integrated circuits employ one or more memory elements
`arranged across the die. A popular memory device is one
`Which can be electrically programmed after the die is
`manufactured, or possibly shipped to the customer. Once the
`storage elements are programmed, they are preferably non
`volatile. Present non-volatile storage elements include, for
`example, programmable read only memory (“PROM”),
`fuses and/or anti-fuses, etc. Examples of popular PROMs
`include EPROMs, EEPROMs, or ?ash memory. The
`memory elements upon the die may be programmed either
`by the manufacturer or in the ?eld. It may be important to
`keep track of the particular version of softWare used to
`program the memory elements since compatibility of that
`program version to a particular hardWare revision used in
`forming the integrated circuit is important.
`If an integrated circuit involves non-volatile memory
`elements then, in many instances, a customer Will program
`the memory elements in the ?eld using a softWare program
`revision Which may or may not be compatible With the
`hardWare revision shipped from the manufacturer. If the
`integrated circuit fails in its intended purpose, the customer
`or manufacturer Will generally not knoW if the problem rests
`With the hardWare or the manner in Which the non-volatile
`storage elements Were programmed. Typically, hoWever, a
`manufacturer Will knoW that a particular hardWare revision
`is compatible With speci?c softWare revisions Which, in
`most instances, are supplied directly or indirectly to the
`customer from the manufacturer. Thus, if a neW hardWare
`revision is released to the customer, then changes may be
`needed to the softWare program to form a neW softWare
`revision compatible With that hardWare. It is for this reason
`that it Would be desirable to knoW if the hardWare revision
`matches the softWare revision. More importantly, it Would
`be desirable to read both the hardWare and softWare revi
`sions either at the customer or manufacturer site, possibly
`during program of the non-volatile memory. If, for example,
`the hardWare and softWare revisions do not match, the
`customer can return the product to the manufacturer and
`
`Page 5 of 10
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`

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`6,052,319
`
`3
`receive updated hardware or software. The bene?t of knoW
`ing a particular hardWare revision and Whether that revision
`is quali?ed for release to a customer Would therefore prove
`an important bene?t to the manufacturer along With knowing
`the particular softWare revision used in programming the
`integrated circuit at the customer site.
`
`SUMMARY OF THE INVENTION
`
`The problems outlined above are in large part solved by
`an electrically programmable integrated circuit, die or chip.
`Formed on a portion of the integrated circuit is a non-volatile
`storage location containing one or more storage elements.
`Certain storage elements may be programmed solely by the
`manufacturer preferably While the integrated circuit remains
`a part of a semiconductor Wafer. A unique set of product
`engineering (“PE”) bits are programmed by the manufac
`turer into those storage elements Within an address space
`Which the customer or end user Will not access during
`normal operation of the integrated circuit.
`The PE bits contain information as to a particular hard
`Ware revision used to produce the integrated circuit embody
`ing the storage elements. The PE bits are addressed prefer
`ably during tests of die Within a Wafer. Viability of the die
`may be tested at the same time at Which the PE bits are
`programmed. Thus, the PE bits can be programmed as early
`as Wafer engineering tests immediately subsequent to Wafer
`manufacture, or as late as partial, functional and parametric
`tests performed immediately prior to scribing the Wafer and
`removing viable die for assembly.
`Each die across the Wafer contains PE bits programmed
`With a speci?c hardWare revision used to produce that Wafer.
`The PE bits therefore contain parameters used in manufac
`turing that Wafer or possibly numerous Wafers Within a
`Wafer lot. Thus, a hardWare revision is stored as PE bits
`Within the storage elements reserved for those bits.
`The stored hardWare revision number can either be one
`Which is quali?ed or non-quali?ed. If quali?ed for release to
`a customer, a ?nal test operation post-assembly Will ascer
`tain this fact and alloW all quali?ed integrated circuits to be
`shipped. HoWever, if the revision number indicates a non
`quali?ed (e.g., experimental) revision number indicative of
`an experiment used in forming that integrated circuit, then
`the assembled integrated circuit Will be held in storage or
`scrapped. Not until the non-quali?ed revision is updated to
`a quali?ed revision Will that integrated circuit containing
`programmed, non-quali?ed PE bits ship to a customer.
`The PE bits and, speci?cally, the storage elements dedi
`cated to receive the PE bits, prove important in ensuring that
`non-quali?ed product does not ship to a customer. Program
`ming occurs prior to Wafer scribe so that traceability to a
`particular manufactured Wafer can be achieved. Reading the
`programmed PE bit locations occurs at various test stages
`and certainly during ?nal tests. The tester reads the pro
`grammed PE bits from the integrated circuits and compares
`those bits against a benchmark bit sequence. If the pro
`grammed PE bits differ from the benchmark bits, then the
`tester Will indicate the integrated circuit is to be sent to a
`particular bin and not shipped to a customer.
`Broadly speaking, the present invention concerns an
`integrated circuit. The integrated circuit comprises a non
`volatile storage element formed in an address location
`reserved for receiving information as to Whether the inte
`grated circuit is suitable for shipment from the integrated
`circuit manufacturer. The address location is deemed inac
`cessible during normal operation of the integrated circuit,
`and the information received by the storage element com
`
`10
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`15
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`4
`prises indicia as to a hardWare revision of that integrated
`circuit. The storage element preferably receives the infor
`mation or indicia as a PE bit prior to assembling the
`integrated circuit in a package. The packaged integrated
`circuit is prevented from shipment if tests performed prior to
`shipment indicate the assembled integrated circuit contains
`PE bits indicative of a non-quali?ed revision.
`The present invention further concerns an apparatus for
`programming an integrated circuit. The apparatus includes a
`programming mechanism adapted for Writing at least one bit
`of information into at least one storage element on the
`integrated circuit. The hardWare revision information is
`attributable to the manufacture of the integrated circuit at a
`time in Which the integrated is traceable to a particular Wafer
`and Wafer lot. A reading mechanism is also included, and is
`adapted for reading the programmed information from the
`storage element to determine if the integrated circuit is
`quali?ed for release by the integrated circuit manufacturer.
`The present invention further concerns a method for
`determining if an integrated circuit is suitable for release
`from the manufacturer. The method includes Writing elec
`tronic indicia into storage locations on the integrated circuit.
`The indicia corresponds to parameters used in the manufac
`ture of the integrated circuit and is generally classi?ed as a
`particular hardWare revision number stored Within the stor
`age location or locations. Thus, electronic indicia represents
`a particular hardWare revision number from among possibly
`numerous hardWare revisions that can be used to produce the
`integrated circuit. The Written indicia (or PE bits) can be
`read during testing of the integrated circuit to determine if
`the read hardWare revision indicates the integrated circuit is
`suitable for release from the manufacturer.
`
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`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Other objects and advantages of the invention Will
`become apparent upon reading the folloWing detailed
`description and upon reference to the accompanying draW
`ings in Which:
`FIG. 1 is a plan vieW of an integrated circuit eXtracted
`from a speci?c Wafer and Wafer lot, Wherein the integrated
`circuit is shoWn to contain storage locations dedicated to
`receiving product engineering bits arranged according to one
`embodiment;
`FIG. 2 is a plan vieW of an integrated circuit eXtracted
`from a speci?c Wafer and Wafer lot, Wherein the integrated
`circuit is shoWn to contain storage locations dedicated to
`receiving product engineering bits arranged according to
`another embodiment;
`FIG. 3 is a memory address space Which includes an
`address location reserved for receiving the product engi
`neering bits used to identify information pertinent to the
`manufacture and program of the integrated circuit;
`FIG. 4 is a ?oW diagram of operations used to
`manufacture, test, assemble and program the integrated
`circuit, to attribute information about the integrated circuit
`hardWare being shipped, to attribute information about the
`softWare used to program the integrated circuit, and/or to
`determine compatibility betWeen the shipped hardWare and
`the program softWare; and
`FIG. 5 is a plan vieW of comparator circuitry used to
`determine compatibility betWeen the shipped hardWare and
`the program softWare.
`While the invention may be modi?ed and have alternative
`forms, speci?c embodiments thereof are shoWn by Way of
`eXample in the draWings and Will herein be described in
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`Page 6 of 10
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`6,052,319
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`5
`detail. It should be understood, however, that the drawings
`and detailed description thereto are not intended to limit the
`invention to the particular form disclosed, but on the
`contrary, the intention is to cover all modi?cations, equiva
`lents and alternatives falling Within the spirit and scope of
`the present invention as de?ned by the appended claims.
`
`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENTS
`
`Turning noW to the draWings, FIG. 1 illustrates numerous
`Wafers 12 Within a Wafer lot 14. An integrated circuit or die
`16 may be derived from a particular location of Wafer 12.
`Wafer lot 14 contains numerous Wafers only one of Which is
`shoWn as Wafer 12. Integrated circuit 16 can be derived from
`many locations of Wafer 12, or from the various other Wafers
`Within Wafer lot 14. Merely as an example, integrated circuit
`16 is draWn from the location shoWn, and is presented in a
`detailed, plan vieW as having a core section 18 and a decode
`unit 20.
`Core section 18 may include an array of memory
`elements, at least some of Which are non-volatile. According
`to one example, at least one storage element can be arranged
`Within a storage location 22 outside core 18. Storage loca
`tion 22 comprises at least one storage element and,
`preferably, as many storage elements as are needed to store
`a particular hardWare revision used in producing integrated
`circuit 16.
`An address and/or data interface 20 receives address and
`data information and accesses core 18 separate from storage
`location 22. Preferably, core 18 is accessed during normal
`operation of integrated circuit 16, Whereas storage location
`22 is inaccessible at times in Which integrated circuit 16 is
`operating. Storage location 22 can be addressed and data
`placed into or from one or more PE bit locations only by the
`manufacturer (if hardWare revisions are Written) or by a
`programmer (if softWare revisions are Written). The combi
`nation of hardWare and softWare revisions helps track the
`particular revision history of the integrated circuit. The PE
`bits stored in location 22 Will not be called upon or used to
`carry out the operation or functionality of integrated circuit
`16. Thus, the user of integrated circuit 16 Will generally not
`knoW that storage location 22 exists or that location 22
`contains PE bits, or the function of those PE bits.
`Decode unit 20 decodes a speci?c address of core 18 to
`carry out the functionality of circuit 16. Address and data
`buses extend betWeen decode unit 20, core 18 and storage
`location 22. HoWever, decode unit 20 addresses from an
`altogether dissimilar address space from that Which accesses
`core 18 storage elements.
`FIG. 2 illustrates the possibility that integrated circuit 36
`can be draWn from another Wafer such as Wafer 32 of Wafer
`lot 34. Integrated circuit 36 is shoWn in plan vieW as
`containing a storage location 42 Within core 38. Contrary to
`the embodiment shoWn in FIG. 1, storage location 42 may
`form a part of the array of memory elements Within core 38.
`Regardless of Whether the storage locations 22/42 are physi
`cally Within the con?nes of the memory array or outside the
`memory array, or Whether the integrated circuit 16/36 is
`draWn from a ?rst, second, etc. Wafer Within a particular
`Wafer lot, the storage location reserved for PE bits remains
`inaccessible during normal operations of the integrated
`circuit. The address/data decoder 20/40, shoWn according to
`alternative embodiments, addresses memory Within the core
`separate from the PE bits stored Within the storage locations.
`The number of conductors Which form the address or data
`bus can vary depending, for example, on the number of PE
`
`10
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`bits needed to indicate the hardWare or softWare revisions
`Which they represent.
`Referring to FIG. 3, some of the information Which can be
`stored Within the storage elements of location 22/42 are
`shoWn. According to one embodiment, the address decoder
`of FIGS. 1 and 2 can accommodate an address space 50. A
`majority of address space 50 is used to program operation of
`the integrated circuit, or other integrated circuits operably
`linked thereto. HoWever, a subset 52 of address space 50 is
`reserved for receiving manufacturing and softWare program
`ming indicia.
`According to one embodiment, subset 52 can be
`addressed to contain any and all manufacturing data embod
`ied upon the integrated circuit and pertinent to parameters
`used in manufacturing the integrated circuit. Those param
`eters being the hardWare revision number. Subset 52 can be
`found as possibly a contiguous space or bifurcated into
`multiple address locations Within address space 50. Subset
`address space 52 can be of ?xed siZe for a particular
`integrated circuit post-manufacture, or can be variable in
`siZe depending on the number of address locations desired.
`For example, at least one address location 54 Within space
`52 may be used to uniquely identify the parameters involved
`in producing, e.g., revision number ?ve of the integrated
`circuit. Thus, address location 54 may contain all informa
`tion needed to identify a particular hardWare revision of the
`produced integrated circuit. Manufacturing information at
`location 54 can be stored in a number of storage elements
`N1, each storage element accommodating the PE bit Which
`indicates a unique product (or hardWare) revision number
`56. For example, if bits N1=8, then there are possibly 28, or
`256 different hardWare revision numbers Which can be
`identi?ed at location 56. Any change Whatsoever in the
`processing recipe, equipment and/or layout of the integrated
`circuit Will be re?ected as a speci?c revision number and
`encoded as one of the possible 256 revisions upon the
`integrated circuit thusly formed. Merely as an example, if
`the sputter tool has been modi?ed to deposit a thicker
`conductive material, or thermal cycles extended, etc., then
`the resulting product Will be identi?ed With a unique revi
`sion number and coded With PE bits at location 56.
`In addition to hardWare revisions, softWare revisions can
`also be stored in subset 52. For example, numerous softWare
`programs, or slightly changed versions of the same softWare
`can program a programmable integrated circuit. For the
`same reasons that hardWare revisions must be kept track of,
`softWare revisions must also be monitored and Written into
`subset address space 52. For example, if address location 54
`can accommodate N2 storage elements dedicated to soft
`Ware revisions, then a total of 2N2 possible softWare revi
`sions can be stored. The same applies for the programming
`tool Which imputes the particular softWare program onto the
`integrated circuit memory. The program tool may be manu
`factured by numerous vendors, each of Which must be kept
`track of in relation to the softWare and hardWare revisions.
`The storage locations dedicated to receiving N3 PE bits
`indicative of a programming tool is shoWn as reference
`numeral 60. The storage location reserved for receiving the
`PE bits containing the softWare revision number is shoWn as
`reference numeral 58.
`Information as to a particular processing recipe or layout
`can be represented as a unique binary value of 1s and 0s,
`similar to the softWare revision number and the particular
`programming tool Which is used to program the integrated
`circuit. All three forms of information are Written to the
`integrated circuit storage location at speci?c times and then
`later read to determine compatibility. According to another
`
`Page 7 of 10
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`

`
`6,052,319
`
`7
`embodiment, the hardware revision can be Written and later
`read to determine if that particular revision is quali?ed for
`release to a customer. Therefore, depending on the applica
`tion or needs of the integrated circuit manufacturer, a portion
`of the stored PE bits Within space 52, or the entire sequence
`of PE bits in space 52 can be read. The number of bits
`needed to take into account all the potential hardWare
`revisions, softWare revisions, and in-the-?eld programming
`tools can vary depending on the number of potential revi
`sions and programming tools.
`The hardWare revision number 56 is Written at a time
`dissimilar from When the softWare revision number 58 is
`Written. In fact, in certain applications, the softWare revision
`number need not be Written When only the hardWare revision
`number is needed. Typically, the hardWare revision number
`56 is Written at a time When the integrated circuit is
`associated With the Wafer or Wafer lot from Which it is
`manufactured. In this manner, manufacturing indicia such as
`hoW, When, Where, etc. the integrated circuit Was manufac
`tured can be stored before the integrated circuit is removed
`from the Wafer of interest. Thus, since manufacturing infor
`mation is generally attributed to a Wafer and not an inte
`grated circuit, the integrated circuit must receive that infor
`mation When it is attributable to a Wafer or Wafer lot.
`Reading the programmed information occurs after the inte
`grated circuit is removed from the Wafer and is typically
`assembled into an encapsulated, packaged product. More
`speci?cally, reading the hardWare information may occur
`before or after the packaged integrated circuit is shipped to
`a customer. In one example, the hardWare revision number
`is read prior to shipment to screen non-quali?ed product
`from shipment. According to an alternative embodiment, the
`hardWare revision number is read after shipment, along With
`the softWare revision number. The combination of hardWare
`and softWare revision numbers proves bene?cial in inform
`ing the manufacturer or customer of an incompatible hard
`Ware and softWare combination.
`Turning to FIG. 4, an example How diagram is illustrated
`as to When hardWare and softWare revision numbers can be
`programmed and thereafter read. Speci?cally, FIG. 4 illus
`trates a sequence of operations 70 undertaken by a manu
`facturer and user of an integrated circuit. FloW 70 begins by
`fabricating a Wafer 72 containing a plurality of die, chips or
`integrated circuits. Engineering tests 74 can be conducted on
`test devices at select locations across one or more Wafers
`Within a Wafer lot. Providing the engineering tests 74
`roughly indicate positive results, then each die of every
`Wafer can then be tested 76 at SORTl. SORTl can include
`parametric and functional testing as Well as visual inspec
`tion. Electrical testing includes probing the bond pads of
`each die to ascertain Whether the die meets a limited number
`of performance points. During SORTl, storage elements
`Within a storage location Which is not called upon during
`normal operation may be programmed at step 78. Program
`ming the storage location With PE bits requires accessing
`subset 54 of the entire address space 50 (shoWn in FIG. 3).
`Once the non-volatile memory elements are programmed,
`then each Wafer may be subjected to a high thermal cycle,
`generally referred to as a bake cycle 80. Each die can
`thereafter be subjected to another sort test 82, referred to as
`SORT2. SORT2 may contain many tests Which are substan
`tially identical to those used as SORTl. Instead of program
`ming the storage location dedicated to PE bits at step 78,
`programming can occur at sort2 via step 84. Alternatively,
`programming may occur at both steps 78 and 84, With
`possibly different manufacturing indicia provided at each
`program operation. All die Which fail SORT2 tests 82 are
`
`10
`
`15
`
`25
`
`35
`
`45
`
`55
`
`65
`
`8
`marked With a visually-identi?able marking, such as an ink
`dot. Die Which are electrically and visually viable are then
`passed to an assembly operation 86.
`Assembly 86 involves placing die Which pass die-probe
`tests (SORTl and SORT2) into a package and then sealing
`that package using various Well-knoWn techniques. The
`connection betWeen the bond pads upon the viable die to
`leads extending from the package occur during assembly
`operation 86.
`Testing the assembled product may involve testing at
`various temperatures. For example, the tests may be the
`same as or more extensive than that used during SORTl and
`SORT2. Testing can occur at different temperatures, or can
`be separated by a high temperature cycle often referred to as
`“burn-in”. The post-assembly tests are shoWn as reference
`numerals 88 and 90, possibly separated by the burn-in cycle
`92. The temperatures used, and the tests speci?ed depend on
`customer demands. Possibly during each test, the storage
`locations programmed during step 78 and/or 84 can be read
`at steps 93 and/or 94. For example, a unique die pro
`grammed With a particular revision of hardWare at step 78
`can be traced to test procedure 88 and read at step 93. Any
`skeW in the operational characteristics of that die can be
`monitored for the particular manufacturing revision used to
`produce that die. The importance in providing speci?c
`details of hoW, When, and Where a die arises as Well as hoW,
`When, and Where a die is manufactured, etc. can be read after
`assembly or even after the die is shipped to a customer in
`order to correlate the read parameters back to the die under
`possibly numerous operating temperatures and conditions.
`Once the assembled die is tested, the packaged product
`can then be marked With customer and/or vendor identi?
`cation at step 96. Thereafter, the packaged product can be
`?nally tested at a quality assurance step 98. Quali?cation test
`98 may involve an additional reading of programmed or
`“imprinted” manufacturing indicia (i.e., hardWare revision
`number) at step 100. That Which passes the quali?cation test
`98 can then be shipped to a customer at step 102 provided
`the revision number read at step 100 is a “quali?ed” revi
`sion. If the hardWare revision number is not quali?ed, then
`tests 98 Will indicate that fact and prevent the product from
`shipping. The non-quali?ed product can be placed in a
`staging area 104. Staging area 104 is an inventory control
`area at the manufacturers site, Where non-quali?ed product
`is stored and categoriZed.
`Non-quali?ed product includes any and all product Which
`has not passed manufacturers scrutiny for shipment to a
`customer. This includes product Which is manufactured as
`experimental Waf