Case IPR2016-1246
`U.S. Patent No. 7,126,174
`
`Filed on behalf of Godo Kaisha IP Bridge 1
`
`By: Neil F. Greenblum (ngreenblum@gbpatent.com)
`Greenblum & Bernstein, P.L.C.
`1950 Roland Clarke Place
`Reston, VA 20191
`Tel: 703-716-1191
`Fax: 703-716-1180
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Case IPR2016-01246
`U.S. Patent No. 7,126,174
`____________
`
`DECLARATION OF DR. E. FRED SCHUBERT, PH.D. IN SUPPORT OF
`PATENT OWNER’S PRELIMINARY RESPONSE
`
`Page 1 of 73
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`Case IPR2016-1246
`U.S. Patent No. 7,126,174
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`TABLE OF CONTENTS
`
`Introduction..............................................................................................................4
`Summary of Opinions..............................................................................................4
`Background and Qualifications..............................................................................6
`Previous Expert Witness Experience......................................................................6
`Compensation .........................................................................................................6
`Background.............................................................................................................7
`Materials Reviewed................................................................................................11
`Legal Standards......................................................................................................11
`Technological Background....................................................................................13
`Acronyms..............................................................................................................13
`Silicon integrated circuit (IC) processing.............................................................13
`Electrical isolation in silicon integrated circuit wafers ........................................23
`Differences between LOCOS isolation and Trench isolation ..............................30
`LOCOS isolation and Trench isolation are not functionally equivalent ..............32
`Difficulty of employing STI on wafers having a non-planar topology................35
`Benefits of the claimed features of the ’174 patent and their synergies ..............38
`Synergies arising from use of L-shaped sidewalls and trench isolation ..............43
`Prior Art..................................................................................................................45
`U.S. Patent No. 5,153,145 (“Lee”) .......................................................................45
`U.S. Patent No. 5,539,229 (“Noble”) ...................................................................47
`U.S. Patent No. 4,506,434 (“Ogawa”) .................................................................49
`Combination: Lee & Noble....................................................................................51
`The initial processing sequence of Noble is opposite from Lee...........................51
`Lee and Noble processes are not compatible........................................................57
`Lee-Noble rejection fails on further grounds........................................................61
`There is No Disclosure Of How L-Shaped Sidewalls Can Be Formed............61
`Salicidation of Lee.............................................................................................62
`Conclusions regarding the Lee-Noble combination .............................................63
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`Combination: Lee & Ogawa ..................................................................................64
`Initial Processing Sequence of Ogawa Is Opposite From Lee.............................64
`Lee and Ogawa processes are not compatible......................................................67
`Conclusions regarding the Lee-Ogawa combination ...........................................72
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`Case IPR2016-1246
`U.S. Patent No. 7,126,174
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`I, E. Fred Schubert, declare as follows:
`
`Introduction
`
`1.
`
`My name is Dr. E. Fred Schubert. I have been asked to submit this
`
`declaration on behalf of Godo Kaisha IP Bridge 1 (“IP Bridge” or “Patent Owner”)
`
`in connection with a Petition for Inter Partes Review of U.S. Patent No. 7,126,174
`
`(“the ’174 patent”), which I understand was submitted to the Patent Trial and
`
`Appeal Board of the United States Patent and Trademark Office by petitioner
`
`Taiwan Semiconductor Manufacturing Company Ltd. (“TSMC”).
`
`2.
`
`I have been retained as a technical expert by IP Bridge to study and
`
`provide my opinions on the technology claimed in, and the patentability or non-
`
`patentability of, claims 1-3, 5-7, 9-12, and 14-18 in the ’174 patent (“the
`
`Challenged Claims”).
`
`3.
`
`I understand the ’174 patent is related to U.S. Patent Nos. 6,967,409
`
`(the ’409 patent), 6,709,950 (the ’950 patent), and 6,281,562 (the ’562 patent) and
`
`also claims the benefit of priority to two Japanese applications, JP 7-192181,
`
`which was filed on July 27, 1995, and JP 7-330112, which was filed on December
`
`19, 1995.
`
`Summary of Opinions
`
`4.
`
`I have reviewed the ’174 patent, associated prior art, the TSMC
`
`Petition, the Declaration of Dr. Banerjee, as well as references cited therein. I
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`understand that the Petitioner and its expert, Dr. Banerjee, express the following
`
`contentions:
`
`5.
`
`First, Petitioner and its expert contend that LOCOS isolation and
`
`trench isolation are interchangeable and one could easily substitute LOCOS
`
`isolation with trench isolation.
`
`6.
`
`Second, Petitioner and its expert offer two combinations, (1) Lee and
`
`Noble as well as (2) Lee and Ogawa, and contend that the substitution of Lee’s
`
`LOCOS isolation with either Noble’s or Ogawa’s trench isolation would result in
`
`the claimed invention of the ’174 patent.
`
`7.
`
`Based on my experience and knowledge in the field and based on my
`
`review of the documents, I express my opinions as follows:
`
`8.
`
`First, it is my opinion that LOCOS isolation and trench isolation are
`
`substantially different structures thereby requiring that their fabrication processes
`
`as well as the processes that they are integrated into must be modified substantially
`
`when transitioning from LOCOS isolation to trench isolation.
`
`9.
`
`Second, it is my opinion that a simple substitution of LOCOS isolation
`
`with trench isolation, without a detailed re-engineering of a fabrication process, is
`
`not obvious, not possible, and if done nonetheless, would result in a non-working
`
`Si IC device.
`
`10. Accordingly, it is my opinion that the ’174 patent is not obvious based
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`on the prior art asserted by Petitioner and its expert. That is, the ’174 patent is not
`
`obviated by the Lee + Noble combination and not obviated by the Lee + Ogawa
`
`combination.
`
`Background and Qualifications
`
`Previous Expert Witness Experience
`
`11.
`
`I have served as a technical expert witness since the late 1990s. My
`
`expert activity included semiconductor materials, processing, devices, packaging,
`
`and systems. I have worked on behalf of Plaintiffs and Defendants, on behalf of
`
`domestic companies and foreign companies, and in proceedings at the USPTO
`
`(including inter partes reviews), District Court, and the International Trade
`
`Commission (ITC). My work included mostly utility patent cases, but also
`
`included a design patent case, a case of alleged misappropriation of a trade secret,
`
`and a case of alleged mishandling of a patent application.
`
`Compensation
`
`12.
`
`I am compensated at my customary rate of $500 per hour1 worked on
`
`the case plus reasonable and customary expenses. My compensation does not
`
`depend of the outcome of the inter partes review.
`
`1 This fee applies when working directly with the client. When working through an
`
`agent, the fee for my services is $650.00 per hour.
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`Background
`
`13.
`
`I am currently a Professor in the Department for Electrical, Computer,
`
`and Systems Engineering at the Rensselaer Polytechnic Institute (RPI) located in
`
`Troy, New York.
`
`14.
`
`I received a Master’s Degree in Electrical Engineering from the
`
`University of Stuttgart, Germany, in 1981. I received a Ph.D. degree in Electrical
`
`Engineering from the University of Stuttgart, Germany, in 1986. My dissertation
`
`was titled “Modern Schottky Gate Field Effect Transistor Devices Made of III-V
`
`Semiconductors.” Subsequent to my education, starting in 1985, I worked in
`
`industry, at AT&T Bell Laboratories in Holmdel and Murray Hill, New Jersey, for
`
`ten years. The transistor was invented at Bell Labs (in 1949) and Bell Labs was
`
`subsequently recognized as one of the world’s premier industrial research
`
`laboratories. In 1995, I joined academia. My first position was at Boston
`
`University (Boston MA) where I worked as a full professor for seven years. In
`
`2002, I joined RPI (Rensselaer Polytechnic Institute) as a distinguished professor,
`
`the Wellfleet Senior Constellation Professor, with appointments in the Department
`
`for Electrical, Computer, and Systems Engineering and the Department for
`
`Physics, Applied Physics, and Astronomy. I served as Head of the Future Chips
`
`Constellation from 2002 to 2015. Furthermore, I am the founding Director of the
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`Smart Lighting Engineering Research Center, which is funded by the US National
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`Science Foundation at $40 million over 10 years.
`
`15.
`
`I am co-inventor of more than 30 U.S. patents and have co-authored
`
`more than 300 publications. I authored the books “Doping in III–V
`
`Semiconductors” (1993), “Delta Doping of Semiconductors” (1996), and the first
`
`and second editions of “Light-Emitting Diodes” (2003 and 2006). My publications
`
`have been well recognized by the technical community as illustrated by the more
`
`than 25,000 citations that my publications have received. The high number of
`
`citations shows the recognition of my research accomplishments and puts me in the
`
`top 1% of researchers in the field of semiconductors.
`
`16.
`
`I have received several awards for my technical contributions. They
`
`include: Senior Member IEEE (1993); Literature Prize of Verein Deutscher
`
`Elektrotechniker for book “Doping in III–V semiconductors” (1994); Fellow SPIE
`
`(1999); Alexander von Humboldt Senior Research Award (1999); Fellow IEEE
`
`(1999); Fellow OSA (2000); Boston University Provost Innovation Award (2000);
`
`Discover Magazine Award for Technological Innovation (2000); R&D 100 Award
`
`for RCLED (2001); Fellow APS (2001); RPI Trustees Award for Faculty
`
`Achievement (2002 and 2008); Honorary membership in Eta Kappa Nu (2004); 25
`
`Most Innovative Micro- and Nano-Products of the Year Award of R&D Magazine
`
`(2007); and the Scientific American 50 Award (2007).
`
`17. My general expertise is in the field of electrical engineering and
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`applied physics with a particular emphasis on semiconductor materials,
`
`semiconductor processing, semiconductor devices, and semiconductor device
`
`packaging. I have worked in semiconductor processing facilities, including
`
`facilities dedicated to silicon integrated circuit (IC) processing, for many years
`
`starting in 1980. I have numerous documented contributions to the field of
`
`semiconductor doping including the fabrication and analysis of ultra-shallow
`
`junctions in silicon, including delta-function-like doping profiles that are deposited
`
`with near-atomic precision. These doping profiles are more precise than what is
`
`currently attainable with ion implantation. At the present time, doping by ion
`
`implantation is the dominant doping technique in the silicon IC industry.
`
`18.
`
`Furthermore, I have made pioneering contributions to the field of
`
`porous silica thin films (porous SiO2 thin films) deposited by oblique-angle
`
`deposition. These highly porous silica films, whose porosity can be as high as
`
`90%, are highly desirable for high-speed interconnects in silicon ICs due to the low
`
`dielectric constant of these materials and the resulting low capacitance of
`
`interconnect wires using interlayer dielectrics made of porous silica. My research
`
`also included the theoretical study, experimental verification, and the application
`
`of the piezo-resistive coefficients of thin silicon membranes that are subjected to a
`
`mechanical stress and strain.
`
`19. At my home institution, Rensselaer Polytechnic Institute (RPI), I
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`teach on the subject of silicon microelectronics on a regular basis. The teaching
`
`includes undergraduate and graduate courses. The subject matter includes silicon
`
`metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary
`
`metal-oxide-semiconductor (CMOS) technology, constant-electric-field scaling,
`
`the theory of transistors and integrated circuits, and the fabrication of integrated
`
`circuits. I am well versed in the theory and the physics of semiconductor devices
`
`and associated electrical circuits. In addition, I regularly work with students and
`
`clean-room staff of a silicon microfabrication clean room facility at my home
`
`institution (RPI). Several of my former Ph.D. and Master students work in the
`
`silicon integrated circuit industry including the following companies: IBM
`
`Company in Fishkill NY, Global Foundry Company in Malta NY, Albany
`
`Nanotech in Albany NY, Micron Company in Boise Idaho, and Intel Company in
`
`Boise Idaho.
`
`20. My experience includes the operation, modeling, driving, design,
`
`fabrication, and analysis of solid-state devices and integrated electrical circuits. I
`
`am the inventor on patents that concern silicon semiconductor devices, including
`
`the doping of silicon.
`
`21.
`
`I have consulted for companies in the semiconductor industry,
`
`including the semiconductor processing industry. Specifically, I have consulted for
`
`Varian Company in Gloucester, Massachusetts (now part of Applied Materials
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`Company) and for Micron Technologies in Boise, Idaho. In my capacity as a
`
`consultant, I have visited these companies multiple times and on a regular basis.
`
`My consulting has allowed the companies to enhance their understanding of
`
`semiconductor devices and take advantage of the technological advancements
`
`made in academia including my research laboratory and the microfabrication
`
`facility at RPI. More details about my experience and background are included in
`
`my curriculum vitae, attached as Exhibit A to this declaration.
`
`Materials Reviewed
`
`22.
`
`I have reviewed the following documents:
`The ’174 patent and its file history
` US patent 6,281,562 and its file history
` US patent 6,709,950 and its file history
` US patent 6,967,409 and its file history
`The TSMC Petition and reference articles cited therein
` Dr. Banerjee’s expert declaration and reference articles cited therein
` Various technical articles
`
`Legal Standards
`
`23.
`
`I am not a lawyer. Counsel for IP Bridge has advised me regarding the
`
`legal principles governing patent law. Based on counsel’s advice, my
`
`understanding is as follows below.
`
`24.
`
`In an IPR proceeding the Petitioner has the initial burden of
`
`persuasion to establish a reasonable likelihood that at least one claim of an issued
`
`patent are unpatentable, and this burden remains throughout the entire proceeding
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`(In re: Magnum Oil Tools, p. 20-30).
`
`25.
`
`Petitioner must provide an analysis of how or why an element from a
`
`prior art teaching could be combined with the teaching of another reference
`
`Magnum, at p. 30).
`
`26. Without any direction by Petitioner how or why a feature is to be
`
`combined, a naked assertion that such would be within the skill of a POSITA is not
`
`enough to establish a reasonable likelihood that at least one claim of an issued
`
`patent is unpatentable in an IPR proceeding.
`
`27. Although the POSITA is entitled to use “common sense” to arrive at
`
`the conclusion that the claimed invention is obvious, the POSITA must provide a
`
`reasoned explanation that avoids conclusory generalizations (Arendi v. Apple, p.
`
`19).
`
`28. An assertion of invalidity cannot be based merely on conclusory
`
`statements when dealing with prior art, but must set forth the rationale on which it
`
`relies (In Re Warsaw, p. 14).
`
`29.
`
`For an invention to be obvious it is not enough that there be a reason
`
`to combine individual elements from different prior art references; the person of
`
`ordinary skill in the art (POSITA) must also be in possession of sufficient
`
`knowledge to know how to incorporate features from one reference into the other
`
`reference.
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`30.
`
`Petitioner’s expert relies on the following Legal Standard:
`
`A person of ordinary skill often will be able to fit the teachings of
`multiple references together like a puzzle;
`
`Exhibit 1004, ¶37(f).
`
`31.
`
`I do not understand this to be a generalized starting point in every
`
`analysis because it entirely fails to take into account the specific technology and
`
`the specific documents being relied upon and which are being combined.
`
`Technological Background
`
`Acronyms
`
`32.
`
`For convenience, I list some acronyms that are commonly used in the
`
`field of Si IC technology:
`
`=
`BEOL
`CMOS =
`CMP
`=
`CVD
`=
`FEOL
`=
`FET
`=
`IC
`=
`LOCOS =
`MOS
`=
`PVD
`=
`S, D, G =
`STI
`=
`TSMC =
`
`Back end of line (interconnect metallization fabrication)
`Complementary MOS
`Chemical mechanical planarization (or polishing)
`Chemical vapor deposition
`Front end of line (transistor and local interconnect fabrication)
`Field-effect transistor
`Integrated circuit
`Local oxidation of silicon
`Metal oxide semiconductor
`Physical vapor deposition
`Source, Drain, Gate (respectively)
`Shallow trench isolation
`Taiwan Semiconductor Manufacturing Company (Petitioner)
`
`Silicon integrated circuit (IC) processing
`
`33.
`
`Si integrated circuits (ICs) are highly complex electrical systems on a
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`small microstructured chip. An integrated circuit can have millions of transistors
`
`that serve to process, store, and transport information. ICs consist of different
`
`units, e.g. a data processing unit for processing information, a memory unit for
`
`storing information, and an input / output unit for receiving and sending
`
`information.
`
`34.
`
`The core element of an integrated circuit is a transistor, specifically
`
`the field-effect transistor (FET) that uses an electric field (“field effect”) in order to
`
`create charge carriers in the transistor’s channel region. The channel region
`
`connects the transistor’s source (S) with the transistor’s drain (D). The source and
`
`drain are separated by the gate (G) that controls the flow of charge in the channel
`
`between the source and drain.
`
`35.
`
`The transistor’s gate has a typical three-layer stack consisting of a
`
`metal or metal-like material (M), an insulator or oxide (O), and a semiconductor
`
`(S), thereby forming the MOS layer stack, gate layer stack, or simply gate stack.
`
`Accordingly, transistors based on the MOS stack are called MOSFETs.
`
`36.
`
`There are two types of transistors, those using negative electrons in
`
`the channel (n-channel FET) and those using positive holes in the channel (p-
`
`channel FET). The two types of transistors have complementary properties. For
`
`example, a positive gate voltage induces an electron channel in an n-channel FET
`
`whereas a negative gate voltage induces a hole channel in a p-channel FET. If a
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`single voltage is applied simultaneously to the two gates of the two types of
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`transistors, one of them will conduct electricity (ON state) whereas the other one
`
`will not conduct electricity (OFF state). Due to the complementary nature of the
`
`two types of transistors, the technology is referred to as complementary MOS
`
`technology or simply CMOS technology. At the present time, the vast majority of
`
`ICs are based on CMOS technology.
`
`37.
`
`The circuit layout is the result of (i) the circuit functionality designed
`
`by design engineers and (ii) how the designed circuit is implemented by a
`
`processing sequence devised by process engineers.
`
`38.
`
`The processing sequence is carried out in a fabrication facility, also
`
`abbreviated as “fab” or “IC fab”. Such fabrication facilities are highly advanced
`
`facilities that are highly automated so that the handling of Si wafers by humans is
`
`minimal. Regarding the processing sequence, we distinguish between a first group
`
`of fabrication processes called front end of line (FEOL) processes and a second
`
`group of fabrication processes called back end of line (BEOL) processes. The
`
`FEOL processes include the fabrication of the actual transistors (MOSFETS)
`
`including the silicidation of source, gate, and drain. The BEOL processes include
`
`the fabrication of metal-based interconnect lines and associated dielectric layers
`
`(interlayer dielectrics) that electrically insulate the metal interconnects from each
`
`other.
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`39. Hallmarks of IC processing include (i) high spatial precision by means
`
`of lithography (to attain very small patterns with sub- m feature sizes) and
`
`(ii) cleanliness (to avoid contaminations).
`
`40.
`
`The processing of wafers proceeds in a strict sequence of processing
`
`steps that are carefully chosen in sequence and content. For example, the gate
`
`stack of a transistor requires the availability of a Si substrate, followed by the
`
`deposition or growth of the gate dielectric (commonly an oxide), and followed by
`
`the deposition of the gate electrode. This processing sequence is mandatory and it
`
`cannot be done through another sequence.
`
`41.
`
`Furthermore, certain elements of an IC require the preexistence of
`
`other elements and rely on their presence for the proper functioning of the
`
`ensemble of elements. For example, the source / drain dopant implant requires the
`
`presence of the gate electrode so that the gate can mask the channel region from
`
`the implantation ion beam. That is, the gate enables the proper definition of the
`
`source / drain implanted regions. An implantation in which the source / drain
`
`regions are automatically aligned with the gate electrode is referred to as a “self-
`
`aligned implantation process”.
`
`42.
`
`It is generally not possible to reverse the sequence of processing steps.
`
`A series of individual processing steps constitute a “processing module”. For
`
`example, the formation of shallow trench isolation is such a processing module
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`with (i) trench etching, (ii) trench refill with silicon dioxide and (iii) planarization
`
`being the major steps of the module.
`
`43.
`
`In addition to the major steps of trench formation, there are minor
`
`steps not listed above. A more complete series of steps employed for trench
`
`formation may include: oxide pad deposition; nitride pad deposition; resist coating;
`
`photo lithography; nitride etching; oxide etching; trench etching by means of a dry
`
`etch; resist strip; liner-oxide growth; trench refill with CVD silicon dioxide;
`
`annealing to improve quality of oxide; planarization by CMP (chemical
`
`mechanical planarization); various cleaning steps and rinsing steps are used
`
`throughout the module (major steps emphasized).
`
`44.
`
`Each processing step (or processing module) is intended and works
`
`for a specific initial configuration of the Si wafer. Upon completion of the
`
`processing step (or processing module), the Si wafer has a new, final configuration.
`
`45.
`
`That is, each processing step (within a processing module) transforms
`
`the Si wafer from an initial configuration to a final configuration associated with
`
`this processing step.
`
`46.
`
`Likewise, each processing module (with each processing module
`
`consisting of a sequence of processing steps) transforms the Si wafer from an
`
`initial configuration to a final configuration associated with this processing
`
`module.
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`47. When taking a specific processing step (within one processing
`
`module) out of its intended sequence and inserting it at another point in the
`
`sequence of processing steps, one must ensure the following: First, the sequence of
`
`processing steps preceding the specific processing step must provide an initial
`
`configuration compatible with the specific processing step. Second, the final
`
`configuration resulting from the specific processing step must be compatible with
`
`the subsequent processing step and beyond.
`
`48.
`
`In other words, the initial and final configuration of a wafer associated
`
`with a specific processing step must be compatible with the entire fabrication
`
`process. As would be understood by a POSITA, a random change in the sequence
`
`in processing steps would not lead to the desired result; if done nonetheless, it will
`
`likely lead to a non-functioning IC device. Changing the sequence of processing
`
`steps requires that the fabrication process be re-engineered, e.g. the entire front-
`
`end-of-line (FEOL) fabrication process may need to be re-engineered. This
`
`elucidates that the fabrication of an IC device is based on a specific sequence of
`
`processing steps that cannot be changed at random.
`
`49.
`
`The same tenet discussed above for processing steps also applies to
`
`processing modules: When taking a specific processing module out of its intended
`
`sequence and inserting it at another point in the sequence of processing modules,
`
`one must ensure the following: First, the processing modules preceding the
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`specific processing module must provide an initial configuration that is compatible
`
`with the specific processing module. Second, the final configuration resulting from
`
`the specific processing module must be compatible with the subsequent processing
`
`module and beyond.
`
`50. As would be understood by a POSITA, a change in the sequence of
`
`processing modules would not lead to the desired result; if done nonetheless, it will
`
`likely lead to a non-functioning IC device.
`
`51.
`
`For example, trench isolation formation consists of three major
`
`processing steps, namely (i) etching the trench, (ii) refilling the trench with CVD
`
`oxide, and (iii) planarizing the wafer. Without elaborating further, it would be
`
`understood by a person of skill that it would not be possible to change the sequence
`
`of these three processing steps.
`
`52.
`
`Planarizing the wafer involves a process that makes the wafer surface
`
`planar or flat. The planarization can be accomplished by, for example, a technique
`
`called chemical mechanical planarization (CMP). This process uses a chemically
`
`enhanced mechanical polishing procedure to planarize or polish a wafer.
`
`53.
`
`The complexity of integrated circuit fabrication is appreciated by the
`
`technical community and widely supported by the technical literature. Quotes
`
`illustrating the complexity of Si ICs include the following:
`
`The management of a modern IC fab is an enormously complex
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`endeavor [...]
`
`Exhibit 2005, p. 145.
`
`Active and passive devices are formed and interconnected
`
`across the substrate using numerous fabrication steps, materials
`
`and equipment. To achieve precise placement of features which
`
`form an integrated circuit, a carefully carried out sequence of
`
`processing steps (e.g., deposition, etch, lithography, implant
`
`and/or heat cycles) must be followed. Any deviation from the
`pre-set fabrication “recipe” will modify characteristics of the
`resulting product. [....] There may be numerous layout
`
`arrangements used for a specific integrated circuit depending
`
`upon the number of revisions that must be undertaken to
`
`achieve optimal performance, or performance which is more
`
`suitable to a specific application.
`
`Exhibit 2006, 1:19-43.
`
`[...] a wafer fab includes a complex sequence of processing
`
`steps wherein the result of any particular processing step
`
`typically is highly dependent on one or more preceding
`
`processing steps. For example, if there is an error in the overlay
`
`or alignment of etch masks for interconnects in adjacent IC
`
`layers, the resulting inter connects are not in their proper design
`
`location. [...] For example, a misalignment of inter connect etch
`
`masks which is not extensive enough to result in an electrical
`
`short, can still contribute to causing an electrical short if the
`
`process is slightly out of specification [...].
`
`Exhibit 2007, 2:30-36, 40-43.
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`Semiconductor Manufacturing is a planar process and is the
`
`foundation of the information age. The planar silicon transistor
`
`is the very heart and soul of modern electronics. Modern IC
`
`devices have a multitude of transistors, capacitors, and resistors.
`
`The complexity and scale of these devices is mind boggling.
`
`Billions of these devices in the submicron dimensions are
`routinely fabricated in today’s modern IC devices. Fabrication
`of these devices is rather simple in theory -- deposit, pattern,
`
`etch, and repeat. However, the actual fabrication process is
`
`unbelievably detailed at every step.
`
`Exhibit 2008, p. 82.
`
`As increasingly complex ICs utilize an increasing number of
`
`circuit elements, more electrical interconnects between circuit
`
`elements and a greater number of conductor-insulator layers are
`
`required.
`
`Exhibit 2009, 1:59-62.
`
`[...] small transistors also incur increased variance of the
`
`statistical distribution of device performance. Increasing
`
`variability in performance from device to device complicates
`
`the already enormous task of designing circuits and multi-
`
`circuit modules.
`
`Exhibit 2010, p. 1.
`
`54.
`
`I have reviewed Dr. Banerjee’s Declaration to see how he addresses
`
`the issue if it would be possible to fabricate the combinations of elements the he
`
`proposes would be obvious to combine. I have found only four instances where he
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`even arguably addresses the issue.
`
`Ogawa also discusses how to implement this trench
`a.
`isolation with “a series of ordinary steps available in the prior
`art” that “are employed for production of sources and drains 58,
`an inter-layer insulating layer 59 and an upper layer wiring 60
`
`for the ultimate purpose of producing a MOS IC. (Ogawa at
`8:3–7.)
`Exhibit 1004, ¶79.
`
`Moreover, a person of ordinary skill in the art would
`b.
`have understood that replacing Lee’s LOCOS with Noble’s STI
`would have been entirely compatible and had no impact on the
`
`processes used for gate formation, source/drain formation, L-
`
`shaped sidewall formation, silicide formation, or any other
`
`aspect of the claims. LOCOS and STI are both methods for
`
`forming insulating materials in the same locations of the
`
`substrate to perform the same function. They are both
`
`performed near the very beginning in device processing, and
`how the isolation regions are formed would not affect Lee’s
`processes or the resultant device structures. It is therefore my
`
`opinion that the combined teachings of Lee and Noble render
`
`the Challenged Claims obvious.
`
`Exhibit 1004, ¶82.
`
`Moreover, a person of ordinary skill in the art would
`c.
`have understood that replacing Lee’s LOCOS with Ogawa’s
`trench isolation would have been entirely compatible and had
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`no impact on the processes used for gate formation,
`
`source/drain formation, L-shaped sidewall formation, silicide
`
`formation, or any other aspect of the claims. LOCOS and trench
`
`isolation are both methods for forming insulating materials in
`
`the same locations of the substrate to perform the same
`
`function. They are both performed near the very beginning in
`
`device processing, and how the isolation regions are formed
`would not affect Lee’s processes or the resultant device
`structures.
`
`Exhibit 1004, ¶198.
`
`Other references further demonstrate that replacing Lee’s
`d.
`LOCOS with Ogawa’s trench isolation would have constituted
`a simple substitution of one known element for another
`
`according to known methods to achieve predictable results.
`
`Exhibit 1004, ¶201
`
`55.
`
`I find these statements to be entirely superficial and conclusory. They
`
`do not begin to address the numerous considerations and