81
`
`
`
`Patent Owner’s Response, Paper 14, p. 119
`
`
`
`
`
`Patent Owner’s Response, Paper 14, p. 119
`
`
`
`82
`
`IPR2016-01246 Patent Owner’s Preliminary Response, Paper 7, p. 30
`
`
`
`83
`
`Noble/Ogawa
`
`Only the wiring
`
`layer goes across
`
`m m
`
`
`
`Gate electrode and gate
`
`dielectric extend across
`
`Patent Owner’s Response, Paper 14, p. 111
`
`:
`
`: Slalth-
`
`_ Isohuon unusual: - Gaucnduclorlpoly-sllkon)
`
`_ Gatedde - Conductive wlrlnglwd(m¢talsllldde)
`
`
`
`84
`
`
`
`
`Top View
`Bl
`
`84
`
`Inter-
`connect
`
`Gate width
`dir‘é‘étibn
`
`A - -
`
`----- --
`
`- - A
`
`
`
`
`
`
`Gate length
`dire'ction
`
`Silicon substrate
`
`AA cross sectional view
`
`
`
`gate stack
`
`Noble
`
`BB cross sectional View
`
`
`
`
`
`lst
`
`edge
`Si substrate
`
`edge
`
`- Isolation oxide - Gate conductor
`
`
`
`Patent Owner’s Response, Paper 14, p. 54
`
`
`
`85
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 38
`
`
`
`86
`
`Process sequence forming the Noble gate stack and interconnect:
`
`Gate stack deposition I growth:
`
`—Ga~e conductor te-s- ms“
`Gate dielectric (e.g. 5:02)
`
`Silicon substrate
`
`Trench etching:
`
`Silicon substrate
`
`Oxide deposition (trench re-fill):
`
`
`
`Silicon substrate
`
`Planarizatlon (e.g. by CMP}:
`
`Silicon substrate
`
`Noble gate and Interconnection:
`
`Silicon substrate
`
`Higth conductive layer (e.g. metal)
`Gate conductor (e.g. poly-Si)
`Gate dielectric (e.g. 510;)
`
`Patent Owner’s Response, Paper 14, p. 74
`
`
`
`87
`
`Cross section along gate length and width direction:
`
`Gate conductor
`
`Interconnection
`(wiring layer)
`
`
`
`Silicon substrate
`
`Patent Owner’s Response, Paper 14, pp. 58, 76
`
`
`
` 88
`
`88
`
`Cross section along gate length direction:
`
`Gate stack
`
`Interconnection
`
`.4
`
`Silicon substrate
`
`Patent Owner’s Response, Paper 14, p. 75
`
`
`
`
`
`89
`
`Anisotropic etching:
`
`/ Second sidewall
`
`
`
`Silicon substrate
`
`
`
`Sfll
`
`
`
`Patent Owner’s Response, Paper 14, p. 77
`
`
`
`90
`
`Patent Owner’s Response, Paper 14, p. 78
`
`
`
`91
`
`a.
`
`Light eeuree
`
`E Mask
`
`"'_"'
`
`Lene te reduee image
`
`
`
`
`
` Die being expeeed en wafer
`
`Patent Owner’s Sur-Reply, Paper 37, p. 35
`
`
`
`
`
`92
`
`Gate 1
`
`Vin
`
`G
`cgficatreed
`
`Gate 2
`
`\
`
`Supply voltage
`
`p-channel
`
`
`
`
`. V0",
`
`
`Enamel
`
`The transistors
`are in an electrical
`series circuit
`
`Patent Owner’s Sur-Reply, Paper 37, p. 38
`
`
`
`93
`
`Lee
`
`— L
`
`ee
`
`Now that fomtion of e netted daehkonriple by“ t:
`speahuhunduaiMendetyotewhc-tiomot
`the inventive structure together with alternative eut-
`hodiuteete and their advantages will he deseeihed.
`FIGS. 5-1 mutate how the inventive concept my
`mheuifiudtofwmalifitly-dopdwm so
`Refarhgfltutofld.8.niouitwhntetiooflep.
`than «W'hymmwrdem
`mealflitpedhmedtotomwm
`thosZSettdnJheeppwpebteiohtpeeietJlisdetee-
`mu-umamocmosmmou ss
`mammamoswamu
`“mahmdmthumd
`themwewhiehmhetlieldedfl'onthehphu-
`flawlessldtwmhenotduillutmedinFIOJ.
`wmuflahedhymcenl’JLutlnMw
`“mamnduuamurmw
`tic-speciesleII‘hyetNhuuotheenetehethttt-y
`mummflmthehpmmuep.
`Walmaufllwmummh
`manna)
`Aurietyofuhefleehniqeesmyheutilhedtol‘am
`juetioasaudfl.lueeeheuemzl.fltud
`ml’iffomedht-iumponitmfludflof
`
`ea
`
`Exhibit 1002, Lee, 3:49-4:33
`
`
`
`94
`
`Exhibit 1002, Lee, 3:49-4:33 (continued from previous page)
`
`
`
`95
`
`Lowrey
`
`— L
`
`owrey
`
`2
`
`arsenic or phosphorus to create the N-wells. The N-
`well regions are then oxidized using a first oonventiOnal
`LOCOS (LOCal Oxidation of Silicon) step to create a
`silicon oxide layer to prOtect them from an Optional
`boron in lant which ad'usts the concentration of the
`P4?!» Shh i'or iii? 153mm aevrces.' During the
`LOCOS process. the pad oxide serves as a stress relief
`layer. Alternatively. an oxide deposition or oxide
`growth step could replace the first LOCOS step, elimi-
`nating the need for the first pad oxide layer and the first
`nitride layer. A subsequent high-temperature drive step
`is used to achieve the desired N-well junction depth.
`Following removal of the oxide layer. a second layer of
`pad oxide is grown over the entire wafer. A second
`silicon nitride layer is then deposited On top of the pad
`oxide layer.
`
`Exhibit 1017, Lowrey, 2:1-6
`
`
`
`Lowrey
`
`Lowrey
`
`'
`
`8
`22 at the edge of masking layer 21 during the oxide
`growth step.
`nitride layer 13, the wafer is exposed to an Optional
`boron adjustment implant which optimizes the concen-
`s tration of P-type charge 'earriers in the substrate regions
`outside the N-well where N-channel devices will he
`created. Silicon dioxide masking layer 2! protects the
`N-well region from this boron adjustment
`implant.
`Next. the phosphorus atoms implanted in the N-well
`10 regions 15 and the boron atoms outside the N-well from
`the optional adjustment implant are driven into the
`substrate during a high-temperature step.
`
`96
`
`Exhibit 1017, Lowrey, 8:2-12
`
`
`
`97
`
`Lowrey
`
`Lowrey
`
`mini-spacer oxide layer 62 on the edges of the N-chan-
`nel transistor gates 56.
`Referring now to FIG. 7. all circuitry is blanketed
`with a first spacer oxide layer 71 by one of various
`techniques (e.g.. chemical vapor deposition).
`Referring now to FIG. 8, first spacer oxide layer 11
`and mini-spacer oxide layer 62 are etched with a first
`misotopicetchthenopdonanyetchedoneeagainwith
`aftrstisotropicetchtoformafiratsetofsidewallspac-
`er: 8! for N-channel transistor gates 36, N-channel
`interconnectsflandtheportionofpolysilioon layers
`which blankets the P-channel regions. The anisotropic
`etch is used to remove most of the spacer oxide layers.
`but not to the point where the substrate is cleared. The
`task of clearing the substrate is left to the wet etch.
`which can be made far more selective to silicon dioxide
`than to the substrate. thus minimizing silicon crystal
`damage on the substrate surface. A high-dosage arsenic
`or phosphorus implant then creates self-aligned heavily
`doped n-type source/drain regions 82 for N-channel
`devices. The high-dosage implant is self-aligned to the
`edges of the N-channel transistor gates 56.
`
`Exhibit 1017, Lowrey, 9:6-12
`
`
`
`_-
`
`Ogawa
`
`98
`
`Ogawa
`
`30
`
`duce a semiconductor device having a high quality.
`Theseoond embodiment. whlchisanextensionofthe
`previous embodiment, is s method for production of a
`semioonductordevioeinsccordsnccwiththefirstem-
`bodiment. wherein the polycrystalline silicon (Si) layer.
`whichfimcfiomwnhsorhthermdsusimisftmher”
`employed for production of electrodes for gates and/or
`some of the metal wiring. This simplifies the production
`steps thereof. This embodiment will he described. refer-
`ring to FIGS. 5(a), 5(b) and 5(c).
`
`Exhibit 1010, Ogawa, 7:31-39
`
`
`
`—-
`
`Noble
`
`99
`
`Noble
`
`single masking step defines the edge between the trench and
`gate stack and provides perfect alignment therebetween.
`Thus. the gate is bounded by a raised trench on two opposite
`sides. However, since the gate dielectric and gate conductor
`wcrcformedasblankct layers beforethetrench wasetehed,
`there is no corner sharpening. no gate dielectric thinning.
`and no gate wrap around
`
`Exhibit 1015, Noble, 4:22-26
`
`
`
`100
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 59:9-16
`
`
`
`101
`
`I31. Lee’s “L-shaped” spacers (Exhibit 1002, 3:8-21) are formed by
`
`etching away layers 119 and 121 shown in Fig. 13. Layers 115, 117 and 118 are
`
`“typically formed during initial steps of semiconductor fabrication.” Exhibit [002,
`
`6:53-56. The purpose of the “L—shaped” spacers is to allow for the specific method
`
`used by Lee to dope the source/drain regions.
`
`Exhibit 2012, Schubert Declaration, ¶131
`
`
`
`102
`
`Exhibit 2012, Schubert Declaration, ¶131 (continued from previous slide)
`
`
`
`103
`
`Exhibit 2012, Schubert Declaration, ¶131 (continued from previous slide)
`
`
`
`104
`
`[52. Different
`
`from Lee, Noble uses
`
`a diffusion process
`
`to for
`
`ultrashallow SID junctions after the spacers are formed.
`
`In this regard, Noble states:
`
`Then, afier
`
`spacers 152 are formed (FIG.
`
`12),
`
`intrinsic
`
`polysilicon (or intrinsic amorphous silicon)
`
`is deposited or
`
`selective silicon is growth for raised source/drain 154 as shown
`
`in FIG. 13. Dopant for the raised source/drain is implanted at
`
`low energy so as to avoid damage to the single crystal silicon
`
`below. Then the dopant is diffused from the polysilicon to form
`
`[source/drain] ultrashallow junctions 156 without damage.
`
`Exhibit
`
`lOlS, 6:l7-24 (emphasis added). Based on these differences, a POSITA
`Exhibit 2012, Schubert Declaration, ¶152
`
`implementing Noble’s transistor would not be motivated to implement the spacers
`
`
`
`105
`
`158. This configuration is achieved because Noble begins the fabrication
`
`process by firs_t
`
`laying down layers 14 and 116 and then boring (or etching)
`
`through these layers to form a trench that is then filled with oxide material. The
`
`opening formed through layers 14 and 116 is bordered by these two layers.
`
`Exhibit 2012, Schubert Declaration, ¶158
`
`
`
`106
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 84:14-18
`
`
`
`107
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 84:19-85:18
`
`
`
`108
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 85:19-86:2
`
`
`
`109
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 86:3-13
`
`
`
`110
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 87:14-88:3
`
`
`
`111
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 88:4-15
`
`
`
`112
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 89:2-13
`
`
`
`113
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 89:14-90:8
`
`
`
`114
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 124:12-125:7
`
`
`
`115
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 125:8-20
`
`
`
`116
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 126:11-17
`
`
`
`117
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 126:18-127:5
`
`
`
`118
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 128:2-15
`
`
`
`119
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 128:16-22
`
`
`
`120
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 129:1-7
`
`
`
`121
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 129:8-17
`
`
`
`122
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 131:14-19
`
`
`
`123
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 132:12-133:2
`
`
`
`124
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 133:2-15
`
`
`
`125
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 133:16-134:3
`
`
`
`126
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 136:1-11
`
`
`
`127
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 148:20-149:8
`
`
`
`128
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 200:21-201:5
`
`
`
`129
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 201:6-19
`
`
`
`130
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 201:20-202:9
`
`
`
`131
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 202:15-21
`
`
`
`132
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 203:14-204:3
`
`
`
`133
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 204:4-11
`
`
`
`134
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 204:12-19
`
`
`
`135
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 207:12-208:15
`
`
`
`136
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 208:16-209:7
`
`
`
`137
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 209:8-20
`
`
`
`138
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 209:21-210:10
`
`
`
`139
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 212:14-213:6
`
`
`
`140
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 272:11-21
`
`
`
`141
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 227:2-7
`
`
`
`142
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 275:6-17
`
`
`
`143
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 275:18-276:3
`
`
`
`144
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 276:4-12
`
`
`
`145
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 276:17-277:2
`
`
`
`146
`
`Exhibit 2078, Deposition Transcript of Dr. Banerjee, 277:17-278:4
`
`
`
`147
`
`147
`
`Unlike lnnogenetics, TSMC devotes dozens of pages to explaining
`
`—aper 2 ammo-01247), at 2|, 62. TSMC also explained why
`
`a POSITA would have made those modifications (i.e., to facilitate scaling of the
`
`Lee and Lowrey devices), and why a POSITA would have reasonably expected to
`
`succeed. Paper 2, at 5-7, 2l-30, 70-76; Paper 2 ([PR20l6-Ol247), at 5-7, 2l-30,
`
`62-68; EX1004, 1182, 198; EX1024, 1193, I73.
`
`Petitioner’s Reply, Paper 21, pp. 27-28
`
`
`
`
`
`and sources and drains (58) (M, 8:3-7. Fig. 5(c)). (Ex. 1004. 180.) Ogawa’s
`
`Figure 5(c). a representative illustration, appears below with color and mutations.
`
`148
`
`Fig.5lc}
`
`
`
`sz—w one. (90,)
`51—min)
`53-!!!” [an
`MM [50,)
`mung-8n-WWI-duel fit-W
`ss—mtor-umm but Winn“
`
`B.
`
`The Lee-Noble combination renders claims 1-3. 5—1, 9-12, and
`14—18 obvious
`
`Lee teaches every limitation of the challenged claims except trench isolation.
`
`A POSITA would have understood that Noble’s $11 was a known substitute for
`
`Lee’s LOCOS isolation. (Ex. I004,182;sec also Ex. 1009, l:3l—2:24; Ex. IN I,
`
`4:8—16; Ex. lOl2, 3:3—10; Ex. 1013, 5:56—67; Ex. l0l4. 22:49—52; Ex. 10l5, Title,
`
`1:7—10, 2:53—57. 4:14—23. Figs. 12. 13.) The combined teachings discussed in this
`
`section refer to the teachings ofLee. with its LOCOS isolation replaced by Noble's
`
`STl.
`
`IPR2016-01246 Petition, Paper 2, p. 21
`
`
`
`149
`
`C.
`
`The Lee-Ogm combination renders clai 1—3, 5—7, 9—D, and
`14—"! obvious
`
`As demonstrated above in Section V.B.. Lee teaches every limitation of the
`
`challenged claims except trench isolation. A POSITA would have understood that
`
`Ogarm's trench isolation was a known substitute for Lee’s LOCOS isolation. (Ex.
`
`I004. 1198:5139 also Ex. [009, |:3I—2:24; Ex. 10! l. 4:846; Ex. I0|2, 3:3—l0; Ex.
`
`IOI3, 5:56—67; Ex. l0l4, 22:49—52: Ex. I015. Title. |:7—|0. 2:53—57, 4:I4—23.
`
`Figs. I2, [3.) The combined teachings discussed in this section refer to the
`
`teachings of Lee, with its LOCOS isolation replaced by Ogawa‘s trench isolation.
`
`l.
`
`A POSITA would have combined the teachings of Lee and
`Ogamr
`
`The same reasons that would have compelled a POSITA to replace Lee‘s
`
`LOCOS with Noble’s 811 also would have compelled a POSlTA to replace Lee's
`
`LOCOS with Ogawa's trench isolation.
`
`1004, 1199; see also §§ILB, V.A.3,
`
`V.B. I .)
`
`a.
`
`Admitted prior art teaches replacing LOCOS with
`known trench Isolation
`
`The ’I'I4 patent shows trench isolation. including trench isolation with a top
`
`surface higher than the surface of the semiconductor substrate, as prior art. (See
`
`supra §V.B. I .a.)
`
`IPR2016-01246 Petition, Paper 2, p. 70
`
`
`
`150
`
`Unlike Innogenetics, TSMC devotes dozens of pages to explaining
`
`_ P
`
`aper 2, at 2|,70;— TSMC also explained why
`
`a POSITA would have made those modifications (i.e., to facilitate scaling of the
`
`Lee and Lowrey devices), and why a POSITA would have reasonably expected to
`
`succeed. Paper 2, at 5-7, 2 [-30, 70-76; Paper 2 (lPR2016-01247), at 5-7, 21-30,
`
`62-68; EXl004,1]82, I98; EX1024, 1193. I73.
`
`Petitioner’s Reply, Paper 21, pp. 27-28
`
`
`
`
`
`151
`
`Fig.5(cl
`
`
`
`u—w one. 560,)
`n—mm
`WW
`“mm
`mm—mmum am
`Wm“
`
`B.
`
`The blurry-Noble combination renders claims 1. 4, 5, 8-l2, l4,
`and I6 obvious
`
`Lawn-y teaches every limitation of the challenged claims except trench
`
`isolation. A POSITA would have understood that Noble‘s trench isolation was a
`
`known substitute for Lawrey's LOCOS isolation. (Ex. 1004, 180; see also Ex.
`
`1009. l:3 l—2:24; Ex. 101 l. 4:8—16;Ex. 1012. 3:340; Ex. l0l3, 5:56—67; Ex.
`
`10”, 22:49—52; Ex. IOIS, Title. I:7—I0, 2:53-57, 4: l4—23, Figs. 12, I3.) The
`
`combined teachings discussed in this section refer to the teachings of Lawrey. with
`
`its LOCOS isolation replaced by Noble's STI.
`
`I.
`
`A POSITA would have found it obvious and even desirable
`
`to have combined the teachings of Low and Noble
`
`Many reasons would have compelled a POSITA to replace Lowrey’s
`
`IPR2016-01247 Petition, Paper 2, p. 21
`
`LOCOS with Noble‘s STI. (a. 1004, 1180—94.) LOCOS was cheaper and
`
`simpler at the time of Lowrey (February 1990). and the bird’s beak was not a major
`
`
`
`152
`
`
`
`
`
`
`
`
`
`
`
`to
`
`It
`
`
`5) -."‘.'"\:17’: "'
`
`
`
`FIG.
`
`l5lgl't~-C4.'n'n:erltnItemRegion
`
`A POSITA would have understood that the LomyNoble combination
`
`teaches “the source/drain regions include low-concentration source/drain regions
`
`and high-concentration sourceidrain region. and the first silicide layers are formed
`
`on the high-concentration soureeldrain regions." (Ex. I004. 11157—62; see also
`
`supra §V.B. I.)
`
`C.
`
`The Lowrey-Ogaw combination reders claims 1, 4, 5. 8-12, 14,
`and 16 obvious
`
`As explained in Section VB, 1.0qu teaches every limitation of the
`
`challenged claims except trench isolation. A POSITA would have understood that
`
`Ogawa’s uench isolation was a known substitute for Lowrey‘s LOCOS isolation..
`
`(Ex. "104.1163: see also Ex. "X19, 1:31-2:24; Ex. lOI 1,4:8-16; Ex. I012. 3:3—
`
`l0; Ex. l013, 5:56—67; Ex. |0|4, 22:49—52; Ex. l0l5, Title. l:7—l0, 2:53—57,
`
`4: l4—23, Figs. l2. 13.) The combined teachings discussed in this section refer to
`
`IPR2016-01247 Petition, Paper 2, p. 62
`
`the teachings of Lowrey, with its LOCOS isolation replaced by Ogawa‘s trench
`
`isolation.
`
`
`
`153
`
`33
`
`7
`
`IIIIIIIIIIIIIII u
`:lllflllflllliillll
`IIIIIIIIIIIIIII .-
`
`
`
`
`uuuuuuuuuuuuuuuuuu..
`
`
`
`exmn (Lo my), FIG
`
`I M .I
`
`In 1
`
`
`
`1 1'1 .
`
`://;
`
`
`
`
`' /
`
`d
`
`
`
`
`Trench
`
`Etch & Ch
`
`an t
`el—S op Implant
`
`R ist Re ova
`es
`In
`
`I 8; Trench Filling
`
`
`
`
`
`Petitioner’s Reply, Paper 21, pp. 21-22
`
`
`
`154
`
`107. At this point of Lowrey’s illustrated embodiment, the isolation regions
`
`start to form. The first step is to prepare a channel stop region 41 after removing
`
`the exposed portions of the second nitride layer 32. (Lowrey at 8:2l—30, FIG. 4.)
`
`That is followed by forming the LOCOS isolation. (Lowrey at 8:31—35, FIG. 5.)
`
`To integrate STI, a person of ordinary skill in the art would have immediately
`
`recognized STI formation can be done here in the alternative.
`
`I note, for example,
`
`that in FIG. 3 of Lowrey a pad oxide and nitride layer are already present. The
`
`well-known STI processes I described in Section VILA begin the same way. For
`
`example, Noble’s FIG. 9 and Ogawa’s Fig. 4(c) are formed the same way, although
`Exhibit 1057, Declaration of Dr. Banerjee, ¶107
`
`
`
`155
`
`they use a polysilicon polish/etch stop layer instead of a nitride polish/etch stop
`
`layer. As I explained in Section VILA, both polysilicon and silicon nitride were
`
`well-known options available to a person of ordinary skill in the art, and either
`
`could be used (as could any number of other materials). In other words, a person
`
`of ordinary skill in the art would have immediater recognized that FIG. 3 of
`
`Lowrey is suitable for a trench etch. A person of ordinary skill in the art would
`
`have also recognized that the channel stop implant should be performed after the
`
`trench is defined.ll This modification to the Lowrey process is illustrated below.
`
`
`
`” [ do not agree with Dr. Schubert that non-uniformity at the bottom of the trench
`
`would enhance leakage currents. Lowrey itself discloses a non-planar LOCOS
`
`Exhibit 1057, Declaration of Dr. Banerjee, ¶107
`
`isolation with non-unifonnity at the bottom of the isolation region. Using STI with
`
`
`
`156
`
`384. Layer 62 is made of “oxide” (e.g. thermal oxidation) and layer 71 is
`
`also made of “oxide” (e.g. chemical vapor deposition), where “oxide” refers to
`
`silicon dioxide or 8102. That is, both layers, 62 and 71, are made of the same
`
`material, “oxide”. Subsequently, the two layers are subjected to an anisotropic etch
`
`to form a single sidewall spacer 81:
`
`Referring now to FIG. 8, first spacer oxide layer 71 and
`
`mini-spacer oxide layer 62 are etched with a first anisotropic
`
`etch, then optionally etched once again with a first isotropic
`
`etch to form a first set of sidewall spacers 81 for N-channel
`
`transistor gates 56, N-channel interconnects 57 and the portion
`
`of polysilicon layer 53 which blankets the P-channel regions.”
`Exhibit 2012, Declaration of Dr. Schubert, ¶384
`
`Exhibit 1017, 926-12.
`
`
`
`157
`
`Petitioner’s Motion to Exclude Evidence, Paper 29, p. 11
`
`
`
`158
`
`Petitioner’s Objections to Evidence, Paper 13, p. 7
`
`
`
`159
`
`Petitioner’s Objections to Evidence, Paper 16, p. 6
`
`
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