1
`
`PATENT OWNER’S
`DEMONSTRATIVE EXHIBIT
`
`Case IPR2016-01246
`
`August 7, 2017
`
`IP Bridge Exhibit 2079
`TSMC v. IP Bridge
`IPR2016-01246
`
`
`
`PATENT OWNER’S
`DEMONSTRATIVE EXHIBIT
`
`Case IPR2016-01246
`
`August 7, 2017
`
`IP Bridge Exhibit 2079
`TSMC v. IP Bridge
`IPR2016-01246
`
`
`
`2
`
`Institution Decision, Paper 8, p. 17-18
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`3
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`Institution Decision, Paper 8, pp. 25-26
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`4
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`Institution Decision, Paper 8, p. 26
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`
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`5
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`FIG. 15'
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`
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`Substrate (Si)
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`Trench Isolation (Siozl
`
`Spacer (Si02)
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`Spacer (5i3N4 or SiON)
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`Conductor (poly-SI, AI, Au, W, siliclde, etc.)
`
`Gate Oxide (5:0,:
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`Gate Electrode/Interconnection (poly-Si)
`
`Optional Silicide
`
`Petitioner’s Reply, Paper 21, p. 20
`
`Protective Nltrlde (Sl3N‘ or SION)
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`Optional LDD Source/Drain
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`
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`6
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`Petitioner’s Reply, Paper 21, p. 19
`
`IPR20l6-01246, IPR20I6-01247
`Patent 7,l26,l74 BZ
`
`6:46-61, FIG. I]. To substitute Noble’s and Ogawa’s S'I'l structures for Lee‘s
`
`LOCOS isolation, a POSITA would have first made raised $11, removing the
`
`polish/etch-stop and pad oxide, and formed the gate stack. EX I 057, 1179-83. IPB
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`provides no basis for asserting a POSITA would have retained the polish/etch-stop
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`and pad oxide as the gate stack. That assertion makes no sense because. as the
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`following figures illustrate, removing those features makes trivial the substitution,
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`TSMC described in its Petitions. EXI057, 1180-83; Paper 2, at 21. 70.
`
`FIE.
`
`1'.
`
`FIG.
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`11'
`
`
`
` Modified Lee FIG. 11
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`— Then, as in Lee, gate oxide I I5, polysilicon I I7,
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`and silicon nitridelsilicon oxynitride layer I [8 are successively deposited.
`
`EX 1 057, 183.
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`
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`
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`7
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`
` ”(SM19 \‘W?’(W
`>\II
`
`
`Exhibit 1002, Lee, Fig. 4
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`
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`8
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`
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`Insufficient diffusion
`
`lnadequately controlled diffusion
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`Excessive diffusion
`
`
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`[— Inversion channel will not form
`in regions Indicated above.
`Device will be non-functional.
`
`Given that there are millions of transistors
`on a Si lC device, individual transistors
`may work, but not the Si IC In its entiretv.
`Device will be non-functional.
`
`Channel length will be
`too short (punch-through effect).
`Device will be non-functional.
`
`[1] Double arrows represent variation in diffusion, Atomsion; this quantity is inherently long because {Diffusion is long.
`Patent Owner’s Sur-Reply, Paper 37, p. 15
`
`
`
`9
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`(a) Lee doping sequence:
`First deep. then a 21 1:: n- implant.
`
`(b) '174 doping sequence:
`First 5 1.1} r. n. then deep Implant.
`
`Gate stack depostton and formation of 3 SW5:
`
`Gate stack deposltion:
`
`5'aiicn1mp‘am:
`[‘i'i
`j
`lllv‘rrrrrrrrr
`
`T
`
`1
`
`5w formation follawed by deep implant:
`HHHHHIH
`
`
`
`on-"nu-“u"-n-n-n-n-n-n-“Cn-
`
`{Advent-3e: [1)Mimmaldifl‘usion required. (21 I
`i Minimal variations. (3] Shallow junctions. -)
`!
`~..........................................’
`1 Suitable for 250-350 nm nodes used win 511.
`1
`
`Patent Owner’s Sur-Reply, Paper 37, p. 18
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`
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`Deep Implant:
`HHHHHHI
`
`
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`3rd SW removal followed Inn-.1 'ILiw i’n',» .m:
`llllllillllll
`
`
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`{1] Undoped region below SW Is problematic
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`Post-Implantation annealing:
`
` —d...
`
`r‘mmm-"mmmmm-“mm
`
`‘i
`
`1I
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`[1] Encesswe diffusion required. {I}
`E Problem:
`I Inherent process variations. [3) Deeper junctions.
`
`
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`10
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`Segawa/’174 Patent
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`Patent Owner’s Response, Paper 14, p. 18
`Exhibit 1001, ‘174 Patent, Fig. 15(d)
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`
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`11
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`Segawa (‘174 Patent)
`
`IPR2016-01246 Patent Owner’s Preliminary Response, Paper 7, p. 17;
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 19
`Patent Owner’s Response, Paper 14, p. 15
`Exhibit 1001, ‘174 Patent, Fig. 15(f)
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`
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`Segawa/‘174 Patent
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`12
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`Patent Owner’s Response, Paper 14, p. 49
`Exhibit 1001, ‘174 Patent, Fig. 17
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`
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`13
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`Patent Owner’s Sur-Reply, Paper 37, p. 21
`Exhibit 1002, Lee, Fig. 6 (Modified)
`
`
`
`14
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`Lee
`
`IPR2016-01246 Patent Owner’s Preliminary Response, Paper 7, p. 21;
`Patent Owner’s Response, Paper 14, p. 21
`Exhibit 1002, Lee, Fig. 1
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`
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`15
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`Lee
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`Patent Owner’s Sur-Reply, Paper 37, p. 12
`Exhibit 1002, Lee, Fig. 5
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`
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`16
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`Lee
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`Patent Owner’s Sur-Reply, Paper 37, p. 13
`Exhibit 1002, Lee, Fig. 6
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`
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`17
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`Lee
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`Patent Owner’s Response, Paper 14, pp. 25, 45, 51
`Exhibit 1002, Lee, Fig. 11
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`
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`18
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`Lee
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`Patent Owner’s Response, Paper 14, p. 67
`Exhibit 1002, Lee, Fig. 12
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`19
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`Lee
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`Patent Owner’s Response, Paper 14, p. 46
`Exhibit 1002, Lee, Fig. 12
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`
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`20
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`Lee
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`Patent Owner’s Response, Paper 14, p. 53
`Exhibit 1002, Lee, Fig. 12
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`
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`21
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`Lee
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`Patent Owner’s Response, Paper 14, p. 26
`Exhibit 1002, Lee, Fig. 13
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`
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`22
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`Lee
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`Patent Owner’s Response, Paper 14, p. 80
`Exhibit 1002, Lee, Fig. 14
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`
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`23
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`Lee
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`Patent Owner’s Response, Paper 14, p. 82
`Exhibit 1002, Lee, Fig. 15
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`
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`24
`
`Lee
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`Patent Owner’s Response, Paper 14, p. 26
`Exhibit 1002, Lee, Fig. 15
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`
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`25
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`Lee
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`Patent Owner’s Response, Paper 14, p. 52
`Exhibit 1002, Lee, Fig. 15
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`
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`26
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`Lee
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`Patent Owner’s Response, Paper 14, p. 71
`Exhibit 1002, Lee, Fig. 15
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`
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`27
`
`Lee
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`Patent Owner’s Response, Paper 14, p. 79
`Exhibit 1002, Lee, Fig. 15
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`
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`28
`
`Noble
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`IPR2016-01246 Patent Owner’s Preliminary Response, Paper 7, p. 28
`Patent Owner’s Response, Paper 14, pp. 45, 55, 105
`Exhibit 1015, Noble, Fig. 9
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`
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`29
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`Noble
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`Patent Owner’s Response, Paper 14, p. 55
`Exhibit 1015, Noble, Fig. 10
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`
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`30
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`Noble
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`Patent Owner’s Response, Paper 14, p. 56
`Exhibit 1015, Noble, Fig. 11
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`
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`31
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`Noble
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`Patent Owner’s Response, Paper 14, p. 47
`Exhibit 1015, Noble, Fig. 11
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`
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`32
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`Noble
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`Patent Owner’s Response, Paper 14, pp. 37, 65
`Exhibit 1015, Noble, Fig. 11
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`
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`33
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`Patent Owner’s Response, Paper 14, p. 114
`Exhibit 1015, Noble, Fig. 11
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`
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`34
`
`Ogawa
`
`IPR2016-01246 Patent Owner’s Preliminary Response, Paper 7, p. 43
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 44
`Exhibit 1010, Ogawa, Figs. 4(a) and 4(b)
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`
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`35
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`Ogawa
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`IPR2016-01246 Patent Owner’s Preliminary Response, Paper 7, p. 44
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 45
`Exhibit 1010, Ogawa, Fig. 4(c)
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`
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`Ogawa
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`36
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`Patent Owner’s Response, Paper 14, p. 62
`Exhibit 1010, Ogawa, Figs. 5(a)-(c)
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`
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`Ogawa
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`37
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`Patent Owner’s Response, Paper 14, p. 109
`Exhibit 1010, Ogawa, Figs. 5(a)-(c)
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`
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`38
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`Ogawa
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`IPR2016-01246 Patent Owner’s Preliminary Response, Paper 7, p. 49
`Exhibit 1010, Ogawa, Fig. 5(b)
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`
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`39
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`Ogawa
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`Patent Owner’s Response, Paper 14, p. 66
`Exhibit 1010, Ogawa, Fig. 5(b)
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`
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`40
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`Ogawa
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`Patent Owner’s Response, Paper 14, p. 76
`Exhibit 1010, Ogawa, Fig. 5(b)
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`
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`41
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`Patent Owner’s Response, Paper 14, p. 113
`Exhibit 1010, Ogawa, Fig. 5(b)
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`
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`42
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`Ogawa
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`Patent Owner’s Response, Paper 14, pp. 60, 107
`Exhibit 1010, Ogawa, Fig. 5(c)
`
`
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`43
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`Ogawa
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`Patent Owner’s Response, Paper 14, p. 117
`Exhibit 1010, Ogawa, Fig. 5(c)
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`
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`44
`
`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 29
`Patent Owner’s Sur-Reply, Paper 37, pp. 25, 37
`Exhibit 1017, Lowrey, Fig. 1
`
`
`
`45
`
`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 30
`Patent Owner’s Sur-Reply, Paper 37, p. 25
`Exhibit 1017, Lowrey, Fig. 2
`
`
`
`46
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`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 31
`Patent Owner’s Sur-Reply, Paper 37, p. 25
`Exhibit 1017, Lowrey, Fig. 3
`
`
`
`47
`
`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, pp. 32, 35
`Patent Owner’s Sur-Reply, Paper 37, p. 25
`Exhibit 1017, Lowrey, Fig. 4
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`
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`48
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`Lowrey
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`Patent Owner’s Response, Paper 14, p. 96
`Exhibit 1017, Lowrey, Fig. 4
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`
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`49
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`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 39
`Patent Owner’s Response, Paper 14, p. 101
`Exhibit 1017, Lowrey, Fig. 4
`
`
`
`50
`
`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 39
`Patent Owner’s Response, Paper 14, p. 101
`Exhibit 1017, Lowrey, Fig. 4
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`
`
`51
`
`Lowrey
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`Patent Owner’s Sur-Reply, Paper 37, p. 27
`Exhibit 1017, Lowrey, Fig. 4
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`
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`52
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`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, pp. 33, 36
`Patent Owner’s Response, Paper 14, pp. 28, 31
`Exhibit 1017, Lowrey, Fig. 5
`
`
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`53
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`Lowrey
`
`IPR2016-01247 Patent Owner’s Preliminary Response, Paper 7, p. 40
`Exhibit 1017, Lowrey, Fig. 5
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`
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`54
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`Lowrey
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`Patent Owner’s Response, Paper 14, p. 97
`Exhibit 1017, Lowrey, Fig. 5
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`
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`55
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`Lowrey
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`Patent Owner’s Response, Paper 14, p. 98
`Exhibit 1017, Lowrey, Fig. 7
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`
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`56
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`Lowrey
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`Patent Owner’s Response, Paper 14, p. 29
`Exhibit 1017, Lowrey, Fig. 7
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`
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`57
`
`Lowrey
`
`Patent Owner’s Response, Paper 14, p. 30
`Exhibit 1017, Lowrey, Fig. 8
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`
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`58
`
`Patent Owner’s Response, Paper 14, p. 113
`Exhibit 1017, Lowrey, Fig. 8
`
`
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`59
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`Lowrey
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`Patent Owner’s Response, Paper 14, p. 99
`Exhibit 1017, Lowrey, Fig. 8
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`
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`60
`
`Petitioner’s Reply, Paper 21, p. 21, 23
`Patent Owner’s Sur-Reply, Paper 37, p. 25
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`
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`61
`
`Petitioner’s Reply, Paper 21, p. 21
`Patent Owner’s Sur-Reply, Paper 37, p. 25, 26
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`
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`62
`
`Petitioner’s Reply, Paper 21, p. 21, 23
`Patent Owner’s Sur-Reply, Paper 37, p. 25
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`
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`63
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`
`
`
`
`
`
`
` \\ \‘WA
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`
`
`
`
`
`Patent Owner’s Sur-Reply, Paper 37, p. 26
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`
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`64
`
`Petitioner’s Reply, Paper 21, p. 24
`Patent Owner’s Sur-Reply, Paper 37, p. 26
`
`
`
`65
`
`
`
`Lowrey with Noble/Ogawa:
`
`
`Lea kage‘current
`
`\path
`x>
`\.
`
`Channel {stopger
`(ID-type Si)
`
`
`
`/"
`
`
`/
`
`Patent Owner’s Sur-Reply, Paper 37, p. 29
`Corner/step -) Non-uniformity -> Higher electric fields
`
`-) Greater leakage current
`
`A
`
`
`
`66
`
`Patent Owner’s Sur-Reply, Paper 37, p. 31 (modified)
`
`
`
` 67
`
`67
`
`Photo-resist
`
`Pad oxide (SiOz)
`
`Nitride (Si3N4)
`
`Patent Owner’s Sur-Reply, Paper 37, p. 31
`
`
`
`68
`
`Patent Owner’s Sur-Reply, Paper 37, p. 31 (modified)
`
`
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`69
`
`Patent Owner’s Sur-Reply, Paper 37, p. 31 (modified)
`
`
`
`70
`
`l'
`
`I
`
`
`
`7heatdifferent levels
`
`
`(.2)//////
`.
`.3
`x" /
`4' Thereshouldbeastep
`x
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`yr'f/Iy////,,//
`'l
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`
`Patent Owner’s Sur-Reply, Paper 37, p. 33
`
`
`
` 71
`
`71
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`¢Difference in height/level
`
`
`
`Nitride Removal
`
`Patent Owner’s Sur-Reply, Paper 37, p. 34
`
`
`
`72
`
`for microelectronic circuits. pri-
`Silicon is the dominant material
`marily because of the ease with which it oxidizes to form insulating barriers
`for the subsequent
`implanting of tiny amounts of dopants into selected
`regions to achieve the requisite electrical properties. The silicon dioxide
`insulator and other dielectric films that are commonly encountered such as
`silicon nitride films are patterned by a process known as photolithography.
`Photolithography is probably the key process in microelectronic fabrication
`technology. because it is repeated 5 - 12 times before the three-dimensional
`circuit geometries necessary for a completed metal oxide semiconductor
`(MOS) or bipolar device are achieved. Figure 4 is an outline of the
`manufacturing sequence of a large-scale integrated circuit and illustrates the
`importance of understanding the lithographic technology used to delineate
`the patterns of thin-film dielectrics and conductors. The structure of an
`intenstedcircuitiseomplexbothinthetopognphyofitssurfaceud inits
`internalcompoeition. Bachelementol‘suchadaieehasanintricstethree-
`dimenionalarchitecturethatmmbereprodncedmctlyineverycircuib
`Thestructureismadeupofmanylaymeachol‘whiehisadetaildpat-
`tern. Someofthelayerslieudthinthesilieonwafersndothersaresuched
`Patent Owner’s Response, Paper 14, p. 13
`onthetop. nemulacturingproeeucouiminformingthiseequenceof
`Exhibit 2013, p. 5
`layerspreeiselyinaceordancewiththeplanofthecircuitdesigner.
`
`
`
`73
`
`This photolithography process is repeated (to more than 10 times) before
`
`the thnxrdimensional circuit geometries necessary for a completed metal oxide
`
`semiconductor (M05) or bipolar device are achieved. The structure of an
`
`integrated circuit is complex, bath in the rcpography of its surface and in
`
`its internal composition. Each element of this device has an intricate three-
`
`dimensional structure that must be reproduced exactly in every circuit. The
`
`structure is made up of many layers, each of which is a detailed pattern. Some
`
`of the layers lie within the silicon wafer and others are stacked on the tOp.
`
`The process is described in detail in the book of L.F. THOMPSON, c.G.WELLSON
`
`and M.J. BONDEH “Introduction to Microlithography", American Chemical Society
`
`Symposium Series 219. Amer.Chem.Soc.. Washington D.C., 1983.
`
`Patent Owner’s Response, Paper 14, p. 13
`Exhibit 2014, p. 4
`
`
`
`74
`
`Since semiconductor devices are becoming more
`complex in structure and materials. and since the CMP
`planarization process is dependent on structure and
`materials. apparatus and techniques that permit
`the
`$0 fabrication engineer to control and design the CMP
`process would be highly desirable.
`Generally, a change in one phase of the integrated
`fabrication process usually impacts other phases. Since
`integrated circuit fabrication processes are highly com-
`55 plex and require sephisticated equipment. developments
`of entirely new processes and materials can be quite
`costly. Thus new apparatus and methods for control of
`the CM? process that can be incorporated into current
`fabrication technology would be highly,I desirable be-
`60 cause expensive modification of equipment and pro-
`Patent Owner’s Response, Paper 14, p. 13
`Exhibit 2015, 2:52-61
`cesses can be avoided.
`
`
`
`75
`
`Patent Owner’s Response, Paper 14, p. 13
`Exhibit 2016, 2:19-24
`
`5
`
`2
`aspect ratios: that is. they become deeper and narrower.
`Conventional deposition techniques. eg. sputtering.
`have difficulty coating such deep. narrow recesses.
`because the atoms tend to contact one of the walls be-
`fore reaching the bottom of the recess. Thus. with re-
`spect to diffusion barriers, the use of conventional pro-
`duction techniques. such as sputtering. leads to a de-
`crease in the thickness of the diffusion barrier at the base
`of a contact as the aspect ratio increases. As the thick-
`‘0 ness of the diffusion bam'er decreases. the ability of the
`diffusion barrier to withstand thermal energy intro-
`duced in subsequent processing decreases. and the reli-
`ability of the device degrades. Thus there has been an
`impetus in the industry toward new barrier technology
`15 that will deposit an adequate barrier in high aspect ratio
`contacts. which impetus has tended toward the devel-
`opment of equipment and materials net presently used
`in semiconductor device fabrication. Generally. a
`20 change in one phase of the fabrication prunes usually
`impacts other pluses. Sincesetniconducsordevice fabri-
`cation processes are highly oomph and require sophiv
`tlcated equipment. developments or entirely new 0
`processes and materials can be spite costly. Thus a
`diffusion barrier that is more effective and yet can be
`incorporated into current fabrication technology would
`be highly desirable because expensive modification of
`equipment and processes can be avoided.
`
`25
`
`
`
`76
`
`5
`
`6
`above) using diffusion or ion implantation techniques in
`order to generate p-n junctions which form active semi-
`conductor devices such as diodes or transistors.
`Finally. various types of proceases (called “metalliza-
`tion“) can be used to produce the interconnecting wir-
`ing pattern between the various circuit elements which
`form the integrated circuit. Wiring patterns can be
`formed on the wafer using flash evaporation. filament
`evaporation, electron-beam evaporation. planar and
`to cylindrical sputtering. or induction evaporation meth-
`ods.
`
`3. EtchingoMasking Processes
`in selective
`The etching-masking processes result
`removal or addition of the deposited or grown layers of
`15 semiconductive or passivation materials in accordance
`with the patterned geometry which defines the inte-
`grated circuit elements. The etching-masking steps can
`be accomplished in a variety of ways. depending upon
`the particular type of material that is to be masked or
`20 etched. Materials commonly used in the etching-mask-
`ing steps are silicon dioxide. doped silicon dioxide.
`poly-silicon. silicon nitride, metals and polyimide.
`“Tam «:12; highly couples imaging. has:
`m mmM IS
`25 mamhnmhmamenumbaof
`integratedcirmmtichmaycnntain Iitenllytenaor
`'Ammag‘W“W' W‘mt.
`processes are completed. each wafer
`scribed and diced an as
`separate it into individual
`
`Patent Owner’s Response, Paper 14, p. 13
`Exhibit 2017, 6:23-31
`
`
`
`77
`
`l
`
`INTEGRATED CIRCUIT MICRO-FABRICATION
`
`USING DRY LITHOGRAPHIC PROCESSES
`
`The United States Government has rights in this 5
`invention pursuant to the Department of Air Force
`Contract No. Fl9628-85-C-0002.
`This application is a continuation of application Ser.
`No. 07/514,394, filed Apr. 27. 1990. now abandoned
`which is a continuation of application Ser. No. 10
`01/149,426, filed Jan. 29. 1988. now abandoned.
`
`BACKGROUND OF THE INVENTION
`
`This invention generally relates to micro-fabrication
`of integrated circuits and, particularly, to an improved ‘5
`processandapparatusforpatternformationonsemi-
`conductor wafers to form such circuits.
`Withintheserniconductcrindnstry. productiond
`electronic circuits by very hue scale integration
`mmnmedbyamietydfac-m
`tors which limit yield and inhibit process flexibility.
`These detrimental factors include, for «sample. the
`exposureofwaferstocontaminantsand/orortidation
`during fabrication. Such processing constraints atl-2
`vetselyafl'ectmassproduetionofintearatedcircuiuln”
`addition.conventionalprocelsesaresiowandinordi-
`nately expensive for the fabrication of low—volume
`pmdmmuspcsinganimpedimenttonewdeviceand
`eircnitderigns.
`. 30
`
`Patent Owner’s Response, Paper 14, p. 13
`Exhibit 2018, 1:18-29
`
`
`
`78
`
`2
`
`mask. A layer ofmetai or other suitable conductor is
`thendepositedontoportionsoftheexposedareasofthe
`semiconductor wafer to form the desired interconnec-
`tions between components on the wafer. Though there
`5 are many fabrication technologies. fabrication tech-
`niques, and integrated circuit materials. fabricating the
`damn for the integrated circuit through one or more
`masksas used consistently.
`Depending on the fabrication technologies and tech-
`lodqmudthemmisbuddimrentconfigmdon
`Wendy.‘rheaeconstraintsamcomonlyre-
`faredtoas “geometricdeIisnruIefior “designrulea.”
`Dainmbhdflforeumphspeuficefionsfor
`15 minimummbetwem transistorsand minimum
`separation bum conductors to prevent shorting.
`Patent Owner’s Response, Paper 14, p. 13
`tpecificedomformininnmmenlwidthandspecifica-
`Exhibit 2019, 2:9-19
`tiouformmumwalhtightsandslopeaotwans
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`79
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`Patent Owner’s Response, Paper 14, p. 34
`Adapted from Exhibit 2022, Bryant, p. 413
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`80
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`Patent Owner’s Response, Paper 14, pp. 63, 77
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