`U.S. Patent No. 7,126,174
`
`
`Filed on behalf of Godo Kaisha IP Bridge 1
`
`By: Neil F. Greenblum (ngreenblum@gbpatent.com)
`
`Greenblum & Bernstein, P.L.C.
`
`1950 Roland Clarke Place
`
`Reston, VA 20191
`
`Tel: 703-716-1191
`
`Fax: 703-716-1180
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED,
`and GLOBALFOUNDRIES U.S. INC.,
`Petitioners,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Case IPR2016-012461
`U.S. Patent No. 7,126,174
`____________
`
`PATENT OWNER’S SUR-REPLY TO PETITIONER’S REPLY
`
`
`
`1 Case IPR2016-01247 has been consolidated with this proceeding.
`
`GlobalFoundries U.S. Inc.’s motions for joinder in Cases IPR2017-00925 and
`
`IPR2017-00926 were granted.
`
`
`
`
`
`
`
`
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`TABLE OF CONTENTS
`
`
`
`I.
`
`INTRODUCTION ........................................................................................... 1
`
`II. THE REPLY SHOULD NOT BE CONSIDERED BECAUSE IT
`
`IMPROPERLY RELIES ON NEW ARGUMENTS AND EVIDENCE .......... 2
`
`III. PETITIONER’S NEW ARGUMENTS DO NOT RENDER THE
`
`CHALLENGED CLAIMS OBVIOUS. ........................................................ 6
`
`A. TSMC Has Shifted Its Arguments ................................................................ 6
`
`1. Semiconductor Fabrication Is Highly Complex ......................................... 6
`
`2. The Rejections Cannot Be Sustained Because They Do Not Account .... For
`
`The Consequences Of Differences In Scale Between LOCOS Devices And
`
`Later Generation STI Devices .................................................................... 7
`
`3. There Were Major Obstacles To Implementing STI In The Devices Of
`
`Lee/Lowrey In 1995 ................................................................................... 8
`
`B. TSMC Still Does Not Establish How A POSITA Would Have Combined Lee
`
`and Noble/Ogawa To Arrive At The Claimed Subject Matter ......................10
`
`C. TSMC Does Not Establish How A POSITA Could Have Combined .. Lowrey
`
`and Noble/Ogawa To Arrive At The Claimed Subject Matter ......................23
`
`1. TSMC Does Not Establish That A POSITA Would Or Could Substitute An
` Unembedded STI Into Lowrey ..................................................................23
`
`2. TSMC Asserts Alternative Embodiments of Lowrey In The Reply Not
` Addressed In The Petition .........................................................................36
`
`3. TSMC Has Not Rebutted IPB’s Argument Regarding The L-Shaped
`
`Sidewalls ..................................................................................................40
`
`IV. CONCLUSION ...........................................................................................43
`
`
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`i
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`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`TABLE OF AUTHORITIES
`
`
`
`
`
`CASES
`
`Kinetic Technologies, Inc. v. Skyworks Solutions, Inc., IPR2014-00529, Paper 8,
`p.15, September 23, 2014.................................................................................... 2
`MasterImage 3D, Inc. v. RealD Inc., IPR2015-00040, Paper 42, at 2 (PTAB July
`15, 2015)............................................................................................................. 4
`Rovalma v. Bohler-Edelstahl GmbH & Co. KG, 856 F.3d 1019, 1025 (Fed. Cir.
`2017). .............................................................................................................. 7, 9
`Toshiba Corp. v. Optical Devices, LLC, IPR2014-01447, Paper 34, pp.45-47,
`March 9, 2016. .................................................................................................... 3
`
`
`
`REGULATIONS
`
`37 C.F.R. §42.123(b) ............................................................................................. 3
`37 C.F.R. §42.65(a). .............................................................................................10
`
`
`
`
`
`
`
`
`ii
`
`
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`Exhibit
`No.
`
`2001
`
`2002
`
`2003
`
`2004
`
`EXHIBIT LIST
`
`
`
`Description
`
`Substitute Declaration of Dr. E. Fred Schubert,
`Ph.D. in support of Patent Owner’s Preliminary
`Response filed in IPR2016-01246 on October 5,
`2016.
`
`Schematic illustration of the Chemical Mechanical
`Polishing process from Steigerwald, Murarka, and
`Gutmann, Chemical Mechanical Planarization of
`Microelectronic Materials (1997).
`
`Schematic illustration of the Chemical Mechanical
`Polishing process from the Motorola Company.
`SCSolutions.com. Accessed September 30, 2016.
`http://www.scsolutions.com/chemical-mechanical-
`planarization-cmp-controllers-0.
`
`Photograph of a Chemical Mechanical Polishing
`Tool from the Applied Materials Company.
`BusinessWire.com. Accessed October 5, 2016.
`http://www.businesswire.com/news/home/20040711
`005007/en/Applied-Materials-Revolutionizes-
`Planarization-Technology-Breakthrough-Reflexion.
`
`2005
`
`Troxel, Boning, McIlrath “Semiconductor Process
`Representation.” Wiley Encyclopedia of Electrical
`and Electronics, pp.139 –147 (1999).
`
`2006
`
`U.S. Patent No. 6,052,319 to Jacobs.
`
`2007
`
`U.S. Patent No. 6,952,656 to Cordova et al.
`
`Newly
`Submitted
`
`Served on
`January 27,
`2017
`
`
`
`
`
`
`
`
`
`
`
`
`
`iii
`
`
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`
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`
`
`
`
`Exhibit
`No.
`
`2008
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`Description
`
`Newly
`Submitted
`
`Hunt, “Low Budget Undergraduate
`Microelectronics Laboratory.” University
`Government Industry Microelectronics Symposium,
`pp.81-87 (2006).
`
`
`
`2009
`
`U.S. Patent No. 7,074,709 to Young.
`
`Burckel, “3D-ICs created using oblique processing.”
`Advanced in Patterning Materials and Processes
`XXXIII, pp. 1–12 (2016).
`
`Substitute Declaration of Dr. E. Fred Schubert,
`Ph.D. in support of Patent Owner’s Preliminary
`Response filed in IPR2016-01247 on October 7,
`2016.
`
`Served on
`January 27,
`2017
`
`Corrected Declaration of Dr. E. Fred Schubert,
`Ph.D. in support of Patent Owner’s Response filed
`in IPR2016-01246 on March 24, 2017.
`
`Thompson, L. F. “An Introduction to Lithography.”
`Introduction to Microlithography, ACS Symposium
`Ser., American Chemical Society, pp. 1-13 (1983).
`
`2010
`
`2011
`
`2012
`
`2013
`
`2014
`
`CA1275846 C to Roland et al.
`
`2015
`
`U.S. Patent No. 5,314,843 to Yu et al.
`
`2016
`
`U.S. Patent No. 5,231,306 to Meikle et al.
`
`2017
`
`U.S. Patent No. 4,529,621 to Ballard.
`
`2018
`
`U.S. Patent No. 5,310,624 to Ehrlich.
`
`2019
`
`U.S. Patent No. 5,097,422 to Corbin, II et al.
`
`2020
`
`Declaration of Amanda Dove.
`
`
`
`iv
`
`
`
`
`
`
`
`
`
`
`
`
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`
`
`
`
`
`Exhibit
`No.
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`Description
`
`Newly
`Submitted
`
`2021
`
`U.S. Patent No. 4,952,524 to Lee et al.
`
`2022
`
`2023
`
`2024
`
`2025
`
`2026
`
`Bryant, A.; Haensch, W.; Geissler, S; Mandelman,
`Jack; Poindexter, D.; and Steger, M. “The Current-
`Carrying Corner Inherent to Trench Isolation.”
`IEEE Electron Device Letters, Vol. 14, No. 8, pp.
`412-414 (1993).
`
`Ohe, Kikuyo; Odanaka, Shinji; Moriyama, Kaori;
`Hori, Takashi; and Fuse, Genshu. “Narrow-Width
`Effects of Shallow Trench-Isolated CMOS with n+-
`Polysilicon Gate.” IEEE Transactions on Electron
`Devices, Vol. 36, No. 6, pp. 1110-1116 (1989).
`
`Shigyo, N.; Wada, T.; Fukuda, S.; Hieda, K.,
`Hamamoto, T.; Watanabe, H.; Sunouchi, K.; and
`Tango, H. “Steep Subthreshold Characteristic and
`Enhanced Transconductance of Fully-Recessed
`Oxide (Trench) Isolated 1/4 µm Width MOSFETs.”
`1987 International Electron Devices Meeting, pp.
`636-639 (1987).
`
`Furukawa, T., and Mandelman, J.A. “Process and
`Device Simulation of Trench Isolation Corner
`Parasitic Device.” Journal Of The Electrochemical
`Society, Vol. 135, No. 8, p. 358C, Item 236 (1988).
`
`“Structural Analysis Sample Report” downloaded
`from
`https://www.chipworks.com/TOC/Structural_Analy
`sis_Sample_Report.pdf (2013).2
`
`2027
`
`U.S. Patent No. 4,776,922 to Bhattacharyya et al.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
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`2 Date corrected from 2008 to 2013.
`
`v
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`
`
`Exhibit
`No.
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`Description
`
`Newly
`Submitted
`
`Subbanna, S.; Ganin, E.; Crabbé, E.; Comfort, J.;
`Wu, S.; Agnello, P.; Martin, B.; McCord, M.;
`Newman, H. Ng. T.; McFarland, P.; Sun, J.; Snare,
`J.; Acovic, A.; Ray, A.; Gehres, R.; Schulz, R.;
`Greco, S.; Beyer, K.; Liebmann, L.; DellaGuardia,
`R.; Lamberti, A. “200 mm Process Integration for a
`0.15 µm Channel-Length CMOS Technology Using
`Mixed X-Ray / Optical Lithography.” Proceedings
`of 1994 IEEE International Electron Devices
`Meeting, pp. 695-698 (1994).
`
`Chung, J.; Jeng, M.-C.; Moon, J.E.; Wu, A.T.;
`Chan, T.Y.; Ko, P.K.; Hu, Chenming. “Deep-
`Submicrometer MOS Device Fabrication Using a
`Photoresist-Ashing Technique.” IEEE Electron
`Device Letters, Vol. 9. No. 4, pp. 186-188 (1988).
`
`Tanaka, Tetsu; Suzuki, Kunihiro; Horie, Hiroshi;
`Sugii, Toshihiro. “Ultrafast Low-Power Operation
`of p+-n+ Double-Gate SOI MOSFETS.” 1994
`Symposium on VLSI Technology Digest of Technical
`Papers, pp. 11-12 (1994).
`
`2028
`
`2029
`
`2030
`
`2031
`
`WIPO Publication No. WO 90/05377 to Lowrey.
`
`2032
`
`Kaufman, F. B.; Thompson, D. B.; Broadie, R. E.;
`Jaso, M. A.; Guthrie, W. L.; Pearson, D. J.; and
`Small, M. B. “Chemical‐Mechanical Polishing for
`Fabricating Patterned W Metal Features as Chip
`Interconnects.” Journal of The Electrochemical
`Society, Vol. 138, No. 11, pp. 3460-3465 (1991).
`
`
`
`
`
`
`
`
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`
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`vi
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`
`Exhibit
`No.
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`Description
`
`Newly
`Submitted
`
`Landis, H.; Burke, P.; Cote, W.; Hill, W.; Hoffman,
`C.; Kaanta, C.; Koburger, C.; Lange, W.; Leach, M.;
`and Luce, S. “Integration of chemical-mechanical
`polishing into CMOS integrated circuit
`manufacturing.” Thin Solid Films, Vol. 220, No. 1-
`2, pp.1-7 (1992).
`
`Library of Congress Catalog Record of
`Steigerwald, Murarka, and Gutmann, Chemical
`Mechanical Planarization of Microelectronic
`Materials (1997).
`
`Library of Congress Catalog Record of Introduction
`to Microlithography, ACS Symposium Ser.,
`American Chemical Society (1983).
`
`Library of Congress Catalog Record of IEEE
`Electron Device Letters, Vol. 14, No. 8 (1993).
`
`Library of Congress Catalog Record of IEEE
`Transactions on Electron Devices, Vol. 36, No. 6
`(1989).
`
`Front cover and table of contents of 1987
`International Electron Devices Meeting (1987).
`
`Front cover of Proceedings of 1994 IEEE
`International Electron Devices Meeting (1994).
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Amended version of Exhibit 2026 - “Structural
`Analysis Sample Report” downloaded from
`https://www.chipworks.com/TOC/Structural_Analy
`sis_Sample_Report.pdf (2013).
`
`Served on
`April 14,
`2017
`
`Russell, Phillip E. “SEM-Based Characterization
`Techniques.” Mat. Res. Soc. Symp. Proc., Vol. 69,
`pp.15-22 (1986).
`
`Served on
`April 14,
`2017
`
`2033
`
`2034
`
`2035
`
`2036
`
`2037
`
`2038
`
`2039
`
`2040
`
`2041
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`
`
`vii
`
`
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`
`
`Exhibit
`No.
`
`Description
`
`2042
`
`Front cover and table of contents of Mat. Res. Soc.
`Symp. Proc., Vol. 69 (1986).
`
`Russell, Phillip E. “SEM Based Characterization
`Techniques for Semiconductor Technology.”
`Spectroscopic Characterization Techniques for
`Semiconductor Technology, Vol. 452, pp.183-189
`(1983).
`
`Front cover and table of contents of Spectroscopic
`Characterization Techniques for Semiconductor
`Technology, Vol. 452 (1983).
`
`Served on
`April 14,
`2017
`
`Thorton, P.R.; Davies, I.G.; Shaw, D.A.; Sulway,
`D.V.; Wayte, R.C. “Device Failure Analysis By
`Scanning Electron Microscopy.” Microelectronics
`and Reliability, Vol. 8, pp. 33-53 (1969).
`
`Newly
`Submitted
`
`Served on
`April 14,
`2017
`
`Served on
`April 14,
`2017
`
`Served on
`April 14,
`2017
`
`Served on
`April 14,
`2017
`
`Served on
`April 14,
`2017
`
`2043
`
`2044
`
`2045
`
`2047
`
`2048
`
`2046
`
`Front cover and table of contents of
`Microelectronics and Reliability, Vol. 8 (1969).
`
`Pabbisetty, S.V.; Gavisetty, Kumar; Vaughan,
`Steve; Wills, Kendall Scott. “Electron beam testing
`and its application to VLSI technology.”
`Characterization of Very High Speed
`Semiconductor Devices & Integrated Circuits, Vol.
`795, pp.166-177 (1987).
`
`Front cover and table of contents of
`Characterization of Very High Speed
`Semiconductor Devices & Integrated Circuits, Vol.
`795, (1987).
`
`Served on
`April 14,
`2017
`
`
`
`viii
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`
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`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`
`
`Exhibit
`No.
`
`2049
`
`2050
`
`Description
`
`Wolfgang, Eckhard; Lindner, Rudolf; Fazekas,
`Peter; Feuerbaum, Hans-Peter. “Electron-Beam
`Testing of VLSI Circuits.” IEEE Journal of Solid-
`State Circuits, Vol. SC-41. No. 2, pp. 471-
`481(1979).
`
`Newly
`Submitted
`
`Served on
`April 14,
`2017
`
`Front cover and table of contents of IEEE Journal of
`Solid-State Circuits, Vol. SC-41. No. 2, pp. 471-
`481(1979).
`
`Served on
`April 14,
`2017
`
`2051
`
`Front cover and table of contents of IEEE Electron
`Device Letters, Vol. 9. No. 4 (1988).
`
`Served on
`April 14,
`2017
`
`Front cover and table of contents of 1994
`Symposium on VLSI Technology Digest of Technical
`Papers (1994).
`
`Served on
`April 14,
`2017
`
`Front cover and table of contents of Journal of The
`Electrochemical Society, Vol. 138, No. 11, pp.
`3460-3465 (1991).
`
`Served on
`April 14,
`2017
`
`Served on
`April 14,
`2017
`
`Served on
`April 14,
`2017
`
`Served on
`April 14,
`2017
`
`2052
`
`2053
`
`2055
`
`2056
`
`2057
`
`
`
`2054
`
`Front cover and table of contents of Thin Solid
`Films, Vol. 220, No. 1-2, pp.1-7 (1992).
`
`Exhibit 2012 - Declaration of Dr. E. Fred Schubert,
`Ph.D. in support of Patent Owner’s Response filed
`in IPR2016-01246 on March 24, 2017 with
`amended CV.
`
`Amended Exhibit 2020 - Declaration of Amanda
`Dove.
`
`Transcript of Conference Call conducted on June
`20, 2017
`
`
`
`ix
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`IPR2016-01246
`U.S. Patent No. 7,126,174
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`
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`Exhibit
`No.
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`Description
`
`2058
`
`Drawing by Dr. Sanjay Kumar Banerjee
`
`2059
`
`U.S. Patent No. 5,945,715 to Kuriyama
`
`2060
`
`European Patent Application No. EP 0 739 032 to
`Park et al.
`
`2061
`
`U.S. Patent No. 6,281,562 to Segawa et al.
`
`2062
`
`First and Last Pages of JP H9-172063
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`2063
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`Verified English Translation of First and Last Pages
`of JP H9-172063
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`2064
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`First and Last Pages of JP H9-97838
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`2065
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`Verified English Translation of First and Last
`Pages of JP H9-97838
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`2066
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`First and Last Pages of JP H9-120964
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`2067
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`Verified English Translation of First and Last Pages
`of JP H9-120964
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`2068
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`Patent Assignment Abstract of Title for 08-571,131
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`2069
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`Recorded Assignment assigning the 08-571,131
`application
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`2070
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`Recorded Assignment assigning 08-685,726
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`2071
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`Recorded Assignment assigning the 08-685,726
`application
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`
`
`x
`
`Newly
`Submitted
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`Provided
`on June 27,
`2017
`
`Provided
`on June 27,
`2017
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`Provided
`on June 27,
`2017
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`IPR2016-01246
`U.S. Patent No. 7,126,174
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`Exhibit
`No.
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`Description
`
`Newly
`Submitted
`
`2072
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`Patent Assignment Abstract of Title for 08-340,341
`
`2073
`
`Recorded Assignment assigning the 08-340,341
`application
`
`2074
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`Executed Declaration of Mr. Hajime Ogawa
`
`2075
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`U.S. Patent No. 6,709,950 to Segawa et al.
`
`2076
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`U.S. Patent No. 6,967,409 to Segawa et al.
`
`2077
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`2078
`
`Order Granting Joint Motion To Dismiss All Claims
`And Counterclaims With Prejudice, Godo Kaisha IP
`Bridge 1 v. Broadcom Limited et al., USDC EDTEX
`2:16-cv-00134-JRG-RSP, Document 337, July 5,
`2017.
`
`Deposition Transcript of Dr. Sanjay K. Banerjee
`dated June 27, 2017 and Errata Sheet (dated June
`28, 2017) from the Deposition of Dr. Sanjay K.
`Banerjee
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`IPR2016-01246
`U.S. Patent No. 7,126,174
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`
`
`I.
`
`INTRODUCTION
`
`Trial was instituted in pertinent part based upon Petitioner’s arguments that a
`
`Shallow Trench Isolation (STI) as disclosed in specific embodiments of Noble and
`
`Ogawa could be simply substituted for the LOCOS (Local Oxidation of Silicon)
`
`isolations disclosed in Lee and Lowrey. The Petitions omitted any explanation of
`
`“how” the elements of the embodiments would or could have been combined at the
`
`time of the invention. Indeed, the Reply admits that the Petitions did not discuss
`
`“how” to combine the prior art, as TSMC believed there was no need to do so. See
`
`Reply, p.18, n.9.
`
`For the first time in its Reply, Petitioner TSMC argues “how” an STI could
`
`allegedly be substituted for the LOCOS disclosed in Lee/Lowrey. However,
`
`TSMC no longer focuses on the embodiments of Noble/Ogawa, which it argued in
`
`the Petitions, instead relying on different embodiments and new evidence.
`
`This Sur-reply was authorized in Paper 28, July 6, 2017. Petitioner’s Reply
`
`should not be considered because it contains new arguments and relies on new
`
`evidence to support arguments that should have been set forth in the Petitions.
`
`Additionally, as explained herein, both Petitioner’s new and original arguments
`
`contain fundamental fatal flaws that do not render the challenged claims obvious.
`
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`IPR2016-01246
`U.S. Patent No. 7,126,174
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`
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`II. THE REPLY SHOULD NOT BE CONSIDERED BECAUSE IT
`IMPROPERLY RELIES ON NEW ARGUMENTS AND EVIDENCE
`
`From the outset, Patent Owner (“PO” or “IPB”) asserted that neither Petition
`
`(‘01246 or ‘01247) described how the prior art could be combined to form the
`
`claimed subject matter:
`
`Neither the Petition in IPR2016-01246 nor the Petition in
`
`IPR2016-01247 describes how the fabrication processes
`
`disclosed in the prior art references could be combined to form
`
`the subject matter recited in the challenged claims.
`
`PO’s Preliminary Responses, Paper 7, p.3; see also Kinetic Technologies, Inc. v.
`
`Skyworks Solutions, Inc., IPR2014-00529, Paper 8, p.15, September 23, 2014.
`
`(Finding the declaration did not explain the “how,” “what,” and “why” of the
`
`proposed combination of references and that “statements of general principles from
`
`the case law that a proposed combination ‘involves no more than a combination of
`
`known elements,’ or that a proposed combination is ‘the predictable use of such
`
`elements according to their established functions,’ or that a proposed combination
`
`yields ‘predictable results’ … are conclusions; they are not a substitute for a fact-
`
`based analysis of the proposed combination of references necessary to support
`
`those conclusions.”)
`
`TSMC did not seek to file supplemental information under 37 C.F.R.
`
`§42.123(b), even though TSMC was aware prior to the institution of the
`
`
`
`2
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`IPR2016-01246
`U.S. Patent No. 7,126,174
`
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`proceeding of the need for supplemental information as to “how” the prior art
`
`could be combined. Rather, TSMC filed 35 new exhibits with the Reply
`
`(Exs.1025-1059), including another expert declaration of 93 pages (not including
`
`attachments). Ex.1057. For at least these reasons, the Reply should not be
`
`considered. Toshiba Corp. v. Optical Devices, LLC, IPR2014-01447, Paper 34,
`
`pp.45-47, March 9, 2016.
`
`The following are a few examples of new arguments and evidence raised in
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`the Reply not raised in the Petitions:
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`• The Petitions argued only “embedded” embodiments of Noble/Ogawa
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`because they included many of the same elements as Lee/Lowrey whereas
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`the Reply now argues only “un-embedded” references/embodiments.
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`Institution Decision, p. 12.
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`• The Reply newly argues a technique using a substrate as a polish/etch-stop.
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`Reply, pp.3-7.
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`• The Reply newly argues using a dedicated polish/etch-stop layer. Reply, p.4.
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`• The Reply newly argues Dash (Ex.1058), Horiguchi (Exs.1028/1029) and
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`Sumi (Exs.1026/1027). Reply pp.11-15.3
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` TSMC improperly asserts that Dash, Horiguchi and Sumi are already art “of
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`record” because they are incorporated by reference or appear on the face of the
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`• TSMC admits that the argument/evidence in the Reply in Section II.A.2.b.
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`was not presented in the Petitions. Reply, p.18, n.9.
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`• The Reply newly argues: “In one process, Lowrey omits the optional ion-
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`adjustment implant in FIG. 2, and in another, Lowrey uses a deposited oxide
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`instead of LOCOS oxidation layer 21 to mask the adjustment implant.”
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`Reply p.22.
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`• In the Reply, Ueda4, Mandelman, Dash, Sumi and Horiguchi are relied upon
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`to support TSMC’s new argument that a POSITA knew how to make raised
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`STI without first forming gate layers. Reply, pp.8-17. These exhibits are
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`asserted to disclose unembedded trench isolations. Id. However, in the
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`Petitions, TSMC relied upon the embedded trench isolations disclosed in
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`Noble/Ogawa because they had other elements similar to Lee/Lowrey.
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`Institution Decision, p. 12.
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`’174 patent. Reply, pp.11-12. “Art of record” as discussed in MasterImage 3D,
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`Inc. v. RealD Inc., IPR2015-00040, Paper 42, at 2 (PTAB July 15, 2015) pertains
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`to a motion to amend, not art supporting the grounds on which trial was instituted.
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` IPB has moved to exclude Ueda as not available as prior art against the ‘174
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`patent. Paper 29, July 12, 2017.
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`IPB has separately filed a Motion To Exclude Evidence requesting TSMC’s
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`new arguments and evidence be excluded. Paper 29, July 12, 2017.
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`III. PETITIONER’S NEW ARGUMENTS DO NOT RENDER THE
`CHALLENGED CLAIMS OBVIOUS.
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`A. TSMC Has Shifted Its Arguments
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`The Petitions argued embodiments from Noble/Ogawa that teach an STI
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`embedded within a gate electrode. Noble Fig. 9, Ogawa Fig. 4(c). The Petitions did
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`not say how the teachings of these references were to be blended with Lee/Lowrey.
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`Apparently realizing a person of ordinary skill in the art (“POSITA”) would not
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`have combined the embedded STI embodiments of Noble/Ogawa with
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`Lee/Lowrey, TSMC shifts its arguments to rely on other references alleged to teach
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`isolations not-embedded within a gate electrode. In other words, ignoring the
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`teachings of the embodiments of Noble/Ogawa relied on in the Petitions, TSMC
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`now picks and chooses disclosures of unembedded STI and argues that they can be
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`simply substituted into Lee/Lowrey. As discussed herein, Petitioner’s new
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`arguments are fundamentally flawed because there would be no motivation to
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`combine either “embedded” or “unembedded” trench isolations with the primary
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`references because as now explained by Petitioner a POSITA would not substitute
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`them into Lee/Lowrey.
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`1. Semiconductor Fabrication Is Highly Complex
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`Si ICs are extremely complex systems (Exs.2013-2020). In 1995, there were
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`millions of transistors on an Si IC. Several hundred steps were typically used to
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`fabricate these devices. Up to 10,000 transistors would have fit on the head of a
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`pin. The small feature sizes (e.g., gate electrode length) and high density of circuits
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`make precision, cleanliness and accuracy mandatory requirements in the
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`manufacturing environment. Petitioner states that “complexity of IC fabrication
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`and the technical community’s recognition of that premise are not at issue in this
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`case.” Paper 13, p. 7; Paper 16, p. 6. Complexity is directly related to the amount
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`of description necessary to support an obviousness rejection. Rovalma v. Bohler-
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`Edelstahl GmbH & Co. KG, 856 F.3d 1019, 1025 (Fed. Cir. 2017).
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`2. The Rejections Cannot Be Sustained Because They Do Not
`Account For The Consequences Of Differences In Scale Between
`LOCOS Devices And Later Generation STI Devices
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`The development of Si ICs devices has proceeded in terms of “technology
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`generations” also called “technology nodes” or “process nodes”. The geometrical
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`length associated with a specific technology node, e.g., 500 nm, represents a
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`characteristic feature size, typically the gate length, of an Si IC. It is generally
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`accepted that the feature size or “node” decreases by “a factor of .7 from one
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`generation to the next.” Ex.2078, 22:1-27:5. Scaling both dimensions of a planar
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`structure by the factor 0.7 results in a device area reduction of 0.7 x 0.7 = 0.49.
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`That is, a new technology node will be able to accommodate approximately twice
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`as many transistors per unit area as the previous technology node.
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`TSMC’s asserted motive for substituting STI for LOCOS is premised on the
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`substantial resulting node-reduction that such a substitution could provide (Reply
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`p.2; Institution Decision, p. 12). While STI was more complex to implement than
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`LOCOS isolation, by far the primary, if not the only reason to substitute STI was
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`the reduction in node size that it provided. Correspondingly, the ‘174 patent is
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`directed to an STI smaller than .5 micron. Ex.1001, 1:34-36; Petition, pp.4-6;
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`Ex.1004, ¶¶51-53; Ex.2078, 22:1-27:5.
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`3. There Were Major Obstacles To Implementing STI In The
`Devices Of Lee/Lowrey In 1995
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`It is generally accepted that certain process technologies may not be
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`transferrable from technology node to technology node. For example, the
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`photolithographic tools that are required for pattern-transfer form a photo-mask to
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`an Si wafer have changed regularly. Additionally, doping procedures5 have
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`changed significantly throughout the development of Si ICs. Also, the silicidation
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`of the source, gate and drain, the introduction of CMP, and the introduction of
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`metal gates have changed Si ICs.
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`5 Doping procedures include S/D (Source/Drain) light doping (shallow doping),
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`S/D heavy doping (deep doping), n- and p-type well doping, channel-stopper
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`doping, and threshold-voltage-adjustment doping.
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`The ’174 patent’s priority application was filed in 1995. In 1995, the next
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`generation node was at about 250-350 nm. Ex.1001, 1:31-36 (“As a result, the
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`dimension of a transistor is changed …. This dimensional change is unallowable in
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`the refinement of a semiconductor device after the 0.5 µm generation.”)(emphasis
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`added); Ex.2078, 22:21-23:9.
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`A POSITA would know that certain process technologies that are suited for
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`one technology node, could be unsuitable for another node. For this reason, it is
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`imperative to consider the context of a specific node when combining technologies
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`from different devices. In addition, when analyzing obviousness, it is imperative
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`to determine whether the process sequence suitable for a past node device
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`(LOCOS) would be suitable for the next-generation node device (STI). Ex.2011,
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`¶55. An obviousness analysis that does not take this into consideration, and admits
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`that it was not concerned with the details as to how technologies could be
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`combined is fatally flawed. Ex.2078, 210:6-10 (Dr. Banerjee testifying that “you
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`don’t spell out in gory detail every single aspect of every single process.”). That is,
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`when combining references in an obviousness combination, it is necessary to
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`consider the issue in the context of the complexity of the combinations at the time
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`of the invention, 1995. Rovalma v. Bohler-Edelstahl GmbH & Co. KG, 856 F.3d
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`1019, 1025 (Fed. Cir. 2017). Dr. Banerjee did not do this. Ex.2078, 81:4-13;
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`227:2-228:2; 270:8-12.
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`While the Lee doping process may have been suitable for the technology
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`nodes of the late 1980’s and very early 1990’s, it was unsuitable for the technology
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`nodes as of the date of the invention (1995) below the 500 nm technology node,
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`e.g., the 350/250 nm node.
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`Dr. Banerjee’s opinions do not take node sizes into account, such that he
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`does not address whether the process sequences, dimensions and technologies
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`suitable for past node devices would be suitable for the next-generation node.
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`Ex.2078, 84:10-18. For this reason alone, Dr. Banerjee’s entire analysis is based
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`on an improper perspective and should be afforded little weight. 37 C.F.R.
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`§42.65(a).
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`B. TSMC Still Does Not Establish How A POSITA Would Have
`Combined Lee and Noble/Ogawa To Arrive At The Claimed Subject
`Matter
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`The ‘01246 Petition argued obviousness over Lee in view of Noble/Ogawa.
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`IPB responded that there was no explanation of how these references could be
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`combined. Response, pp.43-94.
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`As discussed earlier, both Noble/Ogawa first form a gate isolation layer and
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`gate conductor layer into which an STI is embedded. In Lee, the LOCOS isolation
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`is formed prior to the gate isolation layer and gate conductor layer. Ex.2012,
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`¶¶124-130. As such, Lee is not combinable with Noble/Ogawa. Ex.2012, ¶¶186 et
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`seq. For this reason, as explained in the Response on pp.43-94, Lee in view of
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`Noble/Ogawa does not render any of the challenged claims obvious.
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`TSMC for the first time depicts their newly proposed combination using an
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`unembedded STI:
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`Reply, pp.19-20.
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`TSMC asserts to form the device shown in Fig. 15’, instead of forming a
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`LOCOS, a “raised STI 113 is formed by any of the processes discussed above”,
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`i.e., in the newly submitted exhibits. Reply, p.19. “Then, as in Lee, gate oxide 115,
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`polysilicon 117, and silicon nitride/silicon oxynitride layer 118 are successively
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`deposited.” Id. “The remainder of the process would have proceeded as Lee
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`teaches…” Reply, p.20. TSMC states that “dozens of pages” in its Petition
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`explain “how and why” a POSITA would make the Lee combination, but identify
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`only two pages, and the “how” argument does not appear there or anywhere else in
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`the Petition. Reply, pp.27-28; ‘1246 Petition, pp.21, 70.
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`A key feature of the Lee process is shown in Figs. 5 and 6 of Lee where the
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`doping sequence is described. Lee discloses an unusual heavily-doped/lightly-
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`doped process sequence. Lee’s doping sequence starts with the formation of a
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`three-element gate sidewall (Lee Fig. 5 elements 19, 21, and 23), and the deep S/D
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`implant 27 (Ex.1002, 3:49-4:33). The deep or heavily-doped S/D implant region 27
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`is shown with red color in Lee’s colorized Fig. 5 below:
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`After completing the deep implant, Lee proceeds to remove the third
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`sidewall element 23 to then perform the shallow or lightly-doped implant. The
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`lightly-doped S/D implant region 35 is shown with pink color in Lee’s colorized
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`Fig. 6 below:
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`This doping sequence (first deep doping then shallow doping) is opposite of
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`how an implantation sequence is normally performed. Ex.2012, ¶98; Ex.2078,
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`87:9-90:8.
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`TSMC asserts that regions of higher doping and lower doping were standard
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`in the art. ‘1246 petition, pp.25-26. But because of Lee’s reverse process order due
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`to unreliable diffusion, the resulting doping would be unworkable with an STI.
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`The ‘174 patent performs these fabrications steps in opposite order, i.e.,
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`before the sidewalls are positioned, a shallow implant is performed, then the
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`sidewalls are formed, and then the deep implant is formed.
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`Doping procedures in Si ICs have evolved over time. Of particular
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`relevance is the diffusion and spatial redistribution of dopants subsequent to an
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`implantation process which is the result of thermal annealing or “drive-in.”
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`Ex.1002, 4:38-40; 6:38-40. An expert would explain that this “drive-in” process (i)
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`repairs crystal defects formed during high-energy implantation, (ii) activates
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`doping atoms to become electrically active, and (iii) causes doping atoms to diffuse
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`and redistribute. Because the crystal is damaged during the high-energy
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`implantation process, the diffusion is enhanced during a transitionary short time (in
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`the millisecond to second range) while the crystal defects are repaired. The short,
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`transitionary diffusion process is known as “transient enhanced diffusion” or TED.
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`In order to make the FET (field-effect transistor) functional, the dopants of
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`the shallow implant must diffuse to at least the right-hand-side edge of the gate
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`conductor 15; this location is indicated by a green-colored arrow in Lee’s
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`col