`
`Transcript of Sanjay Banerjee
`
`Date: June 27, 2017
`Case: Taiwan Semiconductor Manufacturing Co., LTD -v- Godo Kaisha IP Bridge 1
`(PTAB)
`
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`WORLDWIDE COURT REPORTING | INTERPRETATION | TRIAL SERVICES
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`Page 1 of 374
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`Exhibit 2078
`TSMC v. IP Bridge
`IPR2016-01246
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`
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`
`
`Transcript of Sanjay Banerjee
`
`Date: June 27, 2017
`Case: Taiwan Semiconductor Manufacturing Co., LTD -v- Godo Kaisha IP Bridge 1
`(PTAB)
`
`Planet Depos
`Phone: 888.433.3767
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`WORLDWIDE COURT REPORTING | INTERPRETATION | TRIAL SERVICES
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`Page 2 of 374
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` UNITED STATES PATENT AND TRADEMARK OFFICE
` ___________________
` BEFORE THE PATENT TRIAL AND APPEAL BOARD
` ______________________
` TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
` and GLOBALFOUNDRIES U.S., INC.,
` Petitioners
` v.
` GODO KAISHA IP BRIDGE 1
` Patent Owner
` ______________________
` Case IPR2016-01246
` U.S. Patent No. 7,126,174
` ______________________
` Case IPR2016-01247 has been consolidated with
`this proceeding.
`GlobalFoundries U.S. Inc.’s motions for joinder in
`Cases IPR2017-00925 and IPR2017-00926 were granted.
` DEPOSITION OF SANJAY BANERJEE
` Reston, Virginia
` Tuesday, June 27, 2017
` 8:58 a.m.
`Job No: 149586
`Pages: 1-
`Reported by: Karen Brynteson, RPR, RMR, CRR, FAPR
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`2
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` The deposition of SANJAY BANERJEE held at the
`offices of:
`
` FINNEGAN HENDERSON, LLP
` 11955 Freedom Drive
` Suite 800
` Reston, Virginia 20190
`
` Pursuant to Notice, before Karen Brynteson,
`Registered Professional Reporter, Registered Merit
`Reporter, Certified Realtime Reporter, Fellow of the
`Academy of Professional Reporters.
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`3
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` A P P E A R A N C E S
`ON BEHALF OF THE PETITIONER:
` E. ROBERT YOCHES, ESQ.
` J. PRESTON LONG, Ph.D., ESQ.
` Finnegan, Henderson, Farabow,
` Garrett & Dunner LLP
` 901 New York Avenue, N.W.
` Washington, D.C. 20001-4413
` 202-408-4000
` bob.yoches@finnegan.com
`ON BEHALF OF THE PATENT OWNER:
` NEIL F. GREENBLUM, ESQ.
` AMANDA DOVER
` VERANE SAGNOL
` Greenblum & Bernstein P.L.C.
` 1950 Roland Clarke Place
` Reston, Virginia 20191
` 703-716-1191
` Ngreenblum@bgpatent.com
`Also Present:
` Willy Chang, TSMC
` Fred Schubert
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`4
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` C O N T E N T S
`SANJAY BANERJEE EXAMINATION
`By Mr. Greenblum................. 6
`By Mr. Yoches.................... 303
`
` AFTERNOON SESSION: 169
` E X H I B I T S
`TSMC EXHIBIT NO: PAGE NO:
`1001 21
`1002 68
`1004 10
`1010 231
`1015 98
`1017 179
`1024 10
`1057 9
`1058 240
`IP BRIDGE
`2013 220
`2014 221
`2015 222
`2016 223
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`TSMC EXHIBIT NO: PAGE NO:
`2019 224
`PAPERS:
`Paper 2 133
`Paper 8 250
`NEWLY MARKED EXHIBITS:
`2058 220
`2059 289
`2060 293
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`6
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` P R O C E E D I N G S
` (8:56 a.m.)
`Whereupon--
` SANJAY BANERJEE,
`having been first duly sworn, was examined and
`testified as follows:
` EXAMINATION BY COUNSEL FOR PATENT OWNER
`BY MR. GREENBLUM:
` Q. Dr. Banerjee, in 1995, what kind of work
`were you doing at that time?
` A. In 1995, I was at the University of Texas
`at Austin, and I was working on a variety of things,
`including CMOS devices, transistor fabrication,
`acquisition, modeling.
` Q. I didn't hear the last.
` A. Modeling.
` Q. Modeling.
` A. Among other things.
` Q. And did you have any industrial
`involvement at that time?
` A. I had funding from various industries,
`including from an organization called SEMATECH,
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`7
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`which is a consortium of industries. SEMATECH was
`located in Austin, and we had a center funding from
`SEMATECH. And I believe that was still going on in
`1995, but I'd have to look at my CV.
` Q. And at that time, you were teaching
`where?
` A. At the University of Texas at Austin.
` Q. At Austin. And is the same thing true
`for 1996?
` A. Yes.
` Q. And going back in time before that, did
`you have any actual industrial fabrication
`experience?
` A. Yes.
` Q. Where and when was that?
` A. After I graduated from Illinois in '83, I
`joined Texas Instruments in Dallas as part of the
`four-megabit DRAM team, where I worked on process
`integration issues, transistor fabrication
`characterization, modeling.
` Q. And that was until what year?
` A. Until 1987 when I joined the University
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`8
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`of Texas.
` Q. What were the node sizes in 1987 when you
`left industry?
` A. I don't remember precisely. I'd have to
`look at my notes. It was sub-1 micron around that
`time.
` Q. How many nanometers would that be?
` A. Once again, I'd have to look at the --
` Q. Roughly, roughly.
` A. I'm speaking from memory. Maybe 500
`nanometers.
` Q. That was --
` A. Half a micron, approximately. But once
`again, I'd have to look at the ITRS roadmap. And I
`don't recall exactly.
` Q. And that would have been in 1987?
` A. Approximately, yeah.
` Q. And you said you would have to look at
`what?
` A. There's a roadmap for instance. It's not
`-- at one point, it was called the international
`technology roadmap for semiconductors. And I was
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`part of that committee for several years. So that
`has a nice summary of process nodes as a function of
`time including some projections. So that would be
`one source, but you could also look at publications
`around the time frame to get an idea or products
`made by companies around the time frame to look at
`what the node sizes were.
` Q. Now, in 1995, what is your recollection
`the node size was?
` A. Well, you know, the nodes, the transistor
`size is scale according to what's known as Moore's
`Law.
` Q. Spell it.
` A. Moore's Law, M-o-o-r-e's.
` Q. Oh, yes. Moore's Law, okay.
` A. Where roughly every 18 months or so
`transistor dimensions go down, densities double and
`things like that. So once again I'd have to look
`at, you know, papers from that time frame or the --
`you know, the Moore's Law chart very precisely.
` Q. Now, in preparing your opinion, did you
`take any account whatsoever of the IT roadmap or
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`10
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`publications at the time -- well, I'll start off
`with the IT roadmap.
` A. It's called ITRS roadmap.
` Q. ITRS?
` A. Yes.
` Q. I'm sorry. Did you take any account of
`it?
` A. Sure.
` Q. Well, you never mentioned it anywhere in
`your opinion.
` A. If I may get a copy of my declarations, I
`believe I cited that.
` Q. Okay.
` A. In my -- in my declaration.
` Q. Okay. And would it have been in your
`first declaration or your second?
` A. May I have copies of both, please?
` Q. Okay, sure. So this is your --
`Exhibit 1057, which was your reply declaration. And
`then we'll get you your other declaration.
` (TSMC Exhibit 1057 was marked for
`identification.)
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`11
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` MR. GREENBLUM: And I'll also give you
`Exhibit 1004, which was your original declaration.
` THE WITNESS: Okay.
` MR. GREENBLUM: 1024.
` MS. DOVE: It's two IPRs.
` MR. GREENBLUM: Hold on a second.
`There's 1004 and 1024. And they were both for the
`original IPR. And then we will give you your reply
`declaration shortly.
` THE WITNESS: I've got that already.
` MR. GREENBLUM: What is that?
` THE WITNESS: I've got the reply already.
`BY MR. GREENBLUM:
` Q. And 1057, that's correct. Sorry, that's
`correct.
` (TSMC Exhibits 1004 and 1024 were marked
`for identification.)
`BY MR. GREENBLUM:
` Q. I'm trying to help you by looking it up
`and doing a search.
` A. Right. I see that. I see that. I see
`that in my reply declaration.
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` Q. Okay. It's in the reply?
` A. Yeah. And it's Exhibit 1054. At that
`time, it was called the national --
` MR. YOCHES: Get the number right of the
`exhibit.
` THE WITNESS: The number of the exhibit,
`it's from the --
` MR. YOCHES: 1057.
` THE WITNESS: 1057. But I was looking at
`the exhibit of the roadmap.
`BY MR. GREENBLUM:
` Q. And what page is it on?
` A. It's on page 13. It says Semiconductor
`Industry Association, the national technology
`roadmap for semiconductors, which is Exhibit 1054.
` Q. So here it's also called the SLA roadmap?
` A. SIA, semiconductor industry.
` Q. SIA?
` A. Yes. Semiconductor Industry Association.
` Q. Okay. Roadmap. So it goes by both
`names?
` A. Yeah, some people called it that, yeah.
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` Q. Okay. And then did you discuss it at all
`as part of your analysis?
` MR. YOCHES: Objection.
` THE WITNESS: I did.
`BY MR. GREENBLUM:
` Q. Where?
` A. So, for instance --
` Q. If you tell me which acronym that you
`used for it, I can search it on here and make it
`easier for you.
` A. Maybe you could look under 1054, is the
`exhibit number.
` Q. But, I mean, do you call it SIA roadmap
`in here or do you call it NTRS roadmap or --
` A. I guess SIA roadmap. And it's in
`paragraph 55.
` Q. Here it is. Yes. Hold on a second.
`Okay. Go on. Is there anything else? I think
`that's the only place that I see it in my search,
`but I don't want to -- I find it nowhere else.
` A. Okay.
` Q. Do you think it might be somewhere else?
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`14
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` A. It would be in the background of
`isolation technologies. So that's probably the one
`place I've mentioned it.
` Q. Okay. Now, what it was cited for here is
`that you assert that it identified STI as an
`alternative to LOCOS isolation in CMOS devices. Do
`you see that?
` A. Yes.
` Q. Did you ever in your report use the SIA
`roadmap in connection with node sizes? Did you ever
`rely upon it for the node sizes?
` MR. YOCHES: Objection.
` THE WITNESS: Well, in -- I can't
`remember if it was in the original declaration or
`the reply, but I did talk about -- I believe if I
`may have a copy of the '174 patent. I mean, that
`also has some.
`BY MR. GREENBLUM:
` Q. Okay. Well, we'll get to the '174 in a
`minute. I don't want you to think that I'm
`withholding it from you.
` A. Sure.
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` Q. But my question is, first, did you take
`account of it in your report? Node size I'm talking
`about. Is it taken account of anywhere in your
`report?
` A. Yes, I did.
` Q. And can you tell me where?
` MR. YOCHES: Objection.
`BY MR. GREENBLUM:
` Q. I'll point out that my search for the
`word "node" in the declaration we were just talking
`about does not appear in the declaration, but you go
`ahead and see if you can find it.
` MR. YOCHES: Objection.
` THE WITNESS: If you look at my -- one of
`the original declarations.
`BY MR. GREENBLUM:
` Q. Which one is it?
` A. TSMC Exhibit 1004, and if you look at
`paragraph 53.
` Q. Yeah.
` A. I say clearly over here because the two
`processes are so similar otherwise, STI and LOCOS
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`16
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`are interchangeably and functionally equivalent.
`And I have several cites. And in the 1990s, when
`transitioning from the half micron to the quarter
`micron process node, the industry faced a design
`choice, increase device density and add expense
`using trench isolation or maintain device density
`and costs, using LOCOS. The industry has always
`decided in favor --
` Q. All right. So you say in here that they
`were transitioning from 0.5, and you said before
`that would have been in 1987?
` MR. YOCHES: Objection.
`BY MR. GREENBLUM:
` Q. Is that correct?
` A. As I told you, I don't remember offhand
`exactly at what point.
` Q. Okay.
` A. The nodes were. And I would also add
`that at a point in time, different technologies may
`use different gate lengths. Different companies may
`use slightly different gate lengths. It's not a
`fixed number at a precise point in time.
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` Q. It's just a general measure?
` A. Yes.
` Q. And it's transitioning from 0.5 to 0.25.
`Am I to understand that by 1995 they were getting to
`0.25? I'm asking.
` A. Once again, I mean, without having access
`to the appropriate references, I couldn't give you
`precisely when the transition happened, and the
`transition is not a precise point in time. These
`are just general statements. Approximately in that
`time frame, the transition was happening.
` Q. Okay. And is there any place else that
`you talk about node size?
` A. Well, if you look at TSMC Exhibit 1024.
` Q. Okay. That would be the same thing
`again?
` A. Similar, yeah.
` Q. Why don't we make it for the record. But
`I'm saying I would like him to point out the
`paragraph for the record. I assume it's the same
`one?
` Doctor, it is kind of warm in here. If
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`you want, you can take off your jacket. It doesn't
`offend me.
` A. Okay.
` MR. GREENBLUM: Rob, you can do the same
`if you want.
` MR. YOCHES: Thank you.
` THE WITNESS: Thank you.
` MR. GREENBLUM: I didn't want you to feel
`left out.
` THE WITNESS: Yeah, if you look at
`paragraph 53, because the two processes are so
`similar otherwise, SGI and LOCOS are
`interchangeable.
`BY MR. GREENBLUM:
` Q. It is the same thing again, is that it?
` A. Basically, yes.
` Q. Okay. So it's essentially the same
`statement in Exhibits 1004 and 1024, node size. Is
`there anything else about node size in -- in your
`declaration?
` A. Offhand, I can't remember if I used the
`precise term "node" somewhere else, but it's
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`implicit in many cases when I talk about the
`background.
` Q. Okay. And just if you could -- I don't
`find it in your Exhibit 1057. But could you confirm
`-- I mean, I did a word search for it and I don't
`see it.
` A. What I meant was I may not have used the
`word "node" precisely somewhere else.
` Q. I understand.
` A. But, you know, many of the references
`that I cite perhaps use the word "node" in those
`references also. I -- I would have to check.
` Q. Okay. Well, the references, we'll get to
`them in a minute.
` A. Okay.
` Q. But to your knowledge as you sit here
`now, your best recollection is it was in paragraph
`53 of Exhibits 1024 and 1004 that you referenced
`node size and nowhere else?
` A. I believe that's true.
` Q. And then in 1057, you do talk about the
`NTR -- the National Technology roadmap in paragraph
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`55. Would you take a look at that, please. Do you
`have it?
` A. Yes.
` MR. YOCHES: Is there a question?
`BY MR. GREENBLUM:
` Q. Yeah, did you finish reading it?
` A. Yes.
` Q. Okay, thank you. The -- what I see you
`talking about here is, again, the reference to the
`use of this roadmap and the SIA roadmap for purposes
`of identifying STI as an alternative to LOCOS
`isolation in CMOS devices. Is that correct?
` A. Yes.
` Q. There's no discussion here about node
`size or anything of the sort?
` A. CMOS, we call it CMOS --
` Q. Okay.
` A. -- in general, but it doesn't matter
`really, but -- excuse me, what is the question that
`you said again?
` Q. There is no discussion here about node
`size or anything of the sort -- of the sort in
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`paragraph 55?
` A. Well, these road maps, the NTSR, which is
`the predecessor to the ITRS, is full of charts
`discussing node sizes. So --
` Q. Well, I understand. I'm sorry. I cut
`you off. Did you finish?
` A. Yes. So I don't -- I may not have used
`the word "node" precisely in this paragraph, but
`it's embedded in this roadmap.
` Q. But what you cited it for was that STI
`was an alternative to LOCOS. You did not cite it
`for node sizes. Am I correct?
` A. No, that's implicit in there. So as
`technology evolves according to Moore's Law and it
`goes to smaller and smaller dimensions or node
`sizes, it was a natural progression to go from
`LOCOS, which is the earlier form of device
`isolation, to STI, which solved some of the problems
`of LOCOS.
` Q. But you didn't talk about node size in
`here?
` A. I didn't use the term "node size" in this
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`paragraph, but the roadmaps that I cite have
`numerous charts and a lot of discussions of how
`technology evolves as a function of node size. And
`that's one of the primary goals of this roadmap, if
`you will.
` Q. Okay. Now, you mentioned before you
`wanted to take a look at the '174 patent because --
`when I asked about size. Do you recall that or you
`don't?
` A. Yes, I do.
` Q. So let's -- let's show you the '174
`patent, which is Exhibit 1001.
` (TSMC Exhibit 1001 was marked for
`identification.)
` MR. GREENBLUM: Have I been giving you
`copies?
` MR. YOCHES: Yes. They make it here
`eventually.
` MR. GREENBLUM: Okay, thank you.
`BY MR. GREENBLUM:
` Q. So you were saying to me before that that
`patent discusses node size? Maybe I misunderstood
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`you.
` A. Yes. Yeah, I did mention that.
` Q. And what specifically are you referring
`to?
` A. So, for example, in column 1, line 36, in
`the background, let me read that off. So this
`dimensional change is unallowable in the refinement
`of a semiconductor device after the .5 micron
`generation. Generation means node in this context.
` Q. And so do you understand what -- what
`node the '174 patent was speaking; in other words,
`the description here is describing a device in what
`node size?
` MR. YOCHES: Objection.
` THE WITNESS: If I read the same
`paragraph further down, it also discusses -- this is
`also part of the background. It says, "For example,
`IBM Corporation has introduced the trench isolation
`structure as a .5 micron CMOS process, meaning node,
`for the mass production of MPU." That's
`microprocessor unit. And they cite this IBM Journal
`of Research and Development, Volume 39, Number 1/2,
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`published in 1995.
` So this is motivating this '174 patent
`that as you go below -- around half micron or below,
`there's a strong motivation to go from LOCOS to STI.
`However, I must point out these things are not
`precisely defined in time or in node size. As I
`mentioned earlier, there's a tradeoff between LOCOS
`and STI technologies. LOCOS is cheaper or simpler,
`but it consumes more real estate compared to STI.
` So it's not as if every company made this
`transition at a precise node size at a precise point
`in time.
`BY MR. GREENBLUM:
` Q. As of 1995, was this choice there? Were
`people making this choice?
` A. Yes. As I --
` MR. YOCHES: Objection. Go ahead.
` THE WITNESS: As I just read, IBM
`Corporation has introduced the trench isolation
`structure as a .5 micron CMOS process, meaning node
`size, for the mass production of a microprocessor.
`So that's one example of a leading-edge company
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`which made the transition.
`BY MR. GREENBLUM:
` Q. And this patent was talking about, we
`said before, after the 0.5 micron generation, what
`would be the next generation after .5 micron
`generation?
` A. So, typically, according to Moore's Law
`scaling, when you go from one node to the next, you
`multiply the dimensions by a factor of roughly .7.
`Once again, these are not precise numbers.
` And, in fact, what the node refers to in
`terms of the dimensions of the transistors also has
`changed a little bit. And in those times, generally
`speaking, the node size referred to the transistor
`gate length, but that's not always necessarily been
`the case. But to answer your question, it's roughly
`a factor of .7 from one generation to the next.
` Q. So back to my question. If you
`multiply .7 times .5, I get .35 would be roughly the
`next node.
` A. Roughly, because -- and the reason for
`that is .7 square is .49, so that leads to a
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`doubling of the density. And, once again, these are
`approximate numbers.
` Q. Okay. So at point -- at .35, the density
`on the transistor would be double what it is at .5?
` A. If you scale the linear dimensions
`by .7 --
` Q. Yes.
` A. -- the aerial density would roughly
`double.
` Q. Okay.
` A. These are once again approximate numbers.
` Q. Would double. And do you understand that
`this patent is talking about this next generation
`of .35? It says here this dimensional change is
`unallowable in the refinement of a semiconductor
`after the 0.5 micron generation.
` So do you understand that this background
`here is talking about the .35 node?
` A. Roughly speaking, yes, because as I
`mentioned once again, these transitions in
`technology were never precisely defined as a
`function of node or time, dependent on the company,
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`dependent on the precise product. So it all depends
`on the context.
` Q. Got it. But roughly .35 is the next
`node?
` A. Roughly .35 would be the next node, yes.
` Q. And as -- as you read the points -- I
`assume you've read the points, the '174 patent?
` A. Yes.
` Q. I'm sure. And were the descriptions in
`there consistent with a node size of .35?
` A. Well, the '174 is essentially a
`structure, set of structure claims. And they don't
`talk about precise dimensions, of course.
` Q. I know the claims don't. I wasn't
`talking about the claims.
` But the description of the patent, do you
`-- is that description consistent with the .35 node
`size?
` A. They don't -- even in the specifications,
`they don't have all the necessary dimensions, but
`with that caveat, I'd say -- given the description
`in the background, I'd say yes.
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` Q. So now I wanted to ask you -- I once
`drove by a fab, but I never went inside a fab. And
`I wanted to ask you to a layman, in a two- or
`three-minute description, what goes on inside a fab?
`We'll start there. Okay?
` A. Okay.
` Q. Could you please tell me?
` A. A fab is a shorthand for fabrication
`facility. These are done in what are called clean
`rooms where you have a room with what are called
`HEPA filters, high efficiency --
` Q. That I knew, okay.
` A. Okay. So you recirculate the air so that
`you can remove dust particles. The size and the
`number of dust particles is governed by what is
`called the class of the clean room. So, for
`example, a class 100 clean room, which would be kind
`of state of the art circa 1995, would have less than
`100 particles of size half micron or larger per
`cubic foot.
` Q. Hold on one second.
` A. Sure.
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` Q. I'm sorry. Go ahead. I interrupted you.
` A. Yeah, so the class of the clean room
`refers to the size of a certain size particles per
`unit volume. In this case, in those days, the
`standard was size half micron or larger. So class
`100 would mean less than 100 particles of size half
`micron or larger per cubic foot. You'd have more of
`smaller size particles, fewer of larger size
`particles.
` And the reason you need such a clean
`environment is because the dimensions of the devices
`that you make are so tiny that if you had these dust
`particles that you can't see with your naked eyes,
`fall down on your chips during fabrication, it would
`be like huge boulders falling down on structures --
` Q. I see.
` A. -- and the devices would be ruined. And
`then would you make these transistor structures.
` Q. That's what I want to focus on.
` A. Okay, all right.
` Q. So now the -- as you look at all of this
`prior art, and all of the art in this case, you can
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`see there's a great deal of layering that goes on to
`form these transistors. Is that correct?
` A. Yes.
` Q. And I wanted to ask you how are these
`layers applied? In other words, I assume that they
`are applied by very small things that squirt out
`stuff, but I'm curious about is there a computer
`that controls all of this? How does that work?
` MR. YOCHES: Objection.
` THE WITNESS: No, the layering typically
`is not squirted out, in general, on tiny parts of
`the semiconductor wafer. The layering, generally
`speaking, is done across the entire wafer by
`techniques known as chemical vapor deposition, would
`be one typical example, where you flow in gases, you
`react them in the gas phase. Typically, it goes not
`all the way to completion. You have intermediate
`products which diffuse what's known as the boundary
`layer to the surface of the wafer. And, typically,
`the surface of the wafer would catalyze the final
`stage of the reaction.
` Alternatively, you can have what's called
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`physical vapor deposition techniques, techniques
`such as sputter deposition where you create a plasma
`and you inject particles that are deposited on the
`surface of the wafer.
` So you layer the entire wafer, and then
`to get the aerial dimension localization, you spin
`on something called a photoresist, which is an
`organic chemical which responds to ultraviolet
`light. So what you then do is you shine this
`ultraviolet light on this photoresist that covers
`the semiconductor at different stages of the
`fabrication. And some of the stages would involve
`layering these materials as you mentioned, maybe
`polysilicon or dielectrics or metals depending on
`the stage of the process.
` So that layer would be covered by this
`photoresist. On top of that, you would place a mask
`which would have clear transparent regions and
`opaque regions corresponding to the circuit that
`you're trying to build. And through that you shine
`this ultraviolet light. That ultraviolet light
`shining through the transparent regions would cause
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`appropriate photochemical changes in the
`photoresist.
` The details depend on what kind of
`photoresist, positive or negative. Once you do the
`exposure, you then do what is called a development
`of the photoresist, which is you dunk it into a
`developer solution. In these -- circa 1995, for
`these processes, typically you would use something
`called a positive photoresist.
` And the
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