UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`
`
`Case IPR2016-01246†
`Patent 7,126,174 B2
`
`
`PETITIONER’S REPLY TO PATENT OWNER’S RESPONSE
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`† Case IPR2016-01247 has been consolidated with this proceeding.
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`

`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`
`Table of Contents
`
`
`I.
`
`INTRODUCTION ........................................................................................... 1
`
`II. ARGUMENT ................................................................................................... 2
`
`A.
`
`IPB has not shown why the obviating combinations TSMC
`proposed are legally or factually deficient. ........................................... 2
`
`1.
`
`2.
`
`IPB does not deny a POSITA would have known how to
`form STI without first forming a gate stack. .............................. 3
`
`TSMC’s Petitions provide ample evidence a POSITA
`would have found it obvious to integrate Noble’s and
`Ogawa’s STI structures into Lee’s and Lowrey’s devices. ......... 8
`
`B.
`
`IPB bases its arguments on incorrect legal propositions.....................25
`
`1.
`
`2.
`
`3.
`
`The law does not require TSMC to identify a process for
`substituting a preferred embodiment of Noble’s and
`Ogawa’s STI structures for Lee’s and Lowrey’s LOCOS
`isolation. ....................................................................................26
`
`The law does not require TSMC to demonstrate how to
`make the obviating structures by Noble’s and Ogawa’s
`fabrication processes to show obviousness. ..............................30
`
`The law does not require TSMC to substitute Noble’s and
`Ogawa’s preferred embodiments of STI for Lee’s and
`Lowrey’s LOCOS isolation in ways that also borrow
`Noble’s and Ogawa’s non-STI structures. ................................30
`
`C.
`
`D.
`
`IPB proposes an unreasonably low level of skill for a POSITA
`for the ’174 Patent. ..............................................................................33
`
`IPB misapplies the law in arguing that Noble and Ogawa “teach
`away” from obviating combinations. ..................................................35
`
`1.
`
`IPB identifies nothing in Noble and Ogawa to
`discourage a POSITA from using their STI teachings
`with Lee or Lowrey. ..................................................................36
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`It is irrelevant to patentability that Lee’s and Lowrey’s
`2.
`first-named inventors knew of STI in 1989 and 1990. .............37
`
`3.
`
`Ogawa’s etch-back method is not inherently deficient,
`but there would be no effect on patentability even if it
`were. ..........................................................................................38
`
`E.
`
`IPB’s remaining arguments fail to show the nonobviousness of
`substituting Noble’s and Ogawa’s STI structures for Lee’s and
`Lowrey’s LOCOS isolation. ................................................................39
`
`1.
`
`2.
`
`3.
`
`Contrary to IPB’s assertions, Lowrey discloses L-shaped
`sidewalls. ...................................................................................40
`
`Contrary to IPB’s assertions, Lee discloses silicide on
`source/drain regions ..................................................................42
`
`IPB has no basis for distinguishing between a “line” and
`a “layer” in Lee’s silicide regions. ............................................45
`
`4. Whether Noble or Ogawa disclose L-shaped sidewalls is
`irrelevant. ..................................................................................45
`
`5. Whether Ogawa or Noble use the same layer for the gate
`conductor and interconnection is irrelevant. .............................46
`
`6.
`
`7.
`
`8.
`
`9.
`
`Substituting STI for Lee’s LOCOS isolation does not
`eliminate Lee’s gate runner. ......................................................47
`
`Lee’s dielectric cap does not prevent contact between the
`gate electrode and interconnection. ..........................................48
`
`Noble discloses STI with an upper surface higher than a
`surface of the active area of the substrate. ................................49
`
`TSMC did not challenge claim 7 or 18 based on the
`Lowrey combinations, so IPB’s criticisms of such
`combinations are irrelevant. ......................................................50
`
`F.
`
`No claim terms require construction ...................................................50
`
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`III. CONCLUSION ..............................................................................................50
`
`IV. CERTIFICATION UNDER 37 C.F.R. §42.24(d) .........................................51
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`
`Table of Authorities
`
`Cases
`Amgen Inc. v. Hoechst Marion Roussel, Inc., 314 F.3d 1313 (Fed. Cir. 2003) ......45
`
`Baldwin Graphics Sys., Inc. v. Siebert, Inc., 512 F.3d 1338 (Fed. Cir 2008) .........30
`
`Custom Accessories, Inc. v. Jeffrey-Allan Indus., Inc., 807 F.2d 955 (Fed.
`Cir. 1986) .............................................................................................................. 6
`
`Dell Inc. v. Acceleron, LLC, 818 F.3d 1293 (Fed. Cir. 2016) .................................17
`
`EMI Grp. North Am., Inc. v. Cypress Semiconductor Corp., 268 F.3d 1342
`(Fed. Cir. 2001) ...................................................................................................41
`
`In re Gurley, 27 F.3d 551 (Fed. Cir. 1994) ..............................................................35
`
`In re ICON Health & Fitness, Inc., 496 F.3d 1374 (Fed. Cir. 2007) ........................ 6
`
`In re Kubin, 561 F.3d 1351 (Fed. Cir. 2009) ................................................ 8, 18, 26
`
`In re Mouttet, 686 F.3d 1322 (Fed. Cir. 2012) ........................................................31
`
`In re Thorpe, 777 F.2d 695 (Fed. Cir. 1985) .................................................... 18, 26
`
`In re Warsaw Orthopedic, Inc., 832 F.3d 1327 (Fed. Cir. 2016) ..................... 29, 35
`
`Innogenetics, N.V. v. Abbott Labs., 512 F.3d 1363 (Fed. Cir. 2008) ......................27
`
`Kinetic Concepts, Inc. v. Smith & Nephew, Inc., 688 F.3d 1342 (Fed. Cir.
`2012) ............................................................................................................ 27, 28
`
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007) .................................................. 6
`
`Personal Web Techs., LLC v. Apple, Inc., 848 F.3d 987 (Fed. Cir. 2017) ....... 27, 28
`
`Seachange Int’l, Inc. v. C-COR Inc., 413 F.3d 1361 (Fed. Cir. 2005) ....................43
`
`Standard Oil Co. v. Am. Cyanamid Co., 774 F.2d 448 (Fed. Cir. 1985).......... 37, 43
`
`Tyco Healthcare Grp. LP v. Ethicon Endo-Surgery, Inc., 774 F.3d 968 (Fed.
`Cir. 2014) .............................................................................................................. 6
`
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`Vanguard Prods. Corp. v. Parker Hannifin Corp., 234 F.3d 1370 (Fed. Cir.
`2000) ...................................................................................................................30
`
`Other Authorities
`MasterImage 3D, Inc. v. RealD Inc., IPR2015-00040, Paper 42 (PTAB July
`15, 2015) .............................................................................................................12
`
`Rules
`
`37 C.F.R. §42.23 ............................................................................................... 17, 18
`
`37 C.F.R. §42.24 ......................................................................................................51
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`
`LIST OF EXHIBITS
`
`Petition Exhibit 1001: U.S. Patent No. 7,126,174 to Segawa et al.
`
`Petition Exhibit 1002: U.S. Patent No. 5,153,145 to Lee et al.
`
`Petition Exhibit 1003: U.S. Patent No. 3,617,824 to Shinoda et al.
`
`Petition Exhibit 1004: Corrected Declaration of Dr. Sanjay Kumar Banerjee,
`Ph.D. in Support of Petition for Inter Partes Review of
`United States Patent No. 7,126,174 (IPR2016-01246).
`
`Petition Exhibit 1005:
`
`J.A. Appels et al., “Some Problems of MOS
`Technology,” Philips Tech. Rev. vol. 31 nos. 7-9, pp.
`225-36, 276 (1970).
`
`Petition Exhibit 1006: U.S. Patent No. 4,110,899 to Nagasawa et al.
`
`Petition Exhibit 1007: U.S. Patent No. 3,787,251 to Brand et al.
`
`Petition Exhibit 1008: B.B.M. Brandt et al., “LOCMOS, a New Technology for
`Complementary MOS Circuits,” Philips Tech. Rev. vol.
`34 no. 1, pp. 19-23 (1974).
`
`Petition Exhibit 1009: U.S. Patent No. 5,702,976 to Schuegraf et al.
`
`Petition Exhibit 1010: U.S. Patent No. 4,506,434 to Ogawa et al.
`
`Petition Exhibit 1011: U.S. Patent No. 4,957,590 to Douglas.
`
`Petition Exhibit 1012: U.S. Patent No. 5,976,939 to Thompson et al.
`
`Petition Exhibit 1013: U.S. Patent No. 6,165,826 to Chau et al.
`
`Petition Exhibit 1014: U.S. Patent No. 5,733,812 to Ueda et al.
`
`Petition Exhibit 1015: U.S. Patent No. 5,539,229 to Noble, Jr. et al.
`
`Petition Exhibit 1016: U.S. Patent No. 5,521,422 to Mandelman et al.
`
`Petition Exhibit 1017: U.S. Patent No. 5,021,353 to Lowrey et al.
`
`Petition Exhibit 1018: U.S. Patent No. 4,638,347 to Iyer.
`
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`Patent 7,126,174 B2
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`Petition Exhibit 1019:
`
`Japanese Patent Application No. 7-192181 to Segawa et
`al.
`
`Petition Exhibit 1020: Certified Translation of Japanese Patent Application No.
`7-192181 to Segawa et al.
`
`Petition Exhibit 1021: File History of U.S. Patent No. 7,126,174 to Segawa et
`al.
`
`Petition Exhibit 1022: File History of Japanese Patent Application No.
`7-330112 to Segawa et al.
`
`Petition Exhibit 1023: Certified Translation of Portions of the File History of
`Japanese Patent Application No. 7-330112 to Segawa et
`al.
`
`Petition Exhibit 1024: Corrected Declaration of Dr. Sanjay Kumar Banerjee,
`Ph.D. in Support of Petition for Inter Partes Review of
`United States Patent No. 7,126,174 (IPR2016-01247).
`
`Petition Exhibit 1025: E. Adler et al., “The Evolution of IBM CMOS DRAM
`Technology,” IBM J. Res. Develp., vol. 39, no. 1/2, pp.
`167-88 (Jan/Mar. 1995).
`
`Petition Exhibit 1026:
`
`Japanese Patent Application No. H03-379033 to Sumi et
`al.
`
`Petition Exhibit 1027: Certified Translation of Japanese Patent Application No.
`H03-379033 to Sumi et al.
`
`Petition Exhibit 1028:
`
`Japanese Patent Application No. S59-181062 to
`Horiguchi.
`
`Petition Exhibit 1029: Certified Translation of Japanese Patent Application No.
`S59-181062 to Horiguchi.
`
`Petition Exhibit 1030:
`
`Japanese Patent Application No. H07-183518 to Ueda et
`al.
`
`Petition Exhibit 1031: Certified Translation of Japanese Patent Application No.
`H07-183518 to Ueda et al.
`
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`Petition Exhibit 1032: U.S. Patent No. 4,651,411 to Konaka et al.
`
`Petition Exhibit 1033:
`
`Japanese Patent Application No. S58-73163 to Konaka et
`al.
`
`Petition Exhibit 1034: U.S. Patent No. 6,218,266 to Sato et al.
`
`Petition Exhibit 1035: U.S. Patent No. 5,445,996 to Kodera et al.
`
`Petition Exhibit 1036: U.S. Patent No. 4,511,430 to Chen et al.
`
`Petition Exhibit 1037: U.S. Patent No. 4,599,789 to Gasner.
`
`Petition Exhibit 1038: U.S. Patent No. 4,855,247 to Ma et al.
`
`Petition Exhibit 1039: U.S. Patent No. 5,102,816 to Manukonda et al.
`
`Petition Exhibit 1040: U.S. Patent No. 5,512,771 to Hiroki et al.
`
`Petition Exhibit 1041: U.S. Patent No. 5,648,284 to Kusunoki et al.
`
`Petition Exhibit 1042: S. Deleonibus et al., “Optimization of a Shallow Trench
`Isolation Refill Process for High Density Non Volatile
`Memories Using 100% Chemical-Mechanical Polishing:
`The BOX-ON Process,” Extended Abstracts of the
`Spring 1994 Electrochem. Soc. Meeting, abstract no.
`171, vol. 94-1, pp. 267-77 (May 22-27, 1994).
`
`Petition Exhibit 1043:
`
`J.M. Pierce et al., “Oxide-Filled Trench Isolation
`Planarized Using Chemical/Mechanical Polishing,”
`Proceedings of the Third International Symposium on
`Ultra Large Scale Integration Science and Technology,
`vol. 91-11, pp. 650-56 (1991).
`
`Petition Exhibit 1044: Excerpts from C.Y. Chang & S.M. Sze, “ULSI
`Technology” (1996).
`
`Petition Exhibit 1045: Excerpts from S. Wolf, “Silicon Processing for the VLSI
`Era: Volume 1: Process Technology” (1986).
`
`Petition Exhibit 1046: Excerpts from S. Wolf, “Silicon Processing for the VLSI
`Era: Volume 2: Process Integration” (1990).
`
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`Petition Exhibit 1047: H.W. Fry et al., “Applications of APCVD TEOS/O3
`Thin Films in ULSI IC Fabrication,” Solid State Tech.,
`pp. 31-40 (Mar. 1994).
`
`Petition Exhibit 1048: S. Poon & C. Lage, “A Trench Isolation Process for
`BiCMOS Circuits,” Proceedings of the 1993 IEEE
`Bipolar Circuits & Tech. Meeting 3.3, pp. 45-48 (Oct. 4-
`5, 1993).
`
`Petition Exhibit 1049: L. Clement et al., “Microscopy Needs for Next
`Generation Devices Characterization in the
`Semiconductor Industry,” J. Physics: Conference Series,
`vol. 326, conf. 1, 17th International Conference on
`Microscopy of Semiconducting Materials, pp. 1-14 (Apr.
`4-7, 2011).
`
`Petition Exhibit 1050: R. Pantel et al., “Physical and Chemical Analysis of
`Advanced Interconnections Using Energy Filtered
`Transmission Electron Microscopy,” Microelectronic
`Engineering, vol. 50, nos. 1-4, pp. 277-84 (Jan. 2000).
`
`Petition Exhibit 1051: G. Servanton & R. Pantel, “Arsenic Dopant Mapping in
`State-of-the -Art Semiconductor Devices Using Electron
`Energy-Loss Spectroscopy,” Micron, vol. 41, no. 2, pp.
`118-22 (Feb. 2010).
`
`Petition Exhibit 1052: K. Kurosawa et al., “A New Bird’s-Beak Free Field
`Isolation Technology for VLSI Devices,” Proceedings of
`the 1981 International Electron Devices Meeting, pp.
`384-87 (Dec. 7-9, 1981).
`
`Petition Exhibit 1053: H.K. Kang et al., “Highly Manufacturable Process
`Technology for Reliable 256 Mbit and 1 Gbit DRAMs,”
`Proceedings of the 1994 International Electron Devices
`Meeting, pp. 635-38 (Dec. 11-14, 1994).
`
`Petition Exhibit 1054: Semiconductor Industry Association, “The National
`Technology Roadmap for Semiconductors” (1994).
`
`Petition Exhibit 1055: B. Davarik et al., “A New Planarization Technique,
`Using a Combination of RIE and Chemical Mechanical
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`Polish (CMP),” Proceedings of the 1989 International
`Electron Devices Meeting, pp. 61-64 (Dec. 3-6, 1989).
`
`Petition Exhibit 1056: Deposition Transcript of E. Fred Schubert, Ph.D. dated
`May 25, 2017.
`
`Petition Exhibit 1057: Declaration of Dr. Sanjay Kumar Banerjee, Ph.D. in
`Support of Petitioner’s Reply in Inter Partes Review
`Nos. IPR2016-01246, -01247.
`
`Petition Exhibit 1058: U.S. Patent No. 5,173,439 to Dash et al.
`
`Petition Exhibit 1059: Errata Sheet (dated June 6, 2017) from the Deposition of
`E. Fred Schubert, Ph.D.
`
`
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
`
`I.
`
`INTRODUCTION
`
`In its Petitions, TSMC explained how Lee and Lowrey teach every limitation
`
`of the challenged claims, and why a POSITA would have wanted to substitute
`
`Noble’s and Ogawa’s functionally equivalent shallow-trench isolation (“STI”)
`
`structures for Lee’s and Lowrey’s LOCOS isolation. One reason was such
`
`substitutions allow increased device density. TSMC even showed several
`
`examples how a POSITA would have known to make the STI structures in Noble
`
`and Ogawa.
`
`IPB does not challenge this evidence. Instead, it advances two oblique
`
`arguments. One is to attack combinations TSMC never proposed, which are
`
`irrelevant. The other is to contort the law to suggest TSMC must show
`
`obviousness by inserting non-STI structures from Noble and Ogawa into Lee’s and
`
`Lowrey’s preferred embodiments using only the processes Noble and Ogawa
`
`describe. IPB does so to argue that the result of this contrived combination is
`
`unfeasible, but no law supports its approach.
`
`The only issue the Board thought worthy of consideration was whether a
`
`POSITA would have been motivated and reasonably able to modify the structures
`
`Lee and Lowrey teach by replacing their LOCOS isolation with Noble’s and
`
`Ogawa’s STI. IPB never challenges TSMC’s evidence that the combinations it
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`proposes renders the claims at issue obvious, so the Board should continue to reject
`
`IPB’s flawed analysis and cancel the challenged claims.
`
`II. ARGUMENT
`
`A.
`
`IPB has not shown why the obviating combinations TSMC
`proposed are legally or factually deficient.
`
`The Board observed that TSMC “provide[d] reasons why a [POSITA] would
`
`have been motivated to replace Lee’s LOCOS with Noble’s STI, and, importantly,
`
`evidence that [a POSITA] viewed the two methods as substitutes, with STI having
`
`certain known advantages over LOCOS (such as eliminating the bird’s beak).”
`
`Paper 8, at 17; see also id., 22, 26-28. The evidence supporting this conclusion is
`
`overwhelming, and IPB does not attack it. See EX1057, ¶¶49-78; Paper 2, at 21,
`
`70; Paper 2 (IPR2016-01247, at 21, 62; Paper 8, at 17, 22, 26-28; EX1009, 2:20-
`
`22; EX1010, 1:24-66; EX1011, 4:10-16; EX1012, 3:8-10; EX1014, 22:49-52;
`
`EX1034, 1:60-64; EX1046, 557; EX1053, 636; Paper 14, at 8, 69. Even IPB’s
`
`declarant agrees with the premises underlying the combinations of references.
`
`EX1056, 78:9-17 (“[B]oth structures are isolation structures.”), 76:8-9 (“[Y]es,
`
`there is a concern that LOCOS uses up too much real estate.”), 76:11-78:2
`
`(“Trench isolation was considered at that time, and was one of the candidates [for
`
`replacing LOCOS].”).
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`Although IPB argues “it is not possible to simply start with Noble’s or
`
`Ogawa’s STI without first forming the gate dielectric and gate conductor,” the
`
`record is replete with contrary evidence.
`
`1.
`
`IPB does not deny a POSITA would have known how to
`form STI without first forming a gate stack.
`
`Forming STI has always involved etching a trench in the substrate, filling it
`
`with an insulator, and removing unwanted portions of the insulator outside the STI
`
`regions by polishing and/or etching. Paper 14, at 10; EX1010, 6:16-59, 7:38-42;
`
`EX1015, 4:40-52, 5:49-57; EX1057, ¶50; EX1025, 175.
`
`IPB does not deny a POSITA would have known to use chemical-
`
`mechanical polishing (“CMP”), etch-back, or a combination of both to remove
`
`unwanted portions of the insulator. EX1057, ¶¶58-61, 68. Doing so requires a
`
`polish/etch-stop layer to slow the polishing or etching at the endpoint of the
`
`removal process. EX1057, ¶¶58-63, 68-74. One known technique was to use the
`
`substrate as a polish/etch-stop. EX1057, ¶¶68-78; EX1014, 13:14-47; EX1031,
`
`¶¶64-69; EX1010, 2:4-20; EX1029, 6-7; EX1027, 5-7; EX1032, 3:57-4:13;
`
`EX1058, 2:48-4:46. Making raised trenches with this technique may involve
`
`selectively etching the substrate regions surrounding the STI (EX1014, 13:25-26,
`
`Figs. 12(b), 12(c) (below)), or masking the trench regions and performing an
`
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`Patent 7,126,174 B2
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`anisotropic etch (EX1027, 5, Figs. 1B, 1C below). Id. The resulting substrate
`
`contains a raised trench isolation ready for device fabrication. Id.
`
`
`
`
`
` EX1014 (substrate etching) EX1027 (trench masking/etching)
`
`Another well-known way to remove unwanted insulator portions was to use
`
`a dedicated polish/etch-stop layer of Si3N4, polysilicon, or other material. EX1057,
`
`¶¶58-67; EX1016, 3:55-4:22, 5:40-47; EX1015, 4:40-52, 5:49-57; EX1010, 5:57-
`
`6:59, 7:40-42; EX1001, 4:16-5:20 (admitted prior art); EX1034, 4:58-6:44, 7:46-
`
`8:33; EX1035, 26:59-28:33; EX1042, 267-68 & Fig. 1; EX1043, 651-52; EX1032,
`
`3:57-4:13; EX1055, 61-62; EX1058, 2:48-4:46. One optional way to protect the
`
`substrate from damage during removal of the polish/etch-stop layer is to use a pad
`
`oxide between the substrate and stopper layer. Id. Trenches are etched using the
`
`polish/etch-stop, pad oxide, and substrate, and filled with an insulator (usually
`
`SiO2). Id. The insulator is removed stopping at the polish/etch-stop layer. Id.; see
`
`also EX1016, 3:61-63, FIG. 1d (below); EX1034, 5:36-43, Figs. 1C, 1D (below).
`
`The polish/etch-stop and pad oxide are selectively removed to leave a substrate
`
`with raised trench isolation ready for device fabrication. Id.; see also EX1016,
`
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`3:63-65, FIG. 1d′ (below); EX1034, 5:44-49, Fig. 1D′ (below).1 Sometimes, as in
`
`certain embodiments of Noble and Ogawa, a polysilicon polish/etch-stop may
`
`remain as a gate conductor, and the pad oxide may remain as a gate oxide, but
`
`most processes remove the polish/etch-stop and pad oxide after planarization
`
`(below). Id.
`
`
`
`
`
` EX1016 EX1034
`
`Regardless of the technique to remove portions of the trench insulator, a
`
`POSITA also would have known how to add a trench liner or to place a channel-
`
`stop implant in the trench before filling. EX1057, ¶¶50, 58, 68; see also EX1001
`
`at 4:28-30, FIG. 20(a) (admitted prior art); EX1029, 7, Fig. 3(b); EX1032, 3:62-63,
`
`FIG. 7A; EX1043, 651; EX1009, 5:9-24.
`
`1 FIG. 1d′ is a modified version of Mandelman’s FIG. 1d that Mandelman
`
`describes (EX1016, 3:61-65), and Fig. 1D′ is a modified version of Sato’s Fig. 1D
`
`that Sato describes (EX1034, 5:36-49).
`
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`IPR2016-01246, IPR2016-01247
`Patent 7,126,174 B2
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`When IPB suggests a POSITA would not have thought to remove the
`
`polish/etch-stop layer, or would have been discouraged from doing so because of
`
`the teachings of Noble and Ogawa, it ignores the requirement that a POSITA have
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`knowledge of all relevant art. Custom Accessories, Inc. v. Jeffrey-Allan Indus.,
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`Inc., 807 F.2d 955, 962 (Fed. Cir. 1986). It also ignored the requirement that “[a]
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`person of ordinary skill is also a person of ordinary creativity, not an automaton.”
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`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 420-21 (2007). A POSITA “knows
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`how to combine familiar prior art elements to achieve the same functions,” Tyco
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`Healthcare Grp. LP v. Ethicon Endo-Surgery, Inc., 774 F.3d 968, 978 (Fed. Cir.
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`2014). One cannot “ignore the modifications [a POSITA] would make to a device
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`borrowed from the prior art,” In re ICON Health & Fitness, Inc., 496 F.3d 1374,
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`1382 (Fed. Cir. 2007).
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`Even the Noble and Ogawa embodiments IPB addresses use these well-
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`known processes for forming raised STI. A pad oxide layer and a polish/etch-stop
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`layer are formed on a substrate. EX1010, 5:57-6:9, 6:47-49; EX1015, 3:64-4:5,
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`5:55-57. Then a trench is etched through these layers and into the substrate to
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`define the STI regions. EX1010, 6:16-22; EX1015, 4:40-45. Those regions are
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`filled with a deposited insulator (EX1010, 6:25-30; EX1015, 4:45-48), and the
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`insulator is planarized, stopping on the polish/etch-stop layer. EX1010, 6:42-59;
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`Patent 7,126,174 B2
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`EX1015, 5:55-57. This results in the following STI structures, which, like any STI
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`structure, have a substrate trench filled with an insulator.
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` EX1016 (Noble), FIG. 9 EX1010 (Ogawa), Fig. 4(c)
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`
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`A polish/etch-stop layer chosen in Noble and Ogawa is polysilicon, which
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`remains as the gate conductor (layer 116 in Noble and layer 43 in Ogawa), and the
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`pad oxide remains as the gate dielectric (layer 14 in Noble and layer 42 in Ogawa).
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`Because the polish/etch-stop and pad oxide perform double-duty as part of the gate
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`stack in this example, the gate dielectric and gate conductor are formed before the
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`STI. But again, doing so was known to be optional. EX1057, ¶¶58, 64-66, 79, 81,
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`90.
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`When IPB alleges that formation of the gate electrode and gate conductor
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`must always precede formation of the STI (Paper 14, at 64, 115), it ignores the
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`most straightforward way of substituting for LOCOS isolation. That is to form
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`raised STI before the gate layers, as Lee and Lowrey do for LOCOS isolation.
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`EX1057, ¶¶79-81, 90. A POSITA would have had a reasonable expectation of
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`success (see EX1057, ¶¶79-143), as TSMC’s Petitions demonstrated.
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`Patent 7,126,174 B2
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`TSMC’s Petitions provide ample evidence a POSITA would
`2.
`have found it obvious to integrate Noble’s and Ogawa’s STI
`structures into Lee’s and Lowrey’s devices.
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`The Board recognized that proof of a reasonable expectation of success
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`could come from sources other than the references in an obviousness combination.
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`Paper 8, at 13 n.5. The evidence TSMC provided shows a POSITA would have
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`appreciated “the well-known and reliable nature” of several standard STI
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`techniques compatible with Lee and Lowrey. In re Kubin, 561 F.3d 1351, 1360
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`(Fed. Cir. 2009).
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`a.
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`TSMC supplied unrebutted evidence of well-known
`ways a POSITA knew to make raised STI without
`first forming gate layers.
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`The Board acknowledged at institution that TSMC’s Petitions provide
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`“reasons why a person of ordinary skill in the art would have been motivated to
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`replace Lee’s LOCOS with Noble’s STI, and, importantly, evidence that persons of
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`ordinary skill in the art viewed the two methods as substitutes, with STI having
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`certain known advantages over LOCOS (such as eliminating the bird’s beak).”
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`Paper 8, at 17 (emphasis in original). Numerous references discuss the
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`interchangeability of LOCOS isolation and STI without explaining the details of
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`substitution, demonstrating substituting one for the other was well within the range
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`of ordinary skill. EX1057, ¶57; EX1009, 2:20-22; EX1011, 4:8-16; EX1012, 3:3-
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`Patent 7,126,174 B2
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`10; EX1014, 22:49-52; EX1053, 636; EX1047, 36-37; EX1025, 171-73, 175, Fig.
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`6, Tbl. 2; EX1054, 45-47 & Tbl. 6.
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`TSMC’s Petitions also identified references that disclose how to make STI
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`before the gate layers. Paper 2, at 25; Paper 2 (IPR2016-01247), at 25; see also
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`Paper 2, at 5-7, 22-26; Paper 2 (IPR2016-01247), at 5-7, 22-26; EX1004, ¶¶87-90;
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`EX1024, ¶¶85-88. One reference, Ueda, illustrates a process in which a trench is
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`first dry-etched and filled with a high-temperature oxide (EX1014, Fig. 12(a)
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`below). The oxide is then planarized by CMP (EX1014, Fig. 12(b) below), and the
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`substrate is dry-etched to complete the raised STI structure (EX1014, Fig. 12(c)
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`below). The gate is formed after the STI is formed. (EX1014, Figs. 12(d), 12(e)
`
`below). EX1014 at 13:20-39; see also EX1031, ¶¶0065-0068.2 IPB never
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`addressed this teaching.
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`2 The ’174 patent contemplates the same process. EX1001 at 12:43-52,
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`
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`FIGS. 1(a)-1(d).
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`Patent 7,126,174 B2
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`The Petitions also discussed Mandelman, which describes a process that
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`forms a pad oxide and a nitride over the substrate (EX1016, FIG. 1a below), and
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`etches them to form a window (EX1016, FIG. 1b below) defining a trench pattern
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`etched using the nitride as a mask (EX1016, FIG. 1c below). The trench is filled
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`with an insulator, which is polished, stopping at the nitride layer (EX1016, FIG. 1d
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`below). Removing the nitride leaves a raised STI structure (FIGS. 1d′,3 1e below).
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`EX1016, 3:55-4:22. IPB never challenges this evidence either.
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`TSMC’s Petitions also discussed the admitted prior art of the ’174 patent
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`that describes the process Mandelman discloses. EX1001, 26:40-45, 22:15-58,
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`FIGS. 13(a)-13(c) (below); Paper 2, at 22-23; Paper 2 (IPR-01247), at 22-23. The
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`3 See supra note 2.
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`Patent 7,126,174 B2
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`’174 patent uses this prior art to make the structures in its preferred embodiment.
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`EX1001, 4:16-41, FIGS. 20(a)-20(c) (below).4
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`
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`IPB and its declarant never addressed these aspects of Ueda, Mandelman, or the
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`admitted prior art, despite TSMC’s use of those references to explain its
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`obviousness arguments. See Paper 2, at 5-6, 21-30, 70-76; Paper 1 (IPR2016-
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`01247), at 5-6, 21-30, 62-68; EX1056, 134:15-135:11, 143:17-144:5.
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`Other record evidence and material art from the prosecution history also
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`show a POSITA would have known how to form raised STI structures without
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`using the gate. For example, Noble incorporates Dash by reference. EX1015,
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`3:35-37. And Sumi and Horiguchi appear on the face of the ’174 patent and were
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`cited in an IDS to the Patent Office. EX1021 at 96; EX1001 at [56] (listing “JP
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`4 The only difference between FIGS. 13 and 20 is the thickness of the nitride
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`layer and therefore the height of the trench. EX1057, ¶63.
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`59181062 A 10/1984” and “JP 03079033 A 4/1991”). See MasterImage 3D, Inc.
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`v. RealD Inc., IPR2015-00040, Paper 42, at 2 (PTAB July 15, 2015) (explaining
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`that material art in the prosecution history is “of record” in the proceeding)).
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`Dash describes a process beginning with silicon semiconductor substrate 10
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`coated with silicon nitride etch-stop 12. (EX1058, Fig. 1 below). Trenches are
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`then formed in the silicon nitride etch-stop and the substrate using conventional
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`processes (EX1058, Fig. 2 below). The trenches are over-filled with SiO2, which
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`extends from the trench over the Si3N4 etch-stop (EX1058, Fig. 3). Making wide
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`trenches requires depositing polysilicon over the SiO2 and polishing it to remove
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`polysilicon outside the wide trench area (EX1058, Figs. 3, 4).5 After an
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`anisotropic etch, CMP planarizes the SiO2 up to the silicon nitride etch-stop
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`(EX1058, Figs. 5, 6). The gate and device are then formed, which a POSITA
`
`would know requires removing the silicon nitride etch-stop layer. EX1058, at
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`Abstract, 2:48-4:46;6 EX1034, 5:44-45.
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`5 This is unnecessary for trenches less than about 1,000 nm (EX1058, 1:35-
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`38), which were common by December 1995 (EX1009, 4:23-28; EX1042, Figure
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`2; EX1047, Figure 10).
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`6 This is the process Mandelman and the admitted prior art disclose.
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`EX1001, 4:16-41; EX1016, 3:55-4:22.
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`The ’174 patent describes etch-back as an alternative to CMP. EX1001 at
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`12:43-52, 22:34-49, 25:12-25. Similar to Ogawa, Horiguchi and Sumi describe
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`processes for forming a raised STI using etch-back planarization. In Horiguchi, a
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`trench is defined by photoresist and dry etched into the substrate (EX1028, Figs.
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`3(a), 3(b) below). A channel stop is formed in the trenches, the photoresist is
`
`removed, and a SiO2 film is deposited to fill the trenches (EX1028, Fig. 3(c)
`
`below). A new layer of photoresist is deposited and patterned to fill recessed areas
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`over the trenches (EX1028, Fig. 3(d) below). Another photoresist layer is
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`deposited over the entire wafer to form a planar surface (EX1028, Fig. 3(e) below),
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`and a non-selective etch removes the photoresist and SiO2 at approximately equal
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`rates, stopping on the silicon surface to leave a planar structure (EX1028, Fig. 3(f)
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`below). This process is called “etch-back.” Once etch-back is complete, the
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`Patent 7,126,174 B2
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`silicon surface is etched to form raised STI (EX1028, Fig. 3(g) below). The gate
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`stack (EX1028, Figs. 3(h)-3(i) below) and device (EX1028, Figs. 3(j)-3(n) below)
`
`are then formed. EX1029, at 6-7.7
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`
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`Sumi describes another process for forming a raised STI structure before the
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`gate layers. After etching trenches into the substrate (EX1027, Fig. 1A below), an
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`SiO2 layer is deposited to fill the trenches, and a photoresist pattern is formed over
`
`the trenches (EX1027, Fig. 1B below). Using the photoresist pattern as a mask, the
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`exposed areas of the SiO2 film are dry etched, stopping on the substrate surface,
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`7 The ’174 patent describes this same well-know