`
`
`
`
`United States Patent
`Dash et al.
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`
`
`Illlll||||l||ll|l||||ll||l||||l|lllllllllllllllllllllllllllllllllllllllllll
`U8005173439A
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`[19]
`[11] Patent Number:
`
`[45] Date of Patent:
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`
`
`
`5,173,439
`
`
`Dec. 22, 1992
`
`
`
`
`
`[54] ‘ FORMING WIDE DIELECTRIC-FILLED
`
`
`
`ISOLATION TRENCHES IN
`
`
`SEMICONDUCTORS
`
`
`Inventors:
`
`[75]
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`
`
`
`
`
`
`Somanath Dash; Michael L.
`
`
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`Kerbaugh, both of Burlington;
`
`
`
`Charles W. Koburger, III, Essex;
`
`
`
`
`Brian J. Maehesney, Burlington, all
`
`
`
`
`of Vt.; Nitin B. Parekh, Austin, Tex.
`
`
`
`
`
`International Business Machines
`
`
`
`Corporation, Amonk, NY.
`
`
`[21] App1.No.: 679,568
`
`
`
`
`[22] Filed:
`Apr. 2, 1991
`
`
`
`
`[73] Assignee:
`
`
`
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`
`
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`.
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`
`
`0341898 11/1989 European Pat. Off.
`2599892 12/1987 France 4
`
`
`
`
`
`
`
`1/1984 Japan ,
`59-13342
`
`
`
`59475138 10/1984 Japan ..
`
`
`
`59-17794] 10/1984 Japan 1
`
`
`
`59193044 11/1984 Japan .
`
`
`
`
`60-236244 11/1985 Japan .
`
`
`
`7/1989 Japan.
`59-117233
`
`
`
`' OTHER PUBLICATIONS
`
`
`
`IBM Technical Disclosure Bull, vol. 30, No. 2 (Jul.
`
`
`
`
`
`
`
`1987) pp. 539—540.
`
`
`
`Primary Examiner—G. Fourson
`
`
`
`Attorney. Agent, or Firm—Calfee, Halter & Griswold
`
`
`
`
`
`ABSTRACI‘
`[57]
`
`
`A method of forming a planarized dielectric filled wide
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`shallow trench in a semi-conductor substrate is pro—
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`vided. A layer of etch stop such as Si3N4 is deposited
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`onto the semi-conductor substrate, and wide trenches
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`are formed through the Si3N4 into the substrate by con-
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`ventional RIE. The surface of the substrate including
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`the trenches have formed thereon a SiOz coating, con-
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`forming to the surface of the substrate. A layer of etch
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`resistant material such as polysilicon is deposited onto
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`the SiOz material. The polysilicon outside the width of
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`the trenches is then removed by chemical-mechanical
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`polishing to expose the 5102 there below, while leaving
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`the SD; above the trenches covered with polysilicon.
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`The exposed $02 is then RIE etched down to the
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`Si3N4,
`leaving a plug of SiOz capped with the etch
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`resistant polysilicon over each trench. These plugs are
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`then removed by mechanical polishing down to the
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`Si3N4, to provide a planarized upper surface of $102 and
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`Si3N4 on the top of the substrate. The invention also is
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`useful in forming planarized surfaces on substrates hav-
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`ing trenches filled with conductive material.
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`14 Claims, 1 Drawing Sheet
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`.\\\\\\\‘
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` 2
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`Related US. Application Data
`
`
`
`Continuation of Ser. No, 427,153, Oct. 25, 1989, aban-
`doned.
`
`
`
`
`
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`
`
`H01L 21/76
`Int. Cl.5
`[51]
`437/67; 437/203;
`[52] U.S. Cl.
`
`437/228
`
`
`
`
`
`
`[58] Field of Search ..................... .. 437/62, 67, 69, 70,
`
`437/72, 225, 228, 203; l48/DIG. 50, DIG, 85,
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`DIG. 86
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`
`
`References Cited
`
`
`U.S. PATENT DOCUMENTS
`
`
`
`7/1981
`Imaizumi ..
`357/48
`4,278,987
`
`
`
`
`3/1983 Wang
`156/643
`4,376,672
`
`5/1983 Chu ......
`204/192 E
`4,385,975
`
`
`
`7/1985 Silvestri
`148/175
`4,526,631
`
`
`4,671.851‘ 6/1987 Beyer
`156/645
`
`
`
`
`
`6/1987 Keiser
`.427/93
`4,671,970
`
`
`
`
`
`6/1989 Breiten.
`156/643
`4.336.885
`
`
`
`
`
`4,962,069 10/1990 Haskell e
`....... 437/223
`
`
`
`
`
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`
`
`1/1989 European Pat. Off.
`.
`0300569
`
`
`
`
`2
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`[63]
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`[56]
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`18
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`1 1
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`0
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`1B
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`12
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`‘10
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`Page 1 of 6
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`TSMC Exhibit 1058
`
`TSMC v. IP Bridge
`IPR2016-01246
`
`Page 1 of 6
`
`TSMC Exhibit 1058
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

`US. Patent
`
`Dec. 22, 1992
`
`5,173,439
`
`12
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`1O
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`'I.".""£l
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`2
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`.
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`L__—+Fae ——____J
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`L____ ________J
`Fig.5
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`12
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`1O
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`1 2
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`1 0
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`1 2
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`1 2
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`1—__.__m ____—_J
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`18
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`18
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`x\\\\\\V77 \\\\\\\\\
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`1 2
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`1 B
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`_
`1 8
`.\\\\\\\\V.\\\\\\\\‘
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`12
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`Page 2 of 6
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`

`

`1
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`
`FORMING WIDE DIELECTRIC-FILLED
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`
`ISOLATION TRENCHES IN SEMICONDUCTORS
`
`
`
`5,173,439
`
`
`2
`
`rial, but with a semi-conductor material having a differ-
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`ent characteristic than the base substrate material. This
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`also uses a masking process.
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`U.S. application Ser. No. 189,863, filed May 3, 1988,
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`owned by the assignee of this invention, discloses an-
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`other technique for planarizing wide dielectric filled
`isolation trenches.
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`One of the principal objects of this invention is to
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`provide an improved method of forming dielectric
`filled wide trenches in a semi-conductor substrate
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`which is self-aligning and has resultant good planariza—
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`ti0n.
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`5
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`10
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`well-known practice in the art. Other processes, also
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`This is a continuation of copending application Ser.
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`No. 07/427,153 filed on Oct. 25, 1989, now abandoned.
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`BACKGROUND OF THE INVENTION
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`This invention relates generally to the manufacture of
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`semi-conductor devices. More particularly, the inven-
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`tion relates to a method of forming planarized wide'
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`filled trenches in the surface of a semi-conductor sub-
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`strate, especially a silicon wafer, particularly filled with
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`dielectric material, although the invention also can be
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`used to form trenches filled with conductive material.
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`In the art of large-scale integrated chips, a large num—
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`ber of surface conductors are required for distribution
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`of operating voltages and currents and digital signals
`between devices. Although surface conductors are insu-
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`lated from the semi-conductor substrate upon which
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`they are formed, a certain amount of capacitive cou—
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`pling is present between the insulated conductor and the
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`substrate through the insulating material. This capaci-
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`tive coupling degrades the signal carried by the surface
`conductors.
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`While this capacitive coupling can be minimized by
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`increasing the thickness of the dielectric material sepa-
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`rating the conductors and the substrate, it is more desir-
`able to recess the dielectric material below the surface
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`of the substrate and maintain the planarity of the sub-
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`strate rather than add the dielectric material onto the
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`surface of the substrate. This is accomplished by form-
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`ing shallow trenches in the surface of the substrate, and
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`filling the trenches with dielectric material, normally
`silicon dioxide. These trenches may be either narrow
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`trenches (i.e., less than about one micron in width, and
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`more typically about 0.5 microns) and wide trenches
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`(i.e., those wider than about one micron).
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`is relatively simple to maintain planarity when
`It
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`forming dielectric filled narrow trenches. However,
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`problems of maintaining planarity with the semi-con-
`ductor substrate and the dielectric material are pres-
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`ented with wide trenches because of the conformal
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`nature of the deposition of the dielectric and especially
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`silicon dioxide in the wide trenches.
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`There have been several prior art proposals for solv-
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`ing these problems of forming planarized dielectric
`filled wide trenches. One such proposal, described in
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`U.S. Pat. No. 4,385,975 assigned to the assignee of this
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`invention, utilizes a step in the process of depositing a
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`photoresist material through a mask over the dielectric
`material contained in the trenches before planarization.
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`The dielectric material is then reactive ion etched (RIB)
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`with the photoresist masking the underlying material
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`from etching, thus resulting in a relatively planer struc-
`ture. U.S. Pat. No. 4,671,970 also utilizes a photoresist
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`as a mask for reactive ion etching of dielectric material.
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`These teachings of masking, while somewhat effective,
`nevertheless have certain drawbacks. They require
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`extra masking and photolithographic steps, which adds
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`two processing steps, and more importantly create sig-
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`nificant problems of alignment; i.e., the mask must be
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`perfectly aligned to deposit V the photoresist exactly
`within the conformal or trough portion of the deposited
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`dielectric material to be utilized to mask just that dielec~
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`tric material desired and to expose the rest.
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`U.S. Pat. No. 4,278,987 shows a somewhat different
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`technique for filling trenches, not with dielectric mate-
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`15
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`SUMMARY OF THE INVENTION
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`A method or process for forming a wide, shallow
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`filled trench on the surface of a semi-conductor sub-
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`strate is provided, and in particular a dielectric filled
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`trench. The process includes forming a wide, shallow
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`trench in the surface of the semi-conductor substrate
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`followed by conformally depositing a layer of dielectric
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`material on the surface of the substrates including in the
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`trench. A layer of etch-resistant material is deposited on
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`the layer of the dielectric material. Portions of the etch
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`resistant material outside the width of the trench are
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`selectively removed, preferably by chemical-mechani-
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`cal polishing, such that the remaining portions of the
`etch resistant material reside within the width of the
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`trench. Following this, a dielectric plug is formed above
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`the trench by etching the layer of dielectric material
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`which is not covered by the etch resistant material
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`down to the top of the trench. Finally, the dielectric
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`plug is removed, preferably by polishing, to obtain a
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`dielectric filled trench, having an upper surface in sub-
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`stantial planarity with the upper surface of the substrate.
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`This invention also can be used to fill and planarize
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`trenches with conductive material.
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`DESCRIPTION OF THE DRAWINGS
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`FIGS. 1 through 6 are cross—sectional views, some-
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`what diagrammatic, showing successive stages of pro-
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`cessing of a semi-conductor having wide and narrow
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`shallow trenches formed, filled with dielectric material
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`and planarized according to this invention.
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`DESCRIPTION OF THE PREFERRED
`
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`EMBODIMENTS
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`Referring now to the drawings, and for the present,
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`FIG. 1, there is shown a silicon semi-conductor sub-
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`strate 10 having an etch stop coating of silicon nitride
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`(Si3N4) 12 deposited thereon. The silicon nitride is typi-
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`cally about 1000 A thick and can be deposited by con-
`ventional means such as by chemical vapor deposition
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`(CVD) from SiH2C12+NH3 at 400 mTorr, at 770° C.
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`The silicon nitride is then patterned by conventional
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`photoresist techniques to reveal underlying openings
`where both wide and narrow trenches are to be formed.
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`Two such trenches 14 and 16 are shown in FIG. 2
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`formed in substrate 10 although it is to be understood
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`that normally many such trenches are formed. The
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`trench 14 is a wide trench, typically wider than about
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`one micron, and the trench 16 is a narrow trench, less
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`than one micron wide and typically about 0.5 microns
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`wide. These can be formed by conventional RIE etch-
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`ing in a well-known manner, such as, for example, in a
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`plasma of NF3+Ar at 10 mTorr and 0.1—0.2 W/cmz,
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`utilizing the photoresist as a mask material which is a
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`Page 3 of 6
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`

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`5,173,439
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`3
`4
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`which are well-known, may be used to form the
`5 in which the underlying silicon nitride 12 has been
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`trenches l4 and 16.
`revealed on both sides of the wide trench 14 and on
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`both sides of the narrow trench 16. Also, it should be
`the present invention is espe-
`As indicated above,
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`cially useful for forming dielectric filled wide trenches;
`noted that with respect to the narrow trench 16, since
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`however, FIGS. 1 through 6 illustrate how the present
`there was no polysilicon material overlying the silicon
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`invention can be used on substrates which contain nar-
`dioxide in the trench 16, that the etch was also reacting
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`row trenches as well as wide trenches.
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`with the SiOz overlying the trench 16 to provide a
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`As shown in FIG. 3, a layer of silicon dioxide ($02)
`planarized surface of the dielectric material 18 with
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`18 is formed over the surface of the substrate, including
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`respect to the silicon nitride 12. However, with respect
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`both the wide and narrow trenches 14 and 16. Prefera-
`to the material overlying the wide trench 14, a plug of
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`bly the SiOz layer is deposited using well-known CVD
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`material is left which comprises the SiOz material un—
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`processes which typically includes vapor deposition in
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`derlying the polysilicon 20. This plug of material ex-
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`tetraethylorthosilane CTEOS) at 650 mTorr at 715° C.
`tends significantly ab0ve the planarized level of the
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`Of course, other processes could be used. The thickness
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`silicon nitride 12, thus providing essentially a planarized
`of the CVD SiOz layer is approximately equal to the
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`surface over all of the substrate, except over any
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`total depth of the trench so that the top of the SiOz layer
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`trenches where there are these plugs of material.
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`in the trench 14 is approximately even with the top
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`The entire wafer shown in FIG. 5 is then again
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`chemically—mechanically polished using a silica slurry
`layer “of the silicon substrate. This is typically about
`6000 A in thickness, although this can vary greatly with
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`in basic aqueous solution and polished against a rotating
`different substrates, depending upon the utilization of 20
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`polyurethane disk. This polishing step will remove the
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`plugs of material which are above the wide trenches 14
`the substrates for forming devices and the type of con-
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`ductors which are to be formed on the substrate.
`resulting in a final structure shown in FIG. 6. The sili-
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`con nitride 12 acts as the end point for the polishing so
`On top of the silicon dioxide layer 18 is formed a thip
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`that the entire surface of the wafer which includes both
`layer of polysilicon 20 which typically is about 1000 A
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`wide and narrow trenches filled with silicon dioxide are
`thick. This polysilicon can be deposited in any conven-
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`tional manner,
`a preferred method being CVD in
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`essentially planarized and hence ready for further pro-
`SiH4+H2 at 400 mTorr at 620° C. This resultant struc-
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`cessing such as the formation of the conductor patterns
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`on the surface.
`ture is shown in FIG. 3. This structure is then subjected
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`to a chemical-mechanical polish to remove just that
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`Several modifications can be made to the process.
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`portion of the polysilicon 20 which is located outside
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`For example, a thin (50 nm) layer of polysilicon can be
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`the confines of the trench 14. In the preferred polishing
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`deposited over the silicon nitride layer 12. This will
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`technique the substrate is mounted onto a flat circular
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`improve the selectivity of the SiOz RIE, making com-
`holder which maintains the exposed surface of the
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`plete removal thereof more feasible without impairing
`polysilicon 20 is contact with a rotating polyurethane
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`the uniformity of the silicon nitride etch stop. Also a
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`pad. The pad is wetted with a slurry of an abrasive
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`thin (50 nm) layer of silicon nitride can be deposited
`material in a basic aqueous solution, such as $02, plus
`over the SiOz layer 18 before the deposition of the
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`aluminum oxide (A1203) and tetramethylammonium
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`polysilicon layer 20. This will help prevent reduction of
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`hydroxide (TMAH). As the polyurethane pad rotates
`the SiOz layer during the first chemical-mechanical
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`against the surface of the exposed polysilicon, the chem-
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`polishing step for the remaining polysilicon layer 20
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`icals react with the very outer-most surface of the
`overlying the trenches 18.
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`polysilicon 20 to loosen it from the polysilicon which
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`It is also contemplated that similar process steps can
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`underlies it. The mechanical or abrasive action of the
`be used to form planarized surfaces wherein trenches
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`SiOz then removes this loosened surface wherever it
`are filled with conductive materials rather than dielec-
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`contacts it. Such chemical-mechanical polishing is well-
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`tric material. In such case, the masking materials and
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`known in the art. This is a continuous process in that a
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`etch reagents and conditions are selected to provide the
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`continuous reaction occurs at the outer surface with the
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`selectivity required.
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`chemicals for loosening this layer and those loosened
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`While several embodiments of the present invention
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`portions of the polysilicon are removed by the abrasive
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`have been shown and described, various adaptions and
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`action of the $02.
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`modifications can be made without departing from the
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`The chemical-mechanical polishing continues until
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`scope of the invention as defined in the appended
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`claims.
`all of the polysilicon that lies outside of the boundaries
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`of the trench 14 has been removed as shown in FIG. 4.
`What is claimed is:
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`Coincidentally it can be seen that actually all of the
`l. A process for forming a wide dielectric-filled isola-
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`polysilicon has been removed from the surface of the
`tion trench in the surface of a semi—conductor substrate
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`dielectric 18, filling the narrow trench 16. This, how- 55 comprising the steps of:
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`ever, is not a problem because of the narrowness of the
`forming a wide trench in the surface of the substrate;
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`trench l6, and there is very little conformality which is
`conformally forming a layer of dielectric material
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`indicated by the small indentation shown thereabove
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`over the surface of the substrate including in said
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`and is not significant.
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`trench the top surface of which layer of dielectric
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`The material shown in FIG. 4 is then anisotropically
`material extends above the plane of the surface of
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`etched by reactive ion etching (RIB). Typically this can
`the substrate;
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`be done in a CHF3+C02 atmosphere at 0.1.0.2
`conformally forming a layer of etch resistant material
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`W/CM2 and 40 mTorr. This RIE is reactive with the
`on said layer of dielectric material which etch resis-
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`$02 material 18 but is not reactive with the polysilicon
`tant material will mask said dielectric material from
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`65
`material 20. Thus, the SiOz material not masked by the
`reactive ion etching;
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`polysilicon material 20 is removed with the silicon ni-
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`selectively removing only those portions of said etch
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`tride layer 12 acting as an etch stop in a well-known
`resistant material that extend above the surface of
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`manner. This will result in the structure shown in FIG.
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`the dielectric material by physical polishing and
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`60
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`Page 4 of 6
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`

`

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`6
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`10. The invention as defined in claim 9 wherein a
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`layer of polysilicon is formed between said silicon ni-
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`tride layer and said layer of dielectric material to pro-
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`vide an etch stop for silicon dioxide removal.
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`11. The invention as defined in claim 7 wherein a
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`layer of silicon nitride is formed over the dielectric
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`material.
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`12. A process for forming a filled wide trench in the
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`surface of a substrate comprising the steps of:
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`forming a wide trench in the surface of the substrate;
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`conformally forming a layer of filling material on the
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`surface of the substrate including in said trench the
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`top surface of which filling material extends above
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`the plane of the surface of the substrate;
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`conformally forming a layer of etch-resistant material
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`on said layer of filling material which etch resistant
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`material will mask said filling material from reac-
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`tive ion etching;
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`selectively removing only those portions of said etch
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`resistant material that extend above the surface of
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`the filling material by physical polishing and not
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`removing any etch resistant material disposed
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`below the surface of said filling material, such that
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`the only remaining portion of the etch resistant
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`material resides within the width of said trench;
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`forming a plug above said trench comprising the
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`remaining etch resistant material overlying filling
`material by anisotropically etching said layer of
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`filling material which is not masked by said etch
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`resistant material down to the top of said trench;
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`and
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`removing said plug to obtain a filled trench having an
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`upper surface in substantial planarity with the
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`upper surface of said substrate.
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`13. The invention as defined in claim 12 wherein said
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`filling material is a conductive material.
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`14. The invention as defined in claim 12 wherein said
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`filling material is a dielectric material.
`*
`if
`it
`¥
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`5
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`not removing any etch resistant material disposed
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`below the surface of said dielectric material, such
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`that the only remaining portion of the etch resistant
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`material resides within the width of said trench;
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`forming a dielectric plug ab0ve said trench compris-
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`ing the remaining etch resistant material overlying
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`dielectric material by anisotropically reactive ion
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`etching said layer of dielectric material which is
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`not masked by said etch resistant material down to
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`the top of said trench; and
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`removing said dielectric plug to obtain a dielectric-
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`filled trench having an upper surface in substantial
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`planarity with the upper surface of said substrate.
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`2. The invention as defined in claim 1 wherein said
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`dielectric material forms a depression above'the wide
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`trench.
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`3. The invention as defined in claim 1 wherein said
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`etch-resistant material is polysilicon.
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`4. The invention as defined in claim 3 wherein the
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`selective removal of polysilicon comprises chemical-
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`mechanical polishing.
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`5. The method of claim 4 wherein the chemical me-
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`chanical polishing of the polysilicon is done with a
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`slurry of abrasive material maintained in a basic aqueous
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`solution.
`7
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`6. The invention as defined in claim 1 wherein said
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`plug material is removed down to the top of the trench
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`by chemical-mechanical polishing.
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`7. The invention as described in claim 6 wherein a 30
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`layer of etch stop material is provided on the surface of
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`said semi-conductor substrate at least in the region adja-
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`cent said wide trenches, and said layer of dielectric
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`material which is not masked by said etch resistant
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`material is etched down to the etch stop layer.
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`8. The invention as defined in claim 1 wherein said
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`dielectric material is silicon dioxide.
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`9. The invention as defined in claim 7 wherein said
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`etch stop material is silicon nitride.
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`*
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`5,17 3,439
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`10
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`35
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`Page 5 of 6
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`

`

`A
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`
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`PATENT N0.
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`DATED
`
`|NVENTOR(S)
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`5,173,439
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`
`Dec. 22, 1992
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`Dash, et a1.
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`It is certified that error appears in the above-identified patent and that said Letters Patent is hereby
`corrected as shown below:
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`Column 5,
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`line 33 change "trenches, and" to —-trench,
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`and——
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`Signed and Sealed this
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`Arresting Officer
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`BRUCE LEHMAN
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`CERTIFICATE OF CORRECTION
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`:
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`2
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`:
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`Cummisxioner of Parents and Trademarks
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`Second Day of November, 1998
`mm
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`Page 6 of 6
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