UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`
`
`Case IPR2016-012461
`Patent 7,126,174 B2
`
`
`DECLARATION OF DR. SANJAY KUMAR BANERJEE, PH.D. IN
`SUPPORT OF PETITIONER’S REPLY
`
`
`
`
`
`
`
`
`
`
`1 Case IPR2016-01247 has been consolidated with this proceeding.
`
`
`
`
`
`Page 1 of 204
`
`TSMC Exhibit 1057
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

`TABLE OF CONTENTS
`
`I.
`
`II.
`
`INTRODUCTION ......................................................................................... 1
`
`SUMMARY OF OPINIONS......................................................................... 2
`
`III. BACKGROUND AND QUALIFICATIONS .............................................. 2
`
`A.
`
`B.
`
`C.
`
`Background ........................................................................................... 2
`
`Previous Expert Witness Experience .................................................... 6
`
`Compensation ........................................................................................ 6
`
`IV. MATERIALS REVIEWED .......................................................................... 6
`
`V.
`
`LEGAL STANDARDS FOR OBVIOUSNESS .........................................14
`
`VI. LEVEL OF ORDINARY SKILL ...............................................................20
`
`VII. BACKGROUND KNOWLEDGE OF A PERSON OF
`ORDINARY SKILL IN THE ART REGARDING TRENCH
`ISOLATION .................................................................................................23
`
`A.
`
`B.
`
`STI With a Dedicated Stopper Layer ..................................................31
`
`STI Without a Dedicated Stopper Layer .............................................41
`
`VIII. STI PROCESS INTEGRATION ...............................................................47
`STI Process Integration in Lee ............................................................48
`
`A.
`
`B.
`
`STI Process Integration in Lowrey ......................................................54
`
`IX. A PERSON OF ORDINARY SKILL IN THE ART WOULD
`HAVE UNDERSTOOD THAT SILICON DIOXIDE LAYERS 62
`AND 71 IN LOWREY ARE DISTINCT STRUCTURES .......................84
`
`X.
`
`THE SELF-ALIGNED SILICIDE (“SALICIDE” PROCESS) ..............89
`
`XI. L-SHAPED SIDEWALLS ..........................................................................91
`
`XII. CONCLUSION ............................................................................................92
`
`
`
`
`
`
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`Page 3 of 204
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`ii
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`ii
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`Page 3 of 204
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`I, Dr. Sanjay Kumar Banerjee, Ph.D., declare as follows:
`
`I.
`
`Introduction
`
`1. My name is Dr. Sanjay Kumar Banerjee. I have been asked to submit
`
`this declaration on behalf of Taiwan Semiconductor Manufacturing Company, Ltd.
`
`(“TSMC” or “Petitioner”) in connection with a petition for inter partes review of
`
`U.S. Patent No. 7,126,174 (“the ’174 patent”), which I have been told is being
`
`submitted to the Patent Trial and Appeal Board of the United States Patent and
`
`Trademark Office by TSMC.
`
`2.
`
`I have been retained as a technical expert by TSMC to study and
`
`provide my opinions on the technology claimed in, and the patentability or non-
`
`patentability of, claims 1–12 and 14–18 in the ’174 patent (“the Challenged
`
`Claims”).
`
`3.
`
`I understand the ’174 patent is related to U.S. Patent Nos. 6,967,409
`
`(the ’409 patent), 6,709,950 (the ’950 patent), and 6,281,562 (the ’562 patent) and
`
`also claims the benefit of priority to two Japanese applications, JP 7-192181,
`
`which was filed on July 27, 1995, and JP 7-330112, which was filed on December
`
`19, 1995.
`
`
`
`
`
`Page 4 of 204
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`

`

`II.
`
`Summary of Opinions
`
`4.
`
`This declaration is directed to the Challenged Claims of the ’174
`
`patent, and sets forth certain opinions I have formed, the conclusions I have
`
`reached, and the bases for each.
`
`5.
`
`Based on my experience, knowledge of the art at the relevant time,
`
`analysis of prior art references, and the understanding a person of ordinary skill in
`
`the art would have of the claim terms in light of the specification, it is my opinion
`
`that all of the Challenged Claims of the ’174 patent are unpatentable as being
`
`obvious over the prior art references discussed below.
`
`III. Background and Qualifications
`A. Background
`I am currently the Cockrell Family Chair Professor of Electrical and
`6.
`
`Computer Engineering at the University of Texas at Austin. At UT Austin, I am
`
`also the director of the Microelectronics Research Center. I have been a faculty
`
`member at UT Austin since 1987.
`
`7.
`
`I have also been active in industries related to the relevant field of art.
`
`As a Member of the Technical Staff, Corporate Research, Development and
`
`Engineering of Texas Instruments Incorporated from 1983–1987, I worked on
`
`polysilicon transistors and dynamic random access trench memory cells used by
`
`Texas Instruments in the world’s first 4-Megabit DRAM, for which I was co-
`
`
`
`2
`
`Page 5 of 204
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`

`

`recipient of the Best Paper Award, IEEE International Solid State Circuits
`
`Conference, 1986.
`
`8.
`
`I received a B.Tech from the Indian Institute of Technology,
`
`Kharagpur, an M.S. and Ph.D. from the University of Illinois at Urbana-
`
`Champaign, all in Electrical Engineering.
`
`9.
`
`I am a leading researcher and educator in various areas of transistor
`
`device fabrication technology, including the fabrication, characterization and
`
`applications of memory devices, transistors, and nanotechnology. My research has
`
`been funded by the Texas Advanced Technology Program (ATP), the Texas
`
`Higher Education Coordinating Board, the National Science Foundation, the
`
`SEMATECH (Semiconductor Manufacturing Technology) consortium, the SRC
`
`(Semiconductor Research Corporation) consortium, DARPA, and the Department
`
`of Energy, among others.
`
`10. At the University of Texas, I am the director of the Microelectronics
`
`Research Center, comprised of faculty colleagues, graduate, and undergraduate
`
`students. I also serve as the director of the South West Academy of
`
`Nanoelectronics, one of three centers in the United States to develop a replacement
`
`for MOSFETs.
`
`11.
`
`I have published over 1,000 technical articles, many related to
`
`semiconductor fabrication technology, most at highly competitive refereed
`
`
`
`3
`
`Page 6 of 204
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`

`

`conferences and rigorously reviewed journals. I have also published 8 books or
`
`chapters on transistor device physics and fabrication, and have supervised over 50
`
`Ph.D. and 60 MS students.
`
`12.
`
`I have been a member of scientific organizations and committees,
`
`including the IEEE Dan Noble Award Committee from 2010–2013, serving as
`
`Chair from 2012–2013, the International Technology Roadmap for
`
`Semiconductors, the International Conference on MEMS (Microelectromechanical
`
`Systems) and Nanotechnology, the IEEE International Conference on
`
`Communications, Computers, Devices, the International Electron Devices
`
`Meeting, the International Conference on Simulation of Semiconductor Processes
`
`and Devices, and the IEEE Symposium on VLSI (Very-Large-Scale Integration)
`
`Technology.
`
`13.
`
`I have served as the Session Chair for the “Device Technology”
`
`Session conducted at the IEEE International Electron Devices Meeting in 1989–
`
`1990. I have also served as the General Chairman for the IEEE University
`
`Government Industry Microelectronics Symposium in 1994–1995, and Chair of the
`
`IEEE Device Research Conference.
`
`14.
`
`I have served on the Technical Advisory Boards of AstroWatt, DSM
`
`Semiconductors, Cambrios, Nanocoolers Inc., BeSang Memories, Organic ID and
`
`
`
`4
`
`Page 7 of 204
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`

`

`ITU Ventures; Gerson Lehmann Group, NY; Austin Community College; Asia
`
`Pacific IIT; Rochester Institute of Technology, and HSMC Foundry.
`
`15.
`
`I received the Engineering Foundation Advisory Council Halliburton
`
`Award (1991), the Texas Atomic Energy Fellowship (1990–1997), Cullen
`
`Professorship (1997–2001) and the Hocott Research Award from UT Austin
`
`(2007). I also received the IEEE Grove Award (2014), Distinguished Alumnus
`
`Award, IIT (2005), Industrial R&D 100 Award (2004), ECS Callinan Award,
`
`2003, IEEE Millennium Medal, 2000, NSF Presidential Young Investigator Award
`
`in 1988, and several SRC Inventor Recognition and Best Paper Awards.
`
`16.
`
`I was a Distinguished Lecturer for IEEE Electron Devices Society,
`
`and am a Fellow of the Institute of the Electrical and Electronics Engineers (IEEE),
`
`the American Physical Society (APS) and the American Association for the
`
`Advancement of Science (AAAS).
`
`17.
`
`I am the inventor or co-inventor of over 30 United States patents in
`
`various areas of transistor device fabrication technology.
`
`18. Additional details about my employment history, fields of expertise,
`
`and publications are further included in my curriculum vitae (attached as Appendix
`
`A).
`
`
`
`5
`
`Page 8 of 204
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`

`

`B.
`19.
`
`Previous Expert Witness Experience
`
`I have served as an expert witness since the mid 1990’s. In the last ten
`
`years or so, I have testified at the International Trade Commission three times, and
`
`the Northern District of California once. In addition, I have been deposed six times
`
`on patents related to CMOS and semiconductor memories such as flash and
`
`DRAMs. Several of these have been IPR cases.
`
`C. Compensation
`I am being compensated for services provided in this matter at my
`20.
`
`usual and customary rate of $500 per hour plus travel expenses. My compensation
`
`is not conditioned on the conclusions I reach as a result of my analysis or on the
`
`outcome of this matter. Similarly, my compensation is not dependent upon and in
`
`no way affects the substance of my statements in this declaration.
`
`21.
`
`I have no financial interest in Petitioner or any of its subsidiaries. I
`
`also do not have any financial interest in Patent Owner Godo Kaisha IP Bridge 1. I
`
`do not have any financial interest in the ’174 patent and have not had any contact
`
`with any of the named inventors of the ’174 patent (Mizuki Segawa, Isao
`
`Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita,
`
`Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, and Michikazu Matsumoto).
`
`IV. Materials Reviewed
`
`22.
`
`In forming my opinions, I have reviewed the following references:
`
`
`
`6
`
`Page 9 of 204
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`

`

`• The ’174 patent (which I have been told is Exhibit 1001);
`
`• U.S. Patent No. 5,153,145 to Lee et al. (“Lee,” which I have been told
`
`is Exhibit 1002);
`
`• U.S. Patent No. 3,617,824 to Shinoda et al. (“Shinoda,” which I have
`
`been told is Exhibit 1003);
`
`• J.A. Appels et al., Some Problems of MOS Technology, Philips Tech.
`
`Rev. vol. 31 nos. 7–9, pp. 225–36 (1970) (“Appels,” which I have been
`
`told is Exhibit 1005);
`
`• U.S. Patent No. 4,110,899 to Nagasawa et al. (“Nagasawa,” which I
`
`have been told is Exhibit 1006);
`
`• U.S. Patent No. 3,787,251 to Brand et al. (“Brand,” which I have been
`
`told is Exhibit 1007);
`
`• B.B.M. Brandt et al., “LOCMOS, a New Technology for
`
`Complementary MOS Circuits,” Philips Tech. Rev. vol. 34 no. 1, pp.
`
`19–23 (1974) (“Brandt,” which I have been told is Exhibit 1008);
`
`• U.S. Patent No. 5,702,976 to Schuegraf et al. (“Schuegraf,” which I
`
`have been told is Exhibit 1009);
`
`• U.S. Patent No. 4,506,434 to Ogawa et al. (“Ogawa,” which I have
`
`been told is Exhibit 1010);
`
`
`
`7
`
`Page 10 of 204
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`

`

`• U.S. Patent No. 4,957,590 to Douglas (“Douglas,” which I have been
`
`told is Exhibit 1011);
`
`• U.S. Patent No. 5,976,939 to Thompson et al. (“Thompson,” which I
`
`have been told is Exhibit 1012);
`
`• U.S. Patent No. 6,165,826 to Chau et al. (“Chau,” which I have been
`
`told is Exhibit 1013);
`
`• U.S. Patent No. 5,733,812 to Ueda et al. (“Ueda,” which I have been
`
`told is Exhibit 1014);
`
`• U.S. Patent No. 5,539,229 to Noble, Jr. et al. (“Noble,” which I have
`
`been told is Exhibit 1015);
`
`• U.S. Patent No. 5,521,422 to Mandelman et al. (“Mandelman” which I
`
`have been told is Exhibit 1016);
`
`• U.S. Patent No. 5,021,353 to Lowrey et al. (“Lowrey,” which I have
`
`been told is Exhibit 1017);
`
`• U.S. Patent No. 4,638,347 to Iyer (“Iyer,” which I have been told is
`
`Exhibit 1018);
`
`• Japanese Patent Application No. H07-192181 to Segawa et al. (which I
`
`have been told is Exhibit 1019);
`
`• Certified Translation of Japanese Patent Application No. H07-192181
`
`to Segawa et al. (which I have been told is Exhibit 1020);
`
`
`
`8
`
`Page 11 of 204
`
`

`

`• File History of U.S. Patent No. 7,126,174 to Segawa et al. (which I
`
`have been told is Exhibit 1021);
`
`• File History of Japanese Patent Application No. H07-330112 to
`
`Segawa et al. (which I have been told is Exhibit 1022);
`
`• Certified Translation of the File History of Japanese Patent Application
`
`No. H07-330112 to Segawa et al. (which I have been told is Exhibit
`
`1023);
`
`• Japanese Patent Application No. H07-192181 to Segawa et al. (which I
`
`have been told is Exhibit 1019);
`
`• Certified Translation of Japanese Patent Application No. H07-192181
`
`to Segawa et al. (which I have been told is Exhibit 1020);
`
`• E. Adler et al., “The Evolution of IBM CMOS DRAM Technology,”
`
`IBM J. Res. Develp., vol. 39, no. 1/2, pp. 167–88 (Jan/Mar. 1995)
`
`(“Adler,” which I have been told is Exhibit 1025);
`
`• Japanese Patent Application No. H03-379033 to Sumi et al. (which I
`
`have been told is Exhibit 1026);
`
`• Certified Translation of Japanese Patent Application No. H03-379033
`
`to Sumi et al. (“Sumi,” which I have been told is Exhibit 1027);
`
`• Japanese Patent Application No. S59-181062 to Horiguchi (“Horiguchi
`
`JP,” which I have been told is Exhibit 1028);
`
`9
`
`
`
`Page 12 of 204
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`

`

`• Certified Translation of Japanese Patent Application No. S59-181062
`
`to Horiguchi (“Horiguchi,” which I have been told is Exhibit 1029);
`
`• Japanese Patent Application No. H07-183518 to Ueda et al. (which I
`
`have been told is Exhibit 1030);
`
`• Certified Translation of Japanese Patent Application No. H07-183518
`
`to Ueda et al. (“Ueda JP” which I have been told is Exhibit 1031);
`
`• U.S. Patent No. 4,651,411 to Konaka et al. (“Konaka,” which I have
`
`been told is Exhibit 1032);
`
`• Japanese Patent Application No. S58-73163 to Konaka et al. (“Konaka
`
`JP,” which I have been told is Exhibit 1033);
`
`• U.S. Patent No. 6,218,266 to Sato et al. (“Sato,” which I have been told
`
`is Exhibit 1034);
`
`• U.S. Patent No. 5,445,996 to Kodera et al. (“Kodera,” which I have
`
`been told is Exhibit 1035);
`
`• U.S. Patent No. 4,511,430 to Chen et al. (“Chen,” which I have been
`
`told is Exhibit 1036);
`
`• U.S. Patent No. 4,599,789 to Gasner (“Gasner,” which I have been
`
`told is Exhibit 1037);
`
`• U.S. Patent No. 4,855,247 to Ma et al. (“Ma,” which I have been told
`
`is Exhibit 1038);
`
`10
`
`
`
`Page 13 of 204
`
`

`

`• U.S. Patent No. 5,102,816 to Manukonda et al. (“Manukonda,” which I
`
`have been told is Exhibit 1039);
`
`• U.S. Patent No. 5,512,771 to Hiroki et al. (“Hiroki,” which I have been
`
`told is Exhibit 1040);
`
`• U.S. Patent No. 5,173,439 to Dash et al. (“Dash,” which I have been
`
`told is Exhibit 1058);
`
`• U.S. Patent No. 5,648,284 to Kusunoki et al. (“Kusunoki,” which I
`
`have been told is Exhibit 1041);
`
`• S. Deleonibus et al., “Optimization of a Shallow Trench Isolation
`
`Refill Process for High Density Non Volatile Memories Using 100%
`
`Chemical-Mechanical Polishing: The BOX-ON Process,” Extended
`
`Abstracts of the Spring 1994 Electrochem. Soc. Meeting, abstract no.
`
`171, vol. 94-1, pp. 267–77 (May 22–27, 1994) (“Deleonibus,” which I
`
`have been told is Exhibit 1042);
`
`• J.M. Pierce et al., “Oxide-Filled Trench Isolation Planarized Using
`
`Chemical/Mechanical Polishing,” Proceedings of the Third
`
`International Symposium on Ultra Large Scale Integration Science and
`
`Technology, vol. 91-11, pp. 650–56 (1991) (“Pierce,” which I have
`
`been told is Exhibit 1043);
`
`
`
`11
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`Page 14 of 204
`
`

`

`• Excerpts from C.Y. Chang & S.M. Sze, “ULSI Technology” (1996)
`
`(“ULSI Technology,” which I have been told is Exhibit 1044);
`
`• Excerpts from S. Wolf, “Silicon Processing for the VLSI Era:
`
`Volume 1: Process Technology” (1986) (“Wolf1,” which I have been
`
`told is Exhibit 1045);
`
`• Excerpts from S. Wolf, “Silicon Processing for the VLSI Era:
`
`Volume 2: Process Integration” (1990) (“Wolf2,” which I have been
`
`told is Exhibit 1046);
`
`• H.W. Fry et al., “Applications of APCVD TEOS/O3 Thin Films in
`
`ULSI IC Fabrication,” Solid State Tech., pp. 31–40 (Mar. 1994)
`
`(“Fry,” which I have been told is Exhibit 1047);
`
`• S. Poon & C. Lage, “A Trench Isolation Process for BiCMOS
`
`Circuits,” Proceedings of the 1993 IEEE Bipolar Circuits & Tech.
`
`Meeting 3.3, pp. 45–48 (Oct. 4–5, 1993) (“Poon,” which I have been
`
`told is Exhibit 1048);
`
`• L. Clement et al., “Microscopy Needs for Next Generation Devices
`
`Characterization in the Semiconductor Industry,” J. Physics:
`
`Conference Series, vol. 326, conf. 1, 17th International Conference on
`
`Microscopy of Semiconducting Materials, pp. 1–14 (Apr. 4–7, 2011)
`
`(“Clement,” which I have been told is Exhibit 1049);
`
`
`
`12
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`

`

`• R. Pantel et al., “Physical and Chemical Analysis of Advanced
`
`Interconnections Using Energy Filtered Transmission Electron
`
`Microscopy,” Microelectronic Engineering, vol. 50, nos. 1–4, pp. 277–
`
`84 (Jan. 2000) (“Pantel,” which I have been told is Exhibit 1050);
`
`• G. Servanton & R. Pantel, “Arsenic Dopant Mapping in State-of-the –
`
`Art Semiconductor Devices Using Electron Energy-Loss
`
`Spectroscopy,” Micron, vol. 41, no. 2, pp. 118–22 (Feb. 2010)
`
`(“Servanton,” which I have been told is Exhibit 1051);
`
`• K. Kurosawa et al., “A New Bird’s-Beak Free Field Isolation
`
`Technology for VLSI Devices,” Proceedings of the 1981 International
`
`Electron Devices Meeting, pp. 384–87 (Dec. 7–9, 1981) (“Kurosawa”
`
`which I have been told is Exhibit 1052);
`
`• H.K. Kang et al., “Highly Manufacturable Process Technology for
`
`Reliable 256 Mbit and 1 Gbit DRAMs,” Proceedings of the 1994
`
`International Electron Devices Meeting, pp. 635–38 (Dec. 11–14,
`
`1994) (“Kang,” which I have been told is Exhibit 1053);
`
`• Semiconductor Industry Association, “The National Technology
`
`Roadmap for Semiconductors” (1994) (“SIA Roadmap,” which I have
`
`been told is Exhibit 1054);
`
`
`
`13
`
`Page 16 of 204
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`

`

`• B. Davari et al., “A New Planarization Technique, Using a
`
`Combination of RIE and Chemical Mechanical Polish (CMP),”
`
`Proceedings of the 1989 International Electron Devices Meeting, pp.
`
`61–64 (Dec. 3–6, 1989) (“Davari,” which I have been told is Exhibit
`
`1055); and
`
`• Deposition Transcript of E. Fred Schubert, Ph.D. dated May 25, 2017
`
`(which I have been told is Exhibit 1056).
`
`V. Legal Standards for Obviousness
`
`23.
`
`I am not an attorney and have not been asked to offer my opinion on
`
`the law. However, as an expert offering an opinion on whether the claims in the
`
`’174 patent are patentable, I have been told that I am obliged to follow existing
`
`law. I have been told the following legal principles apply to analysis of
`
`obviousness.
`
`24.
`
`I also understand that, in an inter partes review proceeding, patent
`
`claims may be deemed unpatentable if it is shown by preponderance of the
`
`evidence that they were rendered obvious by one or more prior art patents or
`
`publications.
`
`25.
`
`I have been told that under 35 U.S.C. § 103(a), “[a] patent may not be
`
`obtained although the invention is not identically disclosed or described as set forth
`
`in section 102, if the differences between the subject matter sought to be patented
`
`
`
`14
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`

`

`and the prior art are such that the subject matter would have been obvious at the
`
`time the invention was made to a person having ordinary skill in the art to which
`
`said subject matter pertains.”
`
`26. When considering the issues of obviousness, I have been told that I
`
`am to do the following:
`
`a.
`
`b.
`
`c.
`
`d.
`
`Determine the scope and content of the prior art;
`
`Ascertain the differences between the prior art and the claims at
`
`issue;
`
`Resolve the level of ordinary skill in the pertinent art; and
`
`Consider evidence of secondary indicia of non-obviousness (if
`
`available).
`
`27.
`
`I have been told that the relevant time for considering whether a claim
`
`would have been obvious to a person of ordinary skill in the art is the time of
`
`alleged invention, which I have assumed is shortly before the ’174 patent was filed.
`
`28.
`
`I have been told that obviousness is a determination of law based on
`
`underlying determinations of fact. I have been told that these factual
`
`determinations include the scope and content of the prior art, the level of ordinary
`
`skill in the art, the differences between the claimed invention and the prior art, and
`
`secondary considerations of non-obviousness.
`
`
`
`15
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`
`

`

`29.
`
`I have been told that any assertion of secondary indicia must be
`
`accompanied by a nexus between the merits of the invention and the evidence
`
`offered.
`
`30.
`
`I have been told that a reference may be combined with other
`
`references to disclose each element of the invention under § 103. I have been told
`
`that a reference may also be combined with the knowledge of a person of ordinary
`
`skill in the art and that this knowledge may be used to combine multiple
`
`references. I have also been told that a person of ordinary skill in the art is
`
`presumed to know all relevant prior art. I have been told that the obviousness
`
`analysis may take into account the inferences and creative steps that a person of
`
`ordinary skill in the art would employ.
`
`31.
`
`In determining whether a prior art reference could have been
`
`combined with another prior art reference or other information known to a person
`
`having ordinary skill in the art, I have been told that the following principles may
`
`be considered:
`
`a. A combination of familiar elements according to known methods is
`
`likely to be obvious if it yields predictable results;
`
`b. The substitution of one known element for another is likely to be
`
`obvious if it yields predictable results;
`
`
`
`16
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`

`

`c. The use of a known technique to improve similar items or methods in
`
`the same way is likely to be obvious if it yields predictable results;
`
`d. The application of a known technique to a prior art reference that is
`
`ready for improvement, to yield predictable results;
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`e. Any need or problem known in the field and addressed by the
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`reference can provide a reason for combining the elements in the
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`manner claimed;
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`f. A person of ordinary skill often will be able to fit the teachings of
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`multiple references together like a puzzle; and
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`g. The proper analysis of obviousness requires a determination of
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`whether a person of ordinary skill in the art would have a “reasonable
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`expectation of success”—not “absolute predictability” of success—in
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`achieving the claimed invention by combining prior art references.
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`32.
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`I have been told that whether a prior art reference renders a patent
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`claim unpatentable as obvious is determined from the perspective of a person of
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`ordinary skill in the art. I have been told that there is no requirement that the prior
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`art contain an express suggestion to combine known elements to achieve the
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`claimed invention, but a suggestion to combine known elements to achieve the
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`claimed invention may come from the prior art, as filtered through the knowledge
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`of one skilled in the art. In addition, I have been told that the inferences and
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`creative steps a person of ordinary skill in the art would employ are also relevant to
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`the determination of obviousness.
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`33.
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`I have been told that, when a work is available in one field, design
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`alternatives and other market forces can prompt variations of it, either in the same
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`field or in another. I have been told that if a person of ordinary skill in the art can
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`implement a predictable variation and would see the benefit of doing so, that
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`variation is likely to be obvious. I have been told that, in many fields, there may
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`be little discussion of obvious combinations, and in these fields market demand—
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`not scientific literature—may drive design trends. I have been told that, when
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`there is a design need or market pressure and there are a finite number of
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`predictable solutions, a person of ordinary skill in the art has good reason to pursue
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`those known options.
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`34.
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`I have been told that there is no rigid rule that a reference or
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`combination of references must contain a “teaching, suggestion, or motivation” to
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`combine references. But I also understand that the “teaching, suggestion, or
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`motivation” test can be a useful guide in establishing a rationale for combining
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`elements of the prior art. I have been told that this test poses the question as to
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`whether there is an express or implied teaching, suggestion, or motivation to
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`combine prior art elements in a way that realizes the claimed invention, and that it
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`seeks to counter impermissible hindsight analysis.
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`35.
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`I have been told that a determination of obviousness based on
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`teachings from multiple references does not require an actual, physical substitution
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`of elements. I have been told the proper test for obviousness is what the combined
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`teachings of the references would have suggested to those having ordinary skill in
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`the art.
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`36.
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`I have been told that a reference must be considered for everything
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`that it teaches, not simply the described invention or a preferred embodiment.
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`37.
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`I have been told that a reference “teaches away” when a person of
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`ordinary skill, upon reading the reference, would be discouraged from following
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`the path set out in the reference. I have also been told the existence of better
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`alternatives in the prior art does not mean that an inferior alternative is inapt for
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`obviousness purposes.
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`38.
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`I have been told that a person of ordinary skill in the art is a person of
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`ordinary creativity, not an automaton, and knows how to combine familiar prior art
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`elements to achieve the same functions. I have been told it is improper to ignore
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`modifications that one skilled in the art would make to a device borrowed from the
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`prior art.
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`39.
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`I have been told that a reference may disclose an embodiment in
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`textual form and that the disclosure of multiple embodiments does detract from the
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`other disclosures.
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`40.
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`I have been told it is improper to rely on drawings that are neither
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`expressly to scale nor linked to quantitative values in the text.
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`VI. Level of Ordinary Skill
`I understand a person of ordinary skill in the art is determined by
`41.
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`looking at (A) type of problems encountered in the art; (B) prior art solutions to
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`those problems; (C) rapidity with which innovations are made; (D) sophistication
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`of the technology; and (E) educational level of active workers in the field. Based
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`on my experience in this art in the 1990s, I believe people that fit this description
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`would have had (1) the equivalent of a Master of Science degree from an
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`accredited institution in electrical engineering, materials science, physics, or the
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`equivalent; (2) a working knowledge of semiconductor processing technologies for
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`integrated circuits; and (3) at least two years of experience in related
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`semiconductor processing analysis, design, and development. Additional graduate
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`education could substitute for professional experience, and significant work
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`experience could substitute for formal education.
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`42.
`
`I understand that the Patent Owner has proposed the following
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`definition of ordinary skill in the art: A person of ordinary skill in the art would
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`have at least a Bachelor’s degree in Electrical, Materials, Mechanical, or Chemical
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`Engineering, or a related degree, and at least two years of experience working in
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`semiconductor processing and fabrication, semiconductor equipment
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`manufacturing, or semiconductor materials.
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`43.
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`In my view, the level of skill proposed by the Patent Owner to be
`
`overly broad. The Patent Owner’s definition is not sufficiently tied to the types of
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`materials and devices relevant to the ’174 patent. In fact, it is not tied to any
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`devices or materials at all. The category of “semiconductor processing and
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`fabrication,” for example, would include people who never made integrated
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`circuits or transistors of any kind, let alone LDD MOSFETs of the kind at issue in
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`the ’174 patent. This category would also include people whose sole experience
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`included, for example, work on light emitting devices, semiconductor light
`
`detectors, solar cells, discrete devices, or the like. This category does not
`
`necessarily require a person of ordinary skill in the art to have faced challenges
`
`concerning CMOS integrated circuits, such as problems with device isolation and
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`device scaling.
`
`44.
`
`In my opinion, the category of “semiconductor materials” is also too
`
`broad. This would include people who never worked on silicon devices at all. For
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`example, it includes people whose only experience relates to III-V compound
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`semiconductors, which are processed very differently from silicon devices, faced
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`very different issues, and had very different applications. This category of the
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`Patent Owner’s definition would also include people who made bulk
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`semiconductor materials, such as silicon or germanium substrates, with no
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`experience working on semiconductor devices.2
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`45.
`
`In my opinion, the category of “semiconductor equipment
`
`manufacturing” is also too broad. This category would include, for example,
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`individuals trained as mechanical engineers, who have no experience with
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`semiconductor devices, only the machinery used to manufacture semiconductor
`
`devices.
`
`46.
`
`I believe my definition is more appropriate, as it requires “working
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`knowledge of semiconductor processing technologies for integrated circuits [and]
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`at least two years of experience in related semiconductor processing analysis,
`
`design, and development.” In my view, the references to integrated circuits and
`
`related processing analysis, design, and development appropriately ties the person
`
`of ordinary skill to the relevant technologies. For example, my definition requires
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`working knowledge and experience with designing, analyzing, and developing
`
`processes for fabricating integrated circuits. One would not be able to perform
`
`those tasks without being familiar with the problems associated with processes for
`
`fabricating integrated circuits.
`
`2 Specialty firms grow large ingots (“boules”) in an industrial furnace, slice them
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`into wafers, polish them, and sell them as substrates. They play no role in device
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`fabrication.
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`47.
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`In addition, I note the default education level the Patent Owner
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`identifies is a Bachelor’s degree in one of many fields, including mechanical
`
`engineering. I cannot agree that a person of ordinary skill in this field would be so
`
`inexperienced and unskilled. I believe a person of ordinary skill in this field would
`
`be suitably trained and properly skilled for the technology.
`
`48.
`
`In my decades of experience in this field, which includes consulting
`
`with industrial professionals and training undergraduate and graduate students, I
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`believe my definition captures the appropriate skill level and training for
`
`understanding the technology at issue in the ’174 patent.
`
`VII. Background Knowledge of a Person of Ordinary Skill in the Art
`Regarding Trench Isolation
`
`49. Trench isolation technology has been known in the art since at least
`
`late 1981, when Kei Kurosawa and his colleagues at Toshiba presented a paper
`
`called, “A New Bird’s-Beak Free Field Isolation Technology for VLSI Devices.”
`
`They called the technique “BOX,” which is short for buried oxide. (Kurosawa at
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`384.) It is also referred to as shallow trench isolation, or “STI.”
`
`50. Although STI methods were further refined over the years as
`
`planarization and other techniques matured, the basic process remained unchanged:
`
`a trench is etched into the substrate, which is filled with an insulator (typically
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`SiO2), and excess portions of the insulator that will not remain part of the trench
`
`isolation are removed. Before filling the trench, an optional trench liner (typically
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`
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