A NEW PLANARIZATION TECHNIQUE, USING A COMBINATION OF RIE
`AND CHEMICAL MECHANICAL POLISH (CMP)
`
`B. Davari, ·C.W. Koburger, R. Schulz, J.D. Warnock, ·T. Furukawa, M. Jost
`
`Y. Taur, ·W.G. Schwittek, ·J.K. DeBrosse, ·M.L. Kerbaugh, J.L. Mauer
`
`IBM Research, T.J. Watson Research center, Yorktown Heights, NY 10598
`
`
`
`• IBM General Technology Division, Essex Junction, Vermont 05452
`
`ABSTRACT
`
`process tolerances. Two distinct features of the CMP,
`
`
`which are: 1) the averaging effect of the removal rate
`
`(polish rate is an average over all the exposed regions), and
`
`2) the fast removal rate of the small elevated features
`
`
`(spikes) are demonstrated and utilized.
`
`RIE + CMP PLANARIZA TION PROCESS
`AND RESULTS
`
`In this paper a new planarization technique for vari
`
`
`able size and pattern factors is presented. It is demon­
`
`strated that by the combination of RIE and Chemical
`
`Mechanical Polish (CMP), the process window is improved
`
`
`to an extent that the planarization becomes a reality. This
`
`technique is applied in the Shallow Trench Isolation (STI,
`(I» process which is used in 16 Mb DRAM technology
`
`
`(2). to achieve 0.5 /Lm isolation/device dimensions .. Bya
`Schematic cross sections of variable size shallow
`
`
`proper combination of RIE and CMP processes, the fun­
`
`
`trench isolation before and after planarization are shown
`
`
`damental problem of tolerance accumulation from deposi
`
`
`in Fig.l. After isolation photo resist definition, the
`
`tion and etch back of large film thicknesses is avoided.
`
`nitride/pad oxide and silicon (trench) are etched, followed
`
`
`Excellent planarization is achieved in different areas of
`
`
`
`by CVD oxide deposition (Fig.la). Subsequently, a block
`
`DRAM chip with varying isolation sizes and pattern fac­
`
`
`resist is patterned over large isolation area (down regions)
`
`
`tors, including the deep trench integration. High gate oxide
`to bring up the surface to about the same level as the active
`
`
`breakdown yield (comparable to LOCOS isolation), which
`area. The block resist is then hardened, followed by
`
`
`is indicative of the planarization low defect density is dem
`
`
`planarizing resist spin and cure (Fig. 1 b). The planarization
`onstrated.
`
`
`that follows must satisfy the following requirements for all
`
`
`isolation pattern factors and sizes (Fig.lc): 1) All oxide
`being cleared from the nitride surface, 2) Greater than zero
`nitride remaining on all active area, and 3) Field oxide sur­
`face being above the silicon surface after planarization
`Planarization is rapidly becoming one of the key
`
`
`(prior to nitride/pad oxide etch). For "RIE only"
`
`
`components in the realization of scaled, high density / high
`
`
`
`planarization, a one-to-one etch (oxide/resist) is used and
`
`performance VLSI circuits.
`
`With lithography advance­
`
`the stack height to be etched back is typically over 1.5
`
`ments into the 0.5 /Lm regime and beyond, planarization is
`
`/Lm. Therefore it is very difficult to achieve better than se
`
`needed to achieve lithography limited dimensions in key
`
`veral 100 nm control of the final oxide thickness, even with
`
`areas such as isolation (1) and metallization.
`
`small process tolerances. Non-idealities of the planarizing
`
`Planarization of the variable size and pattern factor
`resist (Fig. 1 b) due to the resist viscous flow and shrinkage
`
`
`trench isolation, represents one of the most demanding
`
`after cure, and due to variable pattern factors (global effect
`
`process control requirements. The reason is that in the
`
`
`(5),(6» also add directly to the process tolerances. These
`
`
`traditional resist planarization and RIE etch back process
`
`problems can be reduced significantly by using CMP in
`(3) , the deposition
`
`and etch back tolerances associated
`
`conjunction with the RIE etch-back.
`
`
`with large film thicknesses are cumulative. Also, since the
`
`etch rate ratio of the trench fill material and the photoresist
`
`In the RIE+CMP planarization, the RIE etch back is
`
`should be close to one, any non-planarity of the resist is
`followed by CMP. In this process, the RIE is stopped be
`fore removing all the oxide from the nitride surface, in
`
`
`replicated into the final planarized surface and thus adds
`
`directly to the process tolerance.
`
`contrast to the "RIE only" planarization. The remaining
`In this work a new planarization technique, using a
`
`
`
`oxide is then removed by the CMP. This ability widens the
`polish (4) is
`af­
`
`combination of RIE and chemical mechanical
`
`
`planarization window, by allowing some non-planarity
`
`presented which alleviates the above problems. The RIE
`
`
`ter the RIE, which is eliminated by the subsequent polish
`+ CMP is employed in such a manner that inevitable
`
`step. One distinguishing feature of the CMP is that the
`
`
`process non-uniformities in intermediate steps do not op­
`
`removal rate is an average of the rates for the different ex
`
`
`erate cumulatively, as well as reducing the sensitivity to the
`
`removes the posed materials. Therefore as the polishing
`
`
`INTRODUCTION
`
`
`
`CH2/\17·7fR9/0000-0061 S1.00 © 1989 IEEE
`
`IEDM 89 61
`
`3.4.1
`
`Page 1 of 4
`
`TSMC Exhibit 1055
`TSMC v. IP Bridge
`IPR2016-01246
`
`

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`RIE. This spike is caused by the higher etch rate of the
`surface,
`once it reaches the nitride
`oxide over the nitride,
`masking). By increasing
`to the resist (resist
`oxide relative
`the oxide removal rate becomes almost the same as the
`etch rate ratio, the spike height (dimension
`the oxide/resist
`slower than
`is polished
`removal rate, if the nitride
`nitride
`while the dip in the oxide (dimension
`A in Fig.2b) increases
`CMP step, polishes the
`a selective
`the oxide. Therefore
`B in Fig.2b),
`which is caused by the resist non planarity,
`with minimal oxide removal from the
`oxide over the nitride,
`dimension
`For a "RIE only" planarization,
`diminishes.
`A
`of the CMP step to the total proc­
`field. The contribution
`A polish rate ratio of
`negligible.
`is therefore
`ess tolerance
`is used in this work.
`about 5/1 (oxide/nitride)
`of CMP, the RIB can be a
`by the application
`Secondly,
`ending with a step which etches the
`process,
`multi-step
`reduces
`This selectivity
`oxide faster than the photo-resist.
`
`P.R. NON-PLANARITY
`
` (GLOBAL)
`
`NITRIDEI
`PAD OXIDE
`
`(a)
`P.R. NON-PLANARITY
`J, (LOCAL)
`
`
`
`
`-
`LARGE, DENSE ARRAY
`
`\
`/
`
`\
`.. "DETAILED IN FIG. 2
`(b)
`
`
`
`(c)
`
`FIG.1 Variable size Shallow Trench Isolation
`(STI)
`schematic
`cross sections
`(a) After CVD oxide conformal fill
`(b) After block + planarizing resist
`(c) After Planarization
`
`BLOCK
`RESIST
`
`(a)
`
`NITRIDE
`
`SILICON
`
`CVD OXIDE
`
`RESIST
`PLANARIZING
`.. ---- -----
`---' BLOCK
`RESIST
`
`NITRIDE
`
`SILICON
`
`CVD OXIDE
`
`(b)
`
`(c)
`
`to the resist thickness/non planarity,
`the RIE sensitivity
`improves the process window significantly
`and therefore
`cross
`schematic
`below. Process simulated
`as described
`before and after selective RIE
`FIG.2 Cross sections
`before and after the RIE step with selective
`etch
`sections
`area of Fig.lb) are shown in Fig.2a,b.
`In
`(from the circled
`etch rate ratio-3/l)
`step (oxide/resist
`a 3/1 RIE selectivity (oxide/resist)
`is used.
`this simulation,
`(a) Simulated cross section Before RIE
`The SEM cross section of a similar region with the same
`(b) Simulated cross section After RIE
`RIB selectivity
`(c): SEM cross section after selective
`RIE and resist
`is shown in Fig.2c (after the photo resist
`strip). It is shown that there is a spike present after the
`strip
`
`62-IEDM 89
`
`3.4.2
`
`Page 2 of 4
`
`

`

`has to be almost zero and therefore the oxide dip (dimen­
`
`sion B) can be large enough to consume a significant por­
`
`tion of the process window. Possible variations of the
`
`multi step RlE proce" include a first step which removes
`
`the resist very fast (for high throughput), and/or followed
`
`by a one to one oxide/resist etch to insure resist clearance
`from the oxide surface prior to the selective etch.
`
`In the RIE+CMP planarization, the oxide spike
`lFig,2c) is also removed by the CMP. This is due to an­
`other key feature of the CMP, which is the increased polish
`
`
`rate for small elevated features (spikes). This effect is ex­
`
`perimentally demonstrated in Fig.3. A large area oxide step
`(width > IOOl'm) with a height of about 100 nm is super­
`imposed by a small area (width ",4I'm) spike with a height
`of about 300 nm. After 30 sec polish. the height of the
`narrow feature is reduced to about 40 nm (260 nm re­
`moval), while only 20 nm is removed from the large step,
`
`
`Therefore the polishing rate of the small feature in this case
`is more than 10 times faster than in the large area,
`
`3
`
`
`
`
`
`
`
`
`
`A:BEFORE POLISH
`
`30 sec
`B:AFTER
`POLISH
`
`
`
`-I
`o
`
`
`20
`40
`60
`DISTANCE (/Lm)
`FIG.3 Measured oxide step heights before and after
`Chemical Mechanical Polish (CMP), demonstrating
`the fast removal rate of the small elevated features
`(spikes) by CMP
`
`(b)
`FIGA SEM cross sections of STI arrays
`
`(a) After selective RIE, Before CMP
`(b) After CMP
`
`PORTION OF OXIDE REMOVED BY RIE
`FOR RIE+POLISH
`
`The eMP effectiveness in removing the spikes which
`RIE process, in a dense array re­
`are left by the selective
`gion. is shown in FigA. It should be noted that the CMP
`alone (no RlE etch back step) is not a viable planarization
`
`alternative. The reason is the residual oxide which will be
`left in the middle of the large active area or arrays after
`as shown in Fig,S. The oxide which is removed
`polishing,
`solves this problem
`by RIE in the RlE+CMP planarization,
`(Fig.S).
`The final planarization of different regions of a
`chip,
`
`with varying pattern factors and sizes, using RIE+CMP, is
`shown in Fig.G. Excellent planarization
`is achieved in all
`the DRAM array area, demonstrating the
`regions, including
`STI and deep trench integration. Gate oxide breakdown
`field histograms of 4 Mb arrays with STI and LOCOS iso­
`
`lation are shown in Fig.7a,b respectively (each data point
`Each array contains large
`
`represents one complete array)
`STI bounded gate oxide area (0,172854 cm2 ) and perime­
`ter (17.25125 m), The high breakdown yield of the STI
`
`POLISHING I
`
`TIME
`
`RESIDUAL OXIDE
`AFTER POLISHING,
`FOR POLISH ONLY
`PROCESS
`
`CVD
`OXIDE
`
`FIG.S Schematic cross section, demonstrating the
`
`fundamental problem of the "CMP only"
`
`planarization, At the end of polishing (field oxide at
`
`the same level as the nitride surface), residual oxide is
`left in the middle of the active area, The oxide etch in
`
`
`the RIE+CMP planarization eliminates the formation
`of the residual oxide.
`
`3.4.3
`
`I[DM 1'9-63
`
`Page 3 of 4
`
`

`

`with RIE+CMP planarization (comparable to LOCOS
`
`
`
`
`
`isolation) demonstrates very low defect density from this
`process.
`
`CONCLUSION
`
`In summary, a planarization technique, using a com- (a)
`
`
`
`bination of RIE and CMP, is presented for the first time.
`
`
`In this technique, the fundamental problems of independ
`
`
`
`ent RIE and CMP processes are largely avoided, resulting
`
`
`
`in excellent planarization with improved window for vary-
`ing pattern factors and trench sizes. This planarization
`
`
`process is successfully applied to 16 Mb DRAM technology
`(1 ),(2).
`
`ACKNOWLEDGEMENT
`
`The authors wish to thank T.H. Ning, M.R. Polcari,
`
`
`P.E. Bakeman, A.S. Bergendahl, D.L. Critchlow and M.C.
`
`
`Hakey for many helpful discussions and D.V. Horak, H.Y.
`
`
`Ng for processing assistance. They also wish to acknowl
`
`
`edge IBM Yorktown Heights silicon facility and IBM Essex
`
`
`
`Junction TDL personnel for the hardware fabrication.
`
`REFERENCES
`
`120 SHALLOW TRENCH ISOLATION
`>- 100
`(.)
`YIELD (Ebd > 8 MY/cm) - 92%
`z
`w
`315,4MbARRAYSTESTED
`::>
`(a)
`13
`Tox� 12.2nm
`w 50
`a: u.
`
`0
`0 I 2 � 4 5 6 7 8 9 10 II 12 I�
`ELECTRIC FIELD (MV/cm)
`
`FIG.6 SEM cross sections of two regions of a DRAM
`
`
`
`
`chip with different isolation pattern factors and sizes,
`1. B. Davari, et ai, "A Variable Size Shallow Trench Iso­
`
`
`after RIE +CMP planarization
`
`
`
`lation (STI) Technology With Diffused Sidewall Dop­
`(a) Support circuit area
`
`
`ing For Submicron CMOS," IEDM Technical Digest,
`
`(b) Array area, including the deep trench (DT)
`pp.92,1988
`
`2. D.M. Kenney, et ai, "16 Mb Merged Isolation and
`Node Trench SPT Cell (MINT)," 1988 Symp. on
`VLSI Tech., San Diego, CA, pp.25
`3. T. Shibata, et ai, "A Simplified BOX (Buried-Oxide)
`
`
`
`
`Isolation Technology for Megabit Dynamic Memo­
`
`
`
`ries," IEDM Technical Digest, pp.27, 1983
`
`4. A.C. Bonora, "Silicon Wafer Process Technology:
`
`
`
`
`Slicing, Etching, Polishing", Semiconductor Silicon
`
`
`1977, Electrochem. Soc., Pennington, N.J., pp.154
`
`
`5. R.H. Wilson, et ai, "Effect of Circuit Structures on
`
`
`
`Planarization Resist Thickness," J. Electrochem. Soc.,
`VoU33, No.5, pp.981, 1986
`6. T.R. Daubenspeck, et ai, "Planarization of ULSI To
`
`
`
`pography Over Variable Pattern Densities," ECS
`
`Spring mtg. Los Angeles, CA, pp.308, 1989
`
`u.
`
`FIG.7 The gate oxide breakdown field histograms of
`
`
`
`
`
`4Mb arrays (each measurement represents one array)
`
`
`o I 2 3 4 5 6 7 8 9 10 II 12 I�
`
`(a) STI, using RIE+CMP planarization
`ELECTRIC FIELD (MVlcm)
`(b) LOCOS isolation
`
`M IEDM 89
`
`3.4.4
`
`LOCOS ISOLATION
`(Ebd > 8 MY/cm) = 93%
`4Mb ARRAYS TESTED
`12.2nm
`
`�O
`
`>-(.)
`
`
`z 20
`w
`(b) ::> 13
`w a: 10
`
`Page 4 of 4
`
`