`
`
`
`Highly Manufacturable Process Technology for
`
`
`
`
`
`
`
`Reliable 256 Mbit and l Gbit DRAMs
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`H.K. Kang, K.H. Kim, Y.G. Shin, I.S. Park, K.M. Ko, C.G. Kim, K.Y. Oh, S.E. Kim. C.G. Hong. K.W. Kwon,
`J.Y. Yoo, Y.G. Kim, C.G. Lee, W.S. Paick, D.I. Suh, CJ. Park, 8.1. Lee. S.T. Ahn, C.G. Hwang. and MY. Lee
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Semiconductor R&D Center. Samsung Electronics Co., LTD.
`
`
`
`
`
`
`
`
`San #24, Nongseo—Lee, Kiheung-Eup, Yongin-Gun, Kyungki-Do, 449-900, Korea
`
`
`
`
`
`
`
`
`
`Abstract
`
`
`T3205 dielectric on poly-Si cylinder capacitors, Chemical-
`
`
`
`
`
`
`Mechanical Polishing (CMP) planarization, pure W bit-line,
`
`
`
`
`
`
`
`and Al reflow were integrated into a highly manufacturable
`
`
`
`
`
`
`
`
`
`DRAM process technology. This technology provided larger
`
`
`
`
`
`
`
`process margin. higher reliability. and better design
`
`
`
`
`
`
`
`flexibility.
`In addition, the critical steps of the new process
`
`
`
`
`
`
`
`
`
`
`has been reduced by 25% of those of the conventional
`
`
`
`
`
`
`
`
`
`
`process. The manufacturability of the technology has been
`
`
`
`
`
`
`
`
`proven by applying it to 16Mbit density DRAMs with 256
`
`
`
`
`
`
`
`
`
`
`Mbit design rule (0.28 tun).
`
`
`
`
`
`
`
`Introduction
`
`
`As the DRAM generation goes 256 Mbit and beyond,
`
`
`
`
`
`
`
`
`
`the DRAM fabrication process has become more and more
`
`
`
`
`
`
`
`
`
`complicated. This will cause the production cost of the high
`
`
`
`
`
`
`
`
`
`
`density DRAMs unacceptably high and will significantly
`
`
`
`
`
`
`
`degrade the device reliability. Thus, it is essential to develop
`
`
`
`
`
`
`
`
`
`
`a process technology that is simple and yet ensures high
`
`
`
`
`
`
`
`
`
`
`performance and high reliability.
`
`
`
`
`We have developed a highly manufacturable process
`
`
`
`
`
`
`
`technology for 256 Mbit DRAMs and beyond. Process was
`
`
`
`
`
`
`
`
`
`simplified by employing a simple cell structure and
`
`
`
`
`
`
`
`
`
`
`
`
`
`metallizations with less complexity. Photolithography
`margin was significantly improved by realizing a better level
`
`
`
`
`
`
`
`
`of planarization. The main features of this process are Ta205
`
`
`
`
`
`
`
`
`
`
`dielectric on poly-Si cylinder capacitors, CMP planarization,
`
`
`
`
`
`
`
`pure W bit-line, and Al reflow. This technology provided
`
`
`
`
`
`
`
`
`
`larger process margin, higher reliability. and better design
`
`
`
`
`
`
`
`
`flexibility.
`
`
`Cell Architecture
`
`
`Fig. 1 shows a schematic diagram of the DRAM cell we
`
`
`
`
`
`
`
`
`
`
`have implemented. Modified LOCOS isolation, W-polycide
`
`
`
`
`
`
`(WSizlpoly-Si) word-line, and W bit-line were used. Fig. 2
`
`
`
`
`
`
`
`
`
`shows the cross-sectional SEM micrograph of the memory
`
`
`
`
`
`
`
`
`
`cell.
`The KrF eximer laser lithography was used for
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`patterning critical layers. The cell size is about 0.98 pm2
`with 0.28 pm design rule.
`
`
`
`
`
`
`
`
`
`
`
`
`Unit Processes and Their Applications
`A. Ta205 Capacitor
`
`
`
`A CVD T3205 dielectric film of 8.5 nm thickness was
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`deposited on a poly-Si cylinder and followed by 03-plasma
`
`
`
`
`
`
`
`
`treatment and dry-02 annealing. Thermally robust Ta205
`capacitor was realized by forming the TiN/Poly-Si bilayer
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`plate electrode [1]. Fig. 3 shows the capacitance and leakage
`characteristic as a function of the applied voltage. The oxide
`
`
`
`
`
`
`
`
`
`equivalent thiclmess ('I‘oxeq) of 3.5 nm and the capacitance of
`
`
`
`
`
`
`
`
`
`
`30 t'F/cell was obtained. Low leakage current level was
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`maintained even after high temperature thermal cycles of the
`full DRAM process.
`
`
`
`
`B. Low Temperature ILD
`
`
`
`
`
`
`
`
`
`Og-TEOS USG/low temperature planarization replaced
`BPSG/reflow ILD (Inter-Layer Dielectric) to reduce the
`
`
`
`
`
`
`
`thermal budget, which improves device isolation and short
`
`
`
`
`
`
`
`
`channel properties of transistors. CMP achieved a perfect
`
`
`
`
`
`
`
`
`planarization of ILD between word-lines and bit-lines.
`It
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`helped patterning bit-lines without using multilayer
`photoresist, resulting low defect density. Fig. 4 shows W
`
`
`
`
`
`
`
`
`
`
`lines patterned on the polished ILD. Carbon from the organic
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`precursor of U86 and mobile ions from the CMP chemistry
`
`
`
`
`
`
`
`could be potential contaminants. Threshold voltage of
`
`
`
`
`
`
`
`
`transistors, however, was not changed by replacing the
`BPSG/reflow ILD process with organic USG/CMP. Gate
`
`
`
`
`
`
`
`oxide integrity measured by TDDB did not also make much
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`difference between the two groups (Fig. 5).
`
`C. W Bit-Line
`
`
`
`After opening bit-line contacts. about 30 nm thick Ti was
`
`
`
`
`
`
`
`
`
`
`deposited and rapid thermal annealed to form TiSiz on the
`
`
`
`
`
`
`
`
`
`
`
`0—7803—2111-1 $4.00 © 19941EEE
`
`
`
`
`
`
`26.4.1
`
`
`
`Page 1 of 4
`
`IEDM 94—635
`
`
`
`
`TSMC Exhibit 1053
`
`TSMC v. IP Bridge
`IPR2016-01246
`
`Page 1 of 4
`
`TSMC Exhibit 1053
`TSMC v. IP Bridge
`IPR2016-01246
`
`
`
`Discussion
`
`
`Table 1 compares the new process proposed in this paper
`
`
`
`
`
`
`
`
`
`
`
`with a conventional process.
`is well known that
`It
`
`
`
`
`
`
`
`
`deposition and dry—etch processes are the major sources of
`
`
`
`
`
`
`
`
`
`process induced particles and thus determine the device yield.
`
`
`
`
`
`
`
`
`
`
`As shown in Fig. 12, the number of deposition and dry-etch
`
`
`
`
`
`
`
`
`
`
`steps of the new process is 75% of those of the conventional
`
`
`
`
`
`
`
`
`
`
`
`
`process.
`
`This technology can be scaled to the 1 Gbit DRAM
`
`
`
`
`
`
`
`
`
`generation with minor modifications, such as replacing
`
`
`
`
`
`
`
`LOCOS with trench isolation and adding hemispherical—
`
`
`
`
`
`
`grained poly-Si on cylinder capacitors.
`
`
`
`
`
`
`
`
`References
`
`
`[1] KW. Kwon et al., Tech. Dig. of IEDM, 1993, p.53.
`
`
`
`
`
`
`
`
`
`
`
`[2] CS. Park et al., Proc. of VMIC, 1991, p.326.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`5w
`
`ago . gyms; 5__. p“
`
`Fig. 2 Cross-sectional SEM micrograph of the DRAM cell.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`exposed Si surface. The remained Ti, which was not reacted
`with Si. was shipped by wet-etch. Then TiN was deposited
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`to a thickness of 30 nm by reactive sputtering. The TiN
`functions as a barrier metal, that prevents W from reacting
`
`
`
`
`
`
`
`
`
`
`with underlayer, and as a glue layer between W and oxide as
`
`
`
`
`
`
`
`
`
`
`
`well. Finally, about 80 nm of W was deposited by CVD and
`
`
`
`
`
`
`
`
`
`
`
`
`patterned by R113.
`
`
`
`The W bit-line widely extended the design flexibility in
`
`
`
`
`
`
`
`
`the core and periphery areas compared to the conventional W-
`
`
`
`
`
`
`
`
`
`polycide bit-line. This is because the W bit-line has a low
`
`
`
`
`
`
`
`
`
`
`
`sheet resistance and a feasibility of forming contacts to both
`
`
`
`
`
`
`
`
`
`N+ and P+ diffusion. As shown in Fig. 6(a), a thinner W
`
`
`
`
`
`
`
`
`
`
`
`
`
`bit-line has about one-quarter of sheet resistance of the thicker
`
`
`
`
`
`
`
`
`
`W-polycide. By the TiSi; salicidation on the active area and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`on the poly-Si landing pads before W bit-line deposition. all
`the bit—line contacts became low resistance metal-to-metal
`
`
`
`
`
`
`
`contacts. As a result, bit-line contacts have much lower
`
`
`
`
`
`
`
`
`
`resistance than that of W-polycide (Fig. 6 (b)-(d)).
`
`
`
`
`
`
`
`
`D. Reflowed Al
`
`
`
`Fig. 7 shows the first level interconnection with contact
`
`
`
`
`
`
`
`
`
`holes filled by Al reflow. Ti/I‘iN was used as the barrier
`
`
`
`
`
`
`
`
`
`
`
`metal. Overhang-free. conformal deposition profile at the
`
`
`
`
`
`
`
`contacts enhanced electromigration and stressmigration
`
`
`
`
`
`
`
`
`
`
`
`
`resistance [2] compared to the conventional Al deposition.
`
`Fig. 8 compares the surface roughness of non-reflowed and
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`reflowed Al after forming gas anneal. High density of
`hillocks are observed on the non—reflowed surface. while
`
`
`
`
`
`
`
`
`almost none on the reflowed surface.
`It eliminated short-
`
`
`
`
`
`
`
`
`circuit failures between the first and the second metal lines.
`
`
`
`
`
`
`
`
`
`
`
`CMOS Transistor Performance
`
`
`
`LDD structure was used for both N— and P—channel MOS
`
`
`
`
`
`
`
`
`
`transistors. Transistors show satisfactory characteristics as
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`summarized in Fig. 9. Thanks to the low thermal budget (65
`minutes at 850°C equivalent) achieved by employing a low
`
`
`
`
`
`
`
`
`temperature ILD, the threshold voltage P-channel transistors
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`vary less than 0.1 volt in the range of 0.3-3.0 tun gate length
`(Fig. 10).
`
`
`
`DRAM Performance
`
`
`Fully working 16 Mbit DRAM with 256 Mbit density
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`was obtained by applying this technology. Fig. 11 shows
`the measured output wave forms of the fabricated 16 Mbit
`
`
`
`
`
`
`
`
`
`
`DRAM. The typical RAS access time is 48 ns.
`
`
`
`
`
`
`
`
`
`
`26.4.2
`
`
`
`636—IEDM 94
`
`
`
`
`Page 2 of 4
`
`Page 2 of 4
`
`
`
`
`
`
`
`
`
`1 [3-9
`
`
`
` ’=‘
`
`Positive
`
`
`
`
`
`Voltage (V)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`%
`
`0
`
`i “5'11
`E
`
`a:
`
`g 1E-13
`0
`
`8:
`
`% 1E—15
`
`Q)
`4 1E 17
`'
`
`
`
`
`
`
`
`
`
`(a)
`
`
`
`
`8
`
`E
`
`v
`a)
`
`
`g
`
`,5
`
`en
`g
`
`
`
`
`
`
`
`
`
`
`
`
`
`(b)
`
`0
`
`4.5
`
`
`
`-1
`
`
`
`
`
`
`
`
`.05 o
`
`
`
`Voltage (V)
`
`0.5
`
`
`
`
`
`
`1
`
`
`
`1.5
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Fig. 3 (a) Capacitance and (b) leakage characteristics of T220, single cylinder capacitor as a function of applied
`
`
`
`
`
`
`
`voltage. Net capacitor area is about 3.2 umzlcell.
`
`1oo
`
`.
`A BPSG/FIEFLOW
`
`o USG/CM?
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Failure(%) 8 1
`
`
`
`
`
`
`
`
`
`
`Fig. 4 Tungsten bit—line patterned on apolished USG
`
`
`
`
`
`
`
`
`
`surface. Bit—lines were RIE etched with a single layer
`
`
`photoresist mask.
`
`
`
`
`_
`1o
`100
`
`
`
`Stress tlme(sec)
`
`
`
`
`
`
`
`
`Fig. 5 Comparison of the gate oxide TDDB
`
`
`
`
`
`
`
`characteristics of (a) BPSG-t‘lowed and (b) USG
`
`
`
`
`
`
`
`
`polished samples. Gate oxide thickness is 8 nm.
`
`
`
`
`
`
`Stress current density is about 50 mA/cmz.
`
`
`1000
`
`
`
`
`
`
`
`
`
`
`
`contact size-0.3103 ,tm'
`-
`.
`
`
`
`
`
`
`
`
`
`coated uiz—naxoa .tm‘
`u a
`
`
`
`
`contact size-0.3103 ,tm’
`1
`
`
`x
`
`
`
`
`
`
`.
`.
`
`
`
`
`
`
`
`
`
`
`o
`a
`BR-IindNo
`Bli-Iina/Gale
`Bt-indLanding Pad
`Shoot Resistance
`
`
`
`
`
`
`160
`200
`120
`80
`40
`1000
`10000
`100
`3
`600 300 1000
`200 400
`T
`6
`4
`5
`B
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Cantata Reel-tattoqohnmn)
`Cantata Rosttaneqohmatt)
`Contact Resistaneqohmlmt)
`Resistance(ohm/em2)
`
`
`
`
`
`(C)
`(b)
`(d)
`(a)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Fig. 6 Comparisons of W and W-polycidc: (a) bit-line sheet resistance, (b) bit-line/tungsten policide gate, (c) bit-
`
`line/N+ substrate, and (d) bit-line/landing pad contact resistace. Thickness of tungsten is 80nm while tungsten
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`silicide/poly Si is 150/50nm.
`
`
`
`
`
`f
`0
`
`‘
`x
`
`‘
`I
`
`
`
`
`
`
`
`
`
`
`
`10
`
`9
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`O
`
`v
`.
`
`0
`
`
`
`
`
`
`
`
`.
`
`’l
`
`2
`
`
`
`ml9ww
`
`
`
`
`
`50
`
`A
`2';
`E
`'5
`
`g
`0
`
`
`E'
`
`.01
`
`
`
`26.4.3
`
`
`
`IEDM 94—637
`
`
`
`
`Page 3 of 4
`
`Page 3 of 4
`
`
`
`
`
`
`
`
`
`
`
`500I0
`
`1500
`
`
`
`
`
`
`
`0M
`
`
`0
`
`
`
`
`
`
`
`
`
`
`
`
`0
`
`1 000
`500
`1 000
`500
`
`
`
`
`
`Length ( um )
`Length ( um )
`
`(b)
`(a)
`
`
`
`
`Fig. 8 Comparison of the hillock density on (a) non—reflowcd and
`
`
`
`
`
`
`
`
`(b) reflowed Al alloy surfaces. Surface roughness was measured
`
`
`
`
`
`
`
`
`by surface profiler after forming gas anneal at 450°C for 30 min.
`
`
`
`
`
`
`
`
`
`
`
`
`0.0
`
`
`
`_
`_
`
`
`
`
`
`
`
`
`Fig- 7 Cross-secuonal 35M 0f 3“ A1 alloy 11113
`
`
`
`
`
`formed by the “flow Process‘
`
`
`
`15-03
`
`
`
`
`E
`
`
`
`a g
`
`
`
`
`
`
`
`
`
`
`
`
`0.0
`
`Vds(V)
`
`
`
`
`
`
`-o.2
`
`-o.4
`
`-0.6
`-0.8
`
`Vth(V)
`
`i
`
`
`
`
`
`
`
`
`
`
`
`
`the
`Fig. 9 (a) Ids-Vds and (b) Ids-Vgs characteristics of Nwhannel (W=10um, Fig.
`10 Variation of
`
`
`
`
`
`
`
`
`
`
`
`
`
`L=0.4um) and P-channcl (W=10um, L=0.4um) MOS transistors. Vgs was varied
`threshold voltage of P-channel
`
`
`
`
`
`
`from 0 to 2.5V for Ids-Vds curve. Vds =0.1V for lds-Vgs curve.
`MOS transistors as a function of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`gate length.
`
`
`
`0.0
`
`
`Vgs(V)
`
`2.5 4'30
`
`3.0
`2.0
`1.0
`Gate Length(pm)
`
`Table 1. Comparison of process steps between a
`
`
`
`
`
`
`
`
`conventional process and the new process.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`mm‘ w
`
`4
`
`
`
`
`
`-muw ,
`
`
`
`
`
`
`Fig. 11 Measured output wave forms of the 16M
`
`
`
`
`
`
`
`
`DRAM.
`
` deposition
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Number of Steps
`
`
`
`
`
`
`
`
`
`
`
`
`Fig. 12 Number of deposition and dry—etch steps of a conventional process and the new process.
`
`
`
`
`
`
`
`
`
`
`
`
`25.4.4
`
`
`
`638-—IEDM 94
`
`
`
`
`Page 4 of 4
`
`Page 4 of 4
`
`