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`A NEW BIRD‘S—BEAK FREE FIELD
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`ISOLATION TECHNOLOGY FOR VLSI DEVICES
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`Kai KUROSAWA, Tadashi SHIBATA and Hisakazu IIZUKA
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`Toshiba Research and Development Center,
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`Toshiba Corporation, Kawasaki, Japan
`is described in detail and the electrical
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`characteristics of test devices fabricated
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`by BOX are discussed.
`BOX TECHNOLOGY
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`ABSTRUCT
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`A new field isolation technology ide-
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`al for VLSI devices has been developed
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`incorporating a unique two step oxide—
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`burying process. This technology is com-
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`pletely free from bird's beak formation
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`which is particularly important for in-
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`creasing the packing density.
`A near-
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`perfect planar surface structure is also
`obtained.
`MOS devices fabricated by the
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`new technology showed no thershold voltage
`increase due to the narrow channel effect
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`for channel widths down to submicron
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`region.
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`The fabrication process of BOX is
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`schematically outlined in Fig. 2.
`The
`active device areas on silicon wafer (P-
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`type, 50 Gem) were covered with aluminum
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`patterns,
`followed by the etching of sili-
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`geac-
`con substrates in the field region.
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`tive ion Etching (RTE) employing CFr gas
`(21 cc/min) was used for the silicon etch-
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`ing. Borons were implanted using the
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`aluminum patterns as masks.
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`These grooves were completely filled
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`up with SiOz using the following two step
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`oxide-burying technique.
`In the first
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`oxide burying step, plasma-deposited SiOz
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`was roughly filled into the engraved field
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`region by the lift—off technique,
`leaving
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`V-shaped grooves in the periphery.
`In the
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`lift-off technique, we used the preferen—
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`tial etching characteristics of plasma
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`deposited SiOz to buffered HF solution
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`occuring at steep side walls.
`The SEM
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`picture in Fig.
`2 demonstrates the prefer-
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`ential etching of plasma deposited Si02
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`which occured at edges of the active
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`region.
`As is clearly seen in the pic-
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`ture,
`the SiOz is completely removed from
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`the steep side walls.
`Then the SiOz on
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`top of aluminum mask was lifted-off by
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`etching the aluminum mask.
`The boiling
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`in H202 + H280“
`(1:3) solution was employ-
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`ed for the etching of aluminum.
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`The remaining V shaped grooves were
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`For
`buried with SiOz in the second step.
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`burying SiOz into the V-grooves, surface
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`levelling technique using spin-coated re—
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`sist was utilized after the deposition of
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`CVD SiOz.
`The resist and CVD SiOz layers
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`were simultaneously etched by RTE with
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`equal etching rates for resist and SiOz.
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`the
`After smoothing the oxide surfaces,
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`remaining oxide on the active device re-
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`gion was removed by solution etching.
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`After oxide—burying processes were
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`completed,
`test devices were fabricated
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`using a conventional n-channel MOS tech—
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`nology.
`For comparision,
`test devices
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`were also fabricated by conventional LOCOS
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`process using the same set of masks.
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`INTRODUCTION
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`The field isolation of device on sil—
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`icon substrate is one of the most
`impor-
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`tant process steps in the fabrication of
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`integrated circuits.
`The widely-known
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`LOCOS process(l) which uses silicon ni—
`tride as masks for selective oxidation has
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`revealed several disadvantages as a proc—
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`ess for future VLSI fabrication.
`The lat-
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`eral oxidation under the nitride masks, for
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`instance, creates so—called brid's beak,(2)
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`resulting in a considerable reduction of
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`packing densit
`Process—induced crystal-
`.
`line defects(3¥ and gate oxide failures
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`due to “white ribbon”,(4) both of which
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`are associated with the LOCOS process,
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`represent a difficult barrier for the de—
`velopment of VLSI devices.
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`The purpose of this paper is to pre-
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`sent
`the newly developed field isolation
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`technology which overcomes these diffi-
`culties.
`Since isolation is achieved by
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`burying oxide into etched grooves formed
`in silicon substrates,
`the technology is
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`called "BOX".(5)
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`the grooves in
`In the BOX process,
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`the field region is completely filled up
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`with SiOz using a two step oxide buring
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`process.
`Since silicon substrates are not
`oxidized to form field oxide,
`the bird's
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`beak length is exactly zero. This is par-
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`ticularly important for the density im-
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`provements of VLSI.
`The BOX structure is
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`further characterized by its near-perfect
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`planar surface which is also essential for
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`fine patterning and high—reliability met-
`allization.
`In this paper,
`the BOX process
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`384——1EDN181
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`Page 1 of 4
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`16.4
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`
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`CH1708-7/81/0000—0384 $00.75 © 1981 IEEE
`
`
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`
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`TSMC Exhibit 1052
`
`TSMC v. IP Bridge
`IPR2016-01246
`
`Page 1 of 4
`
`TSMC Exhibit 1052
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

`RESULTS AND DISCUSSION
`
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`
`SUMMARY
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`The new field isolation technology,
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`BOX has been described. This process is
`
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`completely free from bird's beak formation,
`
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`which is essential for high device density.
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`According to the simple estimation of dy—
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`namic memory cell density,(7) BOX achieves
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`an 80% density improvement as compared to
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`the LOCOS under 1.0 pm layout rules. Near-
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`planar topography is also obtained. This
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`is very important for fine patterning and
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`high reliability of metallization.
`Fur-
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`thermore,
`transistors fabricated by BOX
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`show no threshold voltage increase for
`channel widths even below 1 pm.
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`ACKNOWLEDGMENT
`
`The authors would like to thank
`
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`T. Moriya, R. Hazuki and K. Taniguchi for
`
`
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`their helpful suggestions.
`REFERENCE
`
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`
`
`
`
`
`(1) J. A. Appels and M. M. Paffen, Philips.
`
`
`
`
`
`Res. Rep., gg 157 (1971)
`'
`
`
`
`
`
`
`(2) E. Bassous, H. N. Yu and V. Maniscalco,
`
`
`
`
`
`J. Electrochem. Soc., lgg, 1729 (1976).
`
`
`
`
`
`
`
`(3) K. Shibata and K. Taniguchi, J. Elec—
`
`
`
`
`
`trochem. Soc., lg; 1383 (1980).
`
`
`
`
`
`
`
`
`(4) E. Kooi, J. G. Van Lierop and
`
`
`
`
`
`J. A. Appels, J. Electrochem. Soc.,
`
`
`
`lg;, 1117 (1976).
`Iizuka,
`(5) K. Kurosawa, T. Shibata and H.
`
`
`
`
`
`
`39th Device Research Conference, Santa
`
`
`
`
`
`Barbara, June (1981).
`
`
`
`(6) K. Kurosawa, Y. Horiike, H. Okano and
`
`
`
`
`
`
`
`
`
`
`
`
`
`K. Okumura, Proceedings of the 2nd
`
`
`
`
`Simposium on Dry Processes cosponsored
`
`
`
`
`
`
`
`by The IEE of Japan, P43 (1980).
`
`
`
`
`
`
`
`
`(7) T. Shibata, H.
`Iizuka and S. Kohyama,
`
`
`
`
`
`Int. Electron Devices Meeting, Dig.
`
`
`
`
`Tech. Paper, PP177-180 (1978).
`
`
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`
`Figure 3 shows the current—voltage
`characteristics of test transistors fabri—
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`
`
`cated by LOCOS and BOX. Cross sectional
`
`
`
`
`
`
`views of the transistors along the channel
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`Width direction are also shown by SEM pic-
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`
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`tures.
`As is clearly seen in the figure,
`a submicron transistor with a channel
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`
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`width exactly equal
`to the mask dimension
`
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`
`
`(0.9 pm)
`is realized by BOX technology.
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`While the transistors fabricated by LOCOS
`
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`have collapsed due to the bird's beak when
`the channel width are smaller than 1 pm on
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`the mask.
`In the optimized LOCOS the
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`bird's beak length is minimized to about
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`0.5 um.(6)
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`Figure 4 shows the threshold voltage
`as a function of the channel width defined
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`by mask.
`The threshold voltage of LOCOS
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`samples increases significantly when the
`channel width is reduced below 2 pm. This
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`threshold increase is a result of the nar-
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`row channel effect which is further en—
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`hanced by the bird's beak and the lateral
`diffusion of field borons.
`On the other—
`
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`in the case of BOX sample, the
`hand,
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`
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`threshold voltage is almost constant for
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`channel widths down to submicorn region.
`
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`Figure 5 shows reverse current-volt-
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`age characteristics of p-n junction diode.
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`It is clearly seen in the figure that the
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`reversa current level of the BOX sample is
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`as low as that of the LOCOS sample.
`In
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`LOCOS sample,
`the degradation in reverse
`characteristics is often observed caused
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`by the crystalline defects induced in the
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`periphery of field oxide.
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`Figure 6 shows the field boron dose
`
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`
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`dependence of the field inversion voltage.
`
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`It indicates that about one order of mag-
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`nitude larger dose is required for LOCOS
`
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`since the implanted borons are lost into
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`field oxide during field oxidation.
`One of the difficulties associated
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`with the BOX structure is a parasitic
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`channel formation occuring at the side
`walls of silicon. This results in a chan-
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`leakage current of the order of ~lO'GA.
`nel
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`One example of the degraded subthreshold
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`characteristics is demonstrated in Fig. 7.
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`The leakage current appears as a hump su-
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`perimposed on the subthreshold character-
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`istics of the transistor. As is clearly
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`seen in the figure,
`this effect has been
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`successfully eliminated by the side wall
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`boron implantation.
`The boron implanta-
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`tion to the side walls near perpendicular
`to the wafer surface has been carried out
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`in the following way. Borons of ~1013 cm‘2
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`implanted to the field region prior to the
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`formation of grooves in silicon substrates.
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`The lateral penetration of implanted bo—
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`rons due to the ion Straggle introduced
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`enough amount of impurities in the sub-
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`strate under the aluminum mask which pre-
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`vented the paracitic channel formation at
`the side walls.
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`16.4
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`
`
`IEDM 81 — 385
`
`
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`
`Page 2 of 4
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`Page 2 of 4
`
`

`

`
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`
`
`Isf Oxwe Burwng Step
`
`Aluminum
`
`
`Sioz
`Implanted
`Region
`31 Wafer
`
`
`
`
`
`
`LOCOS
`BOX
`
`.
`Plasma 5102 I
`
`
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`
`
`Aluminum ”
`
`
`
`
`Fig. 2.
`
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`
`
`The SEM picture which explains
`
`
`
`
`The
`the lst oxide-burying step.
`
`
`
`
`plasma—deposited SiOz on steep
`
`
`
`
`side walls is preferentially
`etched by buffered HF solution.
`
`
`
`
`
`
`
`
`smd
`-d
`PI
`sfiira epo'
`
`
`
`
`(After Buffered HF Etching)
`
`V Grooves
`
`I
`‘
`2nd Oxme BWymg smp
`
`Resist
`
`
`CVD SiOg
`
`
`Field SiOg
`
`
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`
`
`Fig. 1. Fabrication process steps of BOX.
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`Fig. 3. Current—voltage characteristics of transistors fabricated by LOCOS and BOX.
`
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`
`In the case of LOCOS,
`the active device area has disappeared due to the bird's
`
`
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`
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`
`
`
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`beak, while BOX realizes a transistor with identical dimensions to the mask.
`
`
`
`386——IEDR481
`
`
`
`Page 3 of 4
`
`16.4
`
`
`
`Page 3 of 4
`
`

`

`
`
`
`
`1o12
`
`10“"
`
`
`
`Field Boron Dose
`
`
`
`1o“
`
`(cafe)
`
`
`
`100
`
`
`
`E
`
`2+
`
`:6 1o
`
`v
`
`2:5
`8
`L
`i
`
`
`
`
`
`1
`
`
`
`
`
`
`
`
`Fig. 6. Field inversion voltage as a
`function of field boron dose.
`
`
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`
`
`length of the field tran—
`Channel
`
`
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`sistors is 20 um.
`
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`
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`
`
`/' /
`
`' //
`
`
`SIDE-WALL
`/ IMPLANTED
`
`
`
`1.5
`
`
`
`
`5
`
`w "0
`3t
`
`
`
`§
`t,
`_
`
`g05
`‘s‘.’
`
`If
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`CHANNEL LENGTH =4,um
`
`%=
`5v
`
`Vsua : 0V
`
`
`
`0
`
`0
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`I
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`2
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`4
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`3
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`Chmmd wmrh deedby Mask
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`(#m)
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`Fig. 4. Threshold voltage as a function of
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`channel width defined by the mask.
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`Negligible narrow channel effects
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`are seen in BOX samples.
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`Diode size ; 200x500 (pmz)
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`) g
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`5
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`3
`S
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`2%
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`E
`o
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`w
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`g
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`“
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`Reverse Bias Volfoge
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`(Vol?)
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`E
`LL]
`E
`DU
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`z
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`<
`0:
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`G
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`10
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`0
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`05
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`GATE VOLTAGE(V)
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`1,0
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`1.5
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`NON SIDE-
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`WALL
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`IMPLAN' -
`TED
`/
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`SOURCE
`SIDE WALL
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`Fig. 5. Reverse current-voltage charac-
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`teristics of p-n junction diode.
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`Page 4 of 4
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`Fig. 7.
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`Subthreshold characteristics of a
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`transistor with W/L=20 um/3 um.
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`(Vsub=OV, VD=5 V.) Parasitic
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`channel formation occuring at the
`side-walls of silicon results in
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`a increased leakage current of
`the order of lO'GA.
`The side-wall
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`boron implantation successfully
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`eliminated the leakage current.
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`16.4
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`IEDM 81 — 387
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`Page 4 of 4
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