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`Microscopy needs for next generation devices characterization in the semiconductor industry
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`2011 J. Phys.: Conf. Ser. 326 012008
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`(http://iopscience.iop.org/1742-6596/326/1/012008)
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`Defect analysis of a silicon nanowire transistor by X-ray energy dispersive spectroscopy technique
`in a STEM: 2D mappings and tomography
`K Lepinay, F Lorut, A Pofelski et al.
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`STEM EDX applications for arsenic dopant mapping in nanometer scale silicon devices
`G Servanton, R Pantel, M Juhel et al.
`
`Characterization of stress transmission from silicon nitride layer to transistor channel
`R Thomas, D Benoit, L Clement et al.
`
`Off-axis electron holography for the measurement of active dopants in silicon semiconductor devices
`David Cooper
`
`Field mapping of focused ion beam prepared semiconductor devices by off-axis and dark field
`electron holography
`David Cooper, Pierrette Rivallin, Georges Guegan et al.
`
`Advanced TEM Characterization for the Development of 28-14nm nodes based on fully-depleted
`Silicon-on-Insulator Technology
`G Servanton, L Clement, K Lepinay et al.
`
`Aberration-corrected STEM and EELS of semiconducting nanostructures
`K Cui, S Hosseini Vajargah, S Y Woo et al.
`
`Electron tomography of gate-all-around nanowire transistors
`P D Cherns, F Lorut, C Dupré et al.
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`Page 1 of 15
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`Microscopy needs for next generation devices characterization
`in the semiconductor industry
`
`L Clement1, C Borowiak1, R Galand1, K Lepinay1, F Lorut1, R Pantel1,
`G Servanton1, R Thomas1, P Vannier1 and N Bicais1
`1 STMicroelectronics, 850 rue Jean Monnet, F-38926 Crolles, France
`
`Email : laurent-renaud.clement@st.com
`
`Abstract. In this paper we present the different imaging based techniques used in the
`semiconductor
`industry
`to
`support both manufacturing and R&D platforms at
`STMicroelectronics. Focus is on fully processed devices characterization from large structure
`(3DI, Imager sensors) to advanced MOS technologies (28-20 nm). Classical SEM and TEM
`(mainly EFTEM) based techniques are now commonly used to characterize each step of the
`semiconductor devices’ process flow in terms of morphology and chemical analysis. However
`to address specific issues, dedicated imaging techniques are currently being investigated. With
`the “High-k Metal Gate” stack involved in the more advanced MOS devices (28-20 nm), new
`challenges occur and therefore advanced characterization is mandatory. Some relevant
`examples are pointed out through (STEM) EELS and EDX experiments. Analysis of stressors
`mainly used to improve carrier mobility in next generation devices, is also presented with
`different approaches (NBD, CBED and Dark-field holography). Advanced STEM and AFM
`based techniques applied to characterize dopants and junction in MOS devices and also in more
`relaxed structure such as imager sensors is discussed too. Concerning back-end (interconnects)
`and 3D integration (3DI) issues, focus is on nano-characterization of defects by classical
`techniques (EFTEM, STEM EELS-EDX) and with dedicated ones still in development. To
`illustrate this topic some 3D FIB/SEM and E-beam tomography experiments are presented.
`Examples of microstructure and texture determination in poly-crystalline materials such as
`copper line by coupling SEM/EBSD and TEM techniques are also shown.
`
`1. Introduction
`Scanning and Transmission Electron Microscopy (SEM and TEM) coupled with Focused Ion Beam
`(FIB) are essential techniques to ensure the process development of future devices in the
`semiconductor industry. At STMicroelectronics Crolles, these tools are now commonly used to
`support both Manufacturing (200 mm and 300 mm fabs) and R&D platforms. In this industrial context
`with fast process evolution, large numbers of sites have to be analyzed with short turn-around-times
`(TAT) but new and innovative characterization techniques have also to be run up.
`Nowadays, physical characterization faces some challenges: on the one hand, analysis of very
`small scale defects and features with the highest resolution (at nanometer and atomic scales) is
`required. Furthermore, in parallel with this miniaturization, new smart structures and complex
`materials are incorporated into devices. Also new transistor architectures that have appeared during the
`last years extended the classical “Moore” law towards the “More Moore” concept.
`
`1 To whom any correspondence should be addressed.
`
`IOP Publishing
`17th International Conference on Microscopy of Semiconducting Materials 2011
`Journal of Physics: Conference Series 326 (2011) 012008
`doi:10.1088/1742-6596/326/1/012008
`
`Published under licence by IOP Publishing Ltd
`
`1
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`Page 2 of 15
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`On the other hand, the functional diversification of semiconductorfunctional diversification of semiconductor-based devices based devices for derivative
`
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`applications have also emerged, designeddesigned as “More than Moore” approach. In this case, more relaxed . In this case, more relaxed
`
`
`structures (like 70x70 µm Through Silicon Vias (like 70x70 µm Through Silicon Via (TSV), copper pillars, objects in 3D chips i3D chips integration
`
`
`(3DI) scheme, imager sensors or MEMSMEMS…) have also to be characterized with dedicated to be characterized with dedicated techniques or
`tools.
`
`
`2. Down-scaling of CMOS transistors scaling of CMOS transistors in the “More Moore” approach
`
`
`Following the “Moore law”, device shrinkinge shrinking has continued for forty years from micrometric nominal has continued for forty years from micrometric nominal
`
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`dimension to about 40 nm. This was possible without great innovation of the dimension to about 40 nm. This was possible without great innovation of the CMOS architectureMOS architecture
`node and beyond based on Si/Si02/poly-Si stack. Downown-scaling of CMOS transistors for the 32/28 nm node and beyond
`
`
`
`
`now needs the introduction of new materials in the devices process’ flow. the introduction of new materials in the devices process’ flow. For instanceFor instance, concerning
`
`
`MOS gate, the implementation of a Hithe implementation of a High-k (HK) dielectric with a metal gate (MG) stack(HK) dielectric with a metal gate (MG) stack is now
`
`
`required for advanced technology. . Moreover, atomic mono-layers (known as capping layers in the layers (known as capping layers in the
`
`
`“gate first” approach) of specific elements are used to tune the metal work function for N and PMOS “gate first” approach) of specific elements are used to tune the metal work function for N and PMOS “gate first” approach) of specific elements are used to tune the metal work function for N and PMOS
`
`
`transistor. Regarding backend (BE) flowbackend (BE) flow, some impurities as aluminium (Al) or cobalt (Co) have to be obalt (Co) have to be
`
`
`added in copper (Cu) metal lines to limit copper (Cu) metal lines to limit electromigration phenomenon in interconnects in interconnects and therefore
`ensure reliability of the chips.
`
`
`So, new challenges have occurredoccurred and manufacturing processing have raised a need for manufacturing processing have raised a need for
`
`
`development of advanced characterization techcharacterization techniques to address specific issues like HKMG, silicide, issues like HKMG, silicide,
`
`
`dopants profiling, stressors and interconnects characterizadopants profiling, stressors and interconnects characterization as described in the following n as described in the following
`paragraphs.
`
`
`2.1. High-k Metal Gate (HKMG) and(HKMG) and silicide characterization
`
`
`The solution chosen for the 28 nm technology developed at the Itechnology developed at the IBM Fishkill ISDA alliance (in whichBM Fishkill ISDA alliance (in which
`
`
`STMicroelectronics is a partner) is to incorporate: lpartner) is to incorporate: lanthanum (La) for NMOS and aluminiumluminium (Al) for
`
`
`PMOS at the metal (TiN)/High-k (HfSiON(HfSiON) interface. The quantitative measurement of the initial La ) interface. The quantitative measurement of the initial La
`
`and Al doses (about one monolayer) and their post anneal diffusion observation and Al doses (about one monolayer) and their post anneal diffusion observation is is crucial for the
`
`
`
`process development. These analyses These analyses thus require atomic resolution which fortunately is available atomic resolution which fortunately is available in
`
`
`the TEM Cs corrected microscopes. Figure 1 presents HRSTEM images of a Si/SiON/HfSiON/La/TiNthe TEM Cs corrected microscopes. Figure 1 presents HRSTEM images of a Si/SiON/HfSiON/La/TiNthe TEM Cs corrected microscopes. Figure 1 presents HRSTEM images of a Si/SiON/HfSiON/La/TiN
`
`
`(gate) stack before and after 1050° C RTP annealing. The observations were carried out using the stack before and after 1050° C RTP annealing. The observations were carried out using the stack before and after 1050° C RTP annealing. The observations were carried out using the
`
`
`MINATEC’s TITAN microscope MINATEC’s TITAN microscope integrating a Cs probe corrector (CEOS Company). The OS Company). The
`
`
`combination of bright field (BF) STEM STEM image (blue), with dark field (DF) HAADF image (red), HAADF image (red),
`
`
`highlights the heavy and light elements distribution. It is shown that the annealing process induces highlights the heavy and light elements distribution. It is shown that the annealing process induces highlights the heavy and light elements distribution. It is shown that the annealing process induces
`
`diffusion and modification of the bottom SiON/diffusion and modification of the bottom SiON/HfSiON interface.
`
`
`
`
`
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`Figure 1. HRSTEM images combining HAADF signal (red) with Bright Field detector signal HRSTEM images combining HAADF signal (red) with Bright Field detector signal HRSTEM images combining HAADF signal (red) with Bright Field detector signal
`
`
`(blue): a) before annealing, b) after 1050°C RTP annealing. (TITAN after 1050°C RTP annealing. (TITAN 200 keV probe Cs correctprobe Cs corrected at
`
`CEA Grenoble-LETI MINATEC). ).
`
`
`
`IOP Publishing
`17th International Conference on Microscopy of Semiconducting Materials 2011
`Journal of Physics: Conference Series 326 (2011) 012008
`doi:10.1088/1742-6596/326/1/012008
`
`2
`
`Page 3 of 15
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`

`

`17th International Conference on Microscopy of Semiconducting Materials 2011
`
`IOP Publishing
`
`Journal of Physics: Conference Series 326 (2011) 012008
`
`doi:10.1088/1742-6596/326/1/012008
`
`es
`
`,
`
`EDX detectors,
`rc
`i h b
`na yi a T]
`During the last yea
`echniques. Fast
`p
`t
`fast EELS spectrometers) have drastically improved h
`ics have now a
`icroelect
`chemical mapping with sub- a ometre resolution is
`righ brightness
`d anc s
`l
`h
`FEI TECNAI-Osiris o
`r01 5
`:ite. W
`n
`electr n sou ce (XFEG). fou
`'D windowless EDX detectors giving 0.9 srad ollection angle
`(SuperX), and a
`a
`n
`EELS spectrometer [1]. Large EELS a
`ED
`rectmm images
`can 11 w be acqu re in
`hort
`ime using an electron probe with a small diameter (~03 nm) and a
`high beam current (1 nA). Fi
`re
`11
`S E
`m g o
`c 055 5
`tion ofa 28 nm
`SRAM b t ell er s
`cti n.
`STEM-EELS
`(
`o a 11
`using the Osiris TEM at 120
`keV. howst e
`.
`a a d
`elemental distributions att
`t
`o N
`ate The lanthanum
`
`ST
`s
`
`tr n ai
`05 v
`ie 0 top fthe
`the Si N/HfSiON ho to
`nt r c :. This lanthanum difl‘usion creating a
`o
`SiON interface is beneficial f
`he optimisation of the NMOS threshold voltage.
`
`a distributednear
`l y r at the High-kl
`
`S'l'l-I‘l Il-\:\Dl5
`
`\“l F“ FFI \ —*
`
`
`
`bt
`S
`0
`se
`a
`A D ima
`Figure 2.
`STEM-EELS map pr sent
`t Hf, La and Si distributions. (TEM Osiris at 120 keV).
`
`the right top a
`
`2 nm technology
`s
`. ni k 1 Si icide containing platinum (NiSiPt)
`gu
`i
`As is sho
`omalous nickel
`at gate. 0 Ice 11 d i
`eve. Past studies for 40 nm technology h ve
`silicide grth [2] can induce l c ric failure. In order to diminish this efl‘ect for a va :ed technology,
`th p ati um conc rati n nsi
`he Ni target is increased (10 at % instead of 5 at %). However the
`f this higher Pt concentrati(
`ki e
`s o
`.
`di ri
`tion of dopants
`and plat num must b stu ied i
`de real devices. Figure 3 presents STEM-
`Ips of a 28 nm
`NMOS ra sist r h win
`i
`rticular Ni, Pt and As distributions. The p tnum is poorly
`r
`hNi
`aAs o
`r
`c
`eainrfces.Thisshows
`
`f
`
`e
`
`th t the an ealing steps are no if cient for the Pt incorporation inside t e NiS
`shows
`E X p 0 a1 ser
`i
`)
`e at
`in or orated in ide he iic de particularly at grain boundaries. The a
`n
`NiSiPt outs des inter c s.
`h
`confirms that
`laser annealing is
`technologies. but
`I
`e s v
`1
`i w
`e
`in
`er 0 a i
`
`e. Figure 4 now
`the platinum has been
`i
`st
`1 rejected at the
`g o the 28-20 nm
`is 55 ment.
`
`o
`t
`
`N—O—Si—Ti—Hf—Pt—Ni
`
`ap o a rt
`E
`Figure 3. S
`As distributions. The plat n
`seen
`
`y
`
`e
`
`f
`
`T
`
`11 i
`
`r
`
`o
`
`ainlyNi. Ptand
`eV).
`
`Page 4 of 15
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`O – Pt
`
`
`
`OO – As – Ni
`
`
`
`OO – Pt – Ni
`
`
`
`
`Figure 4. STEM EDX maps of a cross section of a NiSi(Pt) layeSTEM EDX maps of a cross section of a NiSi(Pt) layer laser annealed. In this case pr laser annealed. In this case platinum
`
`
`atoms incorporate better inside the NiSi(Pt)atoms incorporate better inside the NiSi(Pt), especially at grain boundaries.(TEM Osiris at 120 keV). specially at grain boundaries.(TEM Osiris at 120 keV).
`
`
`
`2.2 Dopants profiling at nanometer scaleat nanometer scale
`
`
`Knowledge of the dopant (As, P, B) distribution in today’s transistors junctions is necessary to , P, B) distribution in today’s transistors junctions is necessary to , P, B) distribution in today’s transistors junctions is necessary to
`
`
`improve their electrical properties. The detection and visualization of those impurities in nanoscale improve their electrical properties. The detection and visualization of those impurities in nanoscale improve their electrical properties. The detection and visualization of those impurities in nanoscale
`
`
`silicon devices has been highlighted by the ITRSsilicon devices has been highlighted by the ITRS2 as a mandatory and difficult task for the as a mandatory and difficult task for the
`
`
`development of future generation devicesgeneration devices. Today, few characterization techniques are able to map . Today, few characterization techniques are able to map
`
`
`dopant distribution both with a spatial resolution at the nanometer scale coupled with a high dopant distribution both with a spatial resolution at the nanometer scale coupled with a high dopant distribution both with a spatial resolution at the nanometer scale coupled with a high
`sensitivity.
`
`
`Conventional transmission electron microscopy, despite atomic resolution, gives a too weak dopant nal transmission electron microscopy, despite atomic resolution, gives a too weak dopant nal transmission electron microscopy, despite atomic resolution, gives a too weak dopant
`
`
`contrast. However phase change contrast (contrast. However phase change contrast (revealed by holography technique) or inelastic interactions ) or inelastic interactions
`
`
`(measured in spectroscopy modemode) can be exploited and provide alternative solutions. Using native solutions. Using
`
`
`holography, it is possible to map the electrically active dopants holography, it is possible to map the electrically active dopants [3]; however specific specimen ]; however specific specimen
`
`
`preparation (parallel side milling, low amorphisation, no gmilling, low amorphisation, no gallium contamination) using Focused Ion allium contamination) using Focused Ion
`
`Beam (FIB) tool is mandatory to perfBeam (FIB) tool is mandatory to perform resolved electron holography experiments orm resolved electron holography experiments [4]. This
`
`
`
`technique is not used in our lab anymore since the specimen preparation and the minimum specimen technique is not used in our lab anymore since the specimen preparation and the minimum specimen technique is not used in our lab anymore since the specimen preparation and the minimum specimen
`
`thickness are not compatible with nowadays SRAM transistors size (< 100 nm). thickness are not compatible with nowadays SRAM transistors size (< 100 nm).
`
`Recent STEM, EELS and EDX Recent STEM, EELS and EDX spectroscopy developments (high brightness sources spectroscopy developments (high brightness sources [5], new
`
`
`
`spectrometers, aberrations correctorsspectrometers, aberrations correctors…) place these techniques as candidates for sub) place these techniques as candidates for sub-nanometer
`
`
`characterization of doped areas. Howevercharacterization of doped areas. However, sensitivity detection limit is obtained at the price of higsensitivity detection limit is obtained at the price of high
`
`
`local electron doses and silicon radiation damages at 200 keV become unavoidable. Those undesirable local electron doses and silicon radiation damages at 200 keV become unavoidable. Those undesirable local electron doses and silicon radiation damages at 200 keV become unavoidable. Those undesirable
`
`
`effects have been experimentally evaluated and it has been shown that they are significantly reduced if effects have been experimentally evaluated and it has been shown that they are significantly reduced if effects have been experimentally evaluated and it has been shown that they are significantly reduced if
`
`
`the electron probe acceleration is lowered toprobe acceleration is lowered to 120 keV or below [6]. During these studies, the STEM ]. During these studies, the STEM
`
`
`EELS technique, which is compatible with classical FIB lamella preparation, has been optimized on a EELS technique, which is compatible with classical FIB lamella preparation, has been optimized on a EELS technique, which is compatible with classical FIB lamella preparation, has been optimized on a
`
`
`TECNAI F20, for two-dimensional dopant maps from high density SRAM circuits. Using the dimensional dopant maps from high density SRAM circuits. Using the dimensional dopant maps from high density SRAM circuits. Using the
`
`
`Spectrum-Imaging approach [7], the first quantitative maps of arsenic dopant have been demonstrated ], the first quantitative maps of arsenic dopant have been demonstrated ], the first quantitative maps of arsenic dopant have been demonstrated
`
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`from a 40 nm device gate length by recording more than 10nm device gate length by recording more than 10 000 EEL spectra during an hour [000 EEL spectra during an hour [1, 8].
`
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`Figure 5 shows that using this approach, arsenic dopant distribution from Sourc5 shows that using this approach, arsenic dopant distribution from Source, Drain and Low e, Drain and Low
`
`
`Doped Drain (LDD) regions is revealed with a spatial resolution close to 2 nm and a dopant sensitivity Doped Drain (LDD) regions is revealed with a spatial resolution close to 2 nm and a dopant sensitivity Doped Drain (LDD) regions is revealed with a spatial resolution close to 2 nm and a dopant sensitivity
`
`
`in the low 1019 at.cm-3 (0.01%). This two(0.01%). This two-dimensional quantitative dopant map clearly reveals the dimensional quantitative dopant map clearly reveals the
`
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`presence of As inside the poly-siliconsilicon gate and local segregations at the gate edges are evidenced. gate and local segregations at the gate edges are evidenced.
`
`
`Arsenic concentration profiles may be extracted across the LDDArsenic concentration profiles may be extracted across the LDD-Channel length to measure the Channel length to measure the
`
`chemical channel length. This kind of information is relevant for process engineerchemical channel length. This kind of information is relevant for process engineeringing in order to
`
`
`
`optimize implantation conditions and, in consequence, maximize the devices electrical performances.imize implantation conditions and, in consequence, maximize the devices electrical performances.imize implantation conditions and, in consequence, maximize the devices electrical performances.
`
`
`
`
`2 www.itrs.net
`
`IOP Publishing
`17th International Conference on Microscopy of Semiconducting Materials 2011
`Journal of Physics: Conference Series 326 (2011) 012008
`doi:10.1088/1742-6596/326/1/012008
`
`4
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`Page 5 of 15
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`Figure 5. Two-dimensional quantitative arsenic dopant map acquired from a 40 nm gate length dimensional quantitative arsenic dopant map acquired from a 40 nm gate length dimensional quantitative arsenic dopant map acquired from a 40 nm gate length
`
`transistor using the STEM EEL spectrum imaging approachtransistor using the STEM EEL spectrum imaging approach (Osiris TEM).
`
`
`
`In the past EDX spectroscopy compared to EELS suffered from poor signal level detection. This has In the past EDX spectroscopy compared to EELS suffered from poor signal level detection. This has In the past EDX spectroscopy compared to EELS suffered from poor signal level detection. This has
`
`recently changed with the introduction of Silicon Drift Detectors (SDD). recently changed with the introduction of Silicon Drift Detectors (SDD). With the new S/TEM Osirishe new S/TEM Osiris3
`
`
`
`[9], at STMicroelectronics Crolles, it , at STMicroelectronics Crolles, it is now possible to retrieve nanoscale chemical compositional ow possible to retrieve nanoscale chemical compositional
`
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`analyses using STEM EDX. Figure analyses using STEM EDX. Figure 6 presents arsenic and phosphorous dopant maps acquired from a presents arsenic and phosphorous dopant maps acquired from a
`
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`40 nm transistor with a total of (800nm transistor with a total of (800 x 400) pixels for a complete acquisition time of 20 minutes. 400) pixels for a complete acquisition time of 20 minutes.
`
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`Arsenic and phosphorus distributions from Source and Drain are clearly revealed using the STEM ic and phosphorus distributions from Source and Drain are clearly revealed using the STEM ic and phosphorus distributions from Source and Drain are clearly revealed using the STEM
`
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`EDX approach with a high probe current (4EDX approach with a high probe current (4 nA) and a probe size estimated lower than 1nA) and a probe size estimated lower than 1 nm. The
`
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`dopant inside the gate seems to segregate at the polydopant inside the gate seems to segregate at the poly-silicon gate edges. Following the example of . Following the example of
`
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`STEM EELS, the STEM EDX approach leads to precise chemical channel length measurements inside STEM EELS, the STEM EDX approach leads to precise chemical channel length measurements inside STEM EELS, the STEM EDX approach leads to precise chemical channel length measurements inside
`
`
`“real” nanoscale silicon devices. Besides, it is interesting to note the presence of As and P at the top of “real” nanoscale silicon devices. Besides, it is interesting to note the presence of As and P at the top of “real” nanoscale silicon devices. Besides, it is interesting to note the presence of As and P at the top of
`
`
`nitrite spacers which played their role by protecting the LDD from the high energy implant of the d their role by protecting the LDD from the high energy implant of the d their role by protecting the LDD from the high energy implant of the
`Source and Drain regions.
`
`Concentration (a.u.)
`
`
`
`
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`Figure 6. Two-dimensional (non quantitative) dimensional (non quantitative) arsenic (left) and phosphorous (right) dopantarsenic (left) and phosphorous (right) dopant maps
`
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`acquired from a 40 nm gate length transistor using the STnm gate length transistor using the STEM EDX spectrum imaging (Osiris TEMOsiris TEM).
`
`
`
`2.3 Stressors integration and characterizationStressors integration and characterization
`
`
`To enhance carrier mobility and drive current in MOS transistors, several approaches basTo enhance carrier mobility and drive current in MOS transistors, several approaches basTo enhance carrier mobility and drive current in MOS transistors, several approaches based on strain
`
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`engineering have been used in the semiconductor industry [10, 11, 12the semiconductor industry [10, 11, 12]. Unfortunately,. Unfortunately, till very
`
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`recently, no physical characterizationcharacterization techniques were available to measure straiwere available to measure strain through the
`
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`transistor channel with a sufficient sensitivity and spatial resolution. sufficient sensitivity and spatial resolution. Considered for a long time as one Considered for a long time as one
`
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`of the most powerful techniques to measure latticel techniques to measure lattice parameters [13, 14], Convergent Beam Electron Convergent Beam Electron
`
`
`Diffraction (CBED) technique suffers from some drawbacks largtechnique suffers from some drawbacks largely described in the literature [ely described in the literature [15, 16,
`
`17] leading to some difficulties to applyies to apply this technique in case of real devices analysis.
`
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`For a few years now, two TEM basedtwo TEM based techniques have emerged as very promising techniques for hniques for the
`
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`semiconductor field: Nano Beam DiffractionBeam Diffraction (NBD) [18] and Dark-field holography (DF Holograp(DF Holography)
`
`recently developed by the CEMES lab at Toulouse [19y the CEMES lab at Toulouse [19].
`
`
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`3 The first worldwide S/TEM Osiris system has been installed at STMicroelectronics Crolles in April 2010.The first worldwide S/TEM Osiris system has been installed at STMicroelectronics Crolles in April 2010.The first worldwide S/TEM Osiris system has been installed at STMicroelectronics Crolles in April 2010.
`
`IOP Publishing
`17th International Conference on Microscopy of Semiconducting Materials 2011
`Journal of Physics: Conference Series 326 (2011) 012008
`doi:10.1088/1742-6596/326/1/012008
`
`5
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`Page 6 of 15
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`The NBD technique uses a nearly parallel electron beam that can be obtained in a 2technique uses a nearly parallel electron beam that can be obtained in a 2-condenser system condenser system
`
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`by lowering the C2 aperture size down to about 10 µm. The corresponding semiby lowering the C2 aperture size down to about 10 µm. The corresponding semi-convergence angle convergence angle
`
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`classically obtained is 0.3 mrad with a probe size around 5ssically obtained is 0.3 mrad with a probe size around 5-8 nm in a FEI Tecnai F20.8 nm in a FEI Tecnai F20. Recent
`
`
`development on this technique using adevelopment on this technique using an FEI Titan with a 3-condenser system at CEA/Leti at CEA/Leti shows very
`
`
`promising results with strain sensitivity as low as promising results with strain sensitivity as low as 6x10-4 [20]. The main interest of this technique of this technique
`
`
`compared to CBED one is the device ondevice on-axis analysis capability. So, no sample tilt is required no sample tilt is required
`
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`anymore and spatial resolution is spatial resolution is then directly linked to probe size. Figure 7 shows NBD results Figure 7 shows NBD results
`
`
`obtained on a 45 nm PMOS transistor with SiGe source and drain nsistor with SiGe source and drain stressors. Compressive strain stressors. Compressive strain
`
`
`through Si channel along x direction is clearly measured with the corresponding tensile strain along direction is clearly measured with the corresponding tensile strain along direction is clearly measured with the corresponding tensile strain along z
`direction.
`
`
`
`
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`Figure 7. NBD results on a 45 nm metal gate NBD results on a 45 nm metal gate PMOS transistor with SiGe source and drain. (a) STEM source and drain. (a) STEM
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`image of the investigated device. Strain components values along image of the investigated device. Strain components values along x and z directions along line scan directions along line scan
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`(B) under the gate (b), along line scan (A) through source, channel and drain regions (b) and along line (B) under the gate (b), along line scan (A) through source, channel and drain regions (b) and along line (B) under the gate (b), along line scan (A) through source, channel and drain regions (b) and along line
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`scan (C) just below one stressor (d).stressor (d).
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`However strain mapping remains difficult to obtain train mapping remains difficult to obtain with this technique due to large and large and time
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`consuming data processing. Furthermore, NBD technique is consuming data processing. Furthermore, NBD technique is still tricky to apply on low stressed on low stressed
`devices.
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`In this case, dark-field electron holography field electron holography based on the analysis of a hologram obtainedobtained by the
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`interference between one diffracted beam diffracted beam through the region of interest with another throughother through an
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`unstrained (reference) region, could be an could be an alternative. The main advantage of this technique this technique is the
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`principal strain components mappingping feasibility on real devices. STMicroelectronics is involved in the is involved in the
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`development of this technique for for microelectronics field applications through the “HDStrainHDStrain” ANR
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`project carried out by the CEMES lab in Toulouselab in Toulouse.
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`We have developed in particular dedicated sample preparation by coupling backside milling (to developed in particular dedicated sample preparation by coupling backside milling (to developed in particular dedicated sample preparation by coupling backside milling (to
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`avoid curtaining effects) with low energy milling at 8 kV (to limit amorphous layers thickness) in dual ) with low energy milling at 8 kV (to limit amorphous layers thickness) in dual ) with low energy milling at 8 kV (to limit amorphous layers thickness) in dual
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`beam system. The aim is then to obtain paobtain parallel sided lamella with no bending and uniform thicknessand uniform thickness
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`through a large field of view to ensure through a large field of view to ensure high-quality dark-field holography experiments.
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`2.4 Interconnection issue
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`Concerning transistors interconnects (backendtransistors interconnects (backend, BE) issue, one of a main failure modes one of a main failure modes in IC
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`technology is electromigration (EM). This phenomenon islectromigration (EM). This phenomenon is the migration of atoms under electron flow the migration of atoms under electron flow
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`in metal lines leading to formation of voids (figure 8formation of voids (figure 8b) and thus to the loss of chip functionality.chip functionality. To
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`IOP Publishing
`17th International Conference on Microscopy of Semiconducting Materials 2011
`Journal of Physics: Conference Series 326 (2011) 012008
`doi:10.1088/1742-6596/326/1/012008
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`6
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`Page 7 of 15
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`17th International Conference on Microscopy of Semiconducting Materials 2011
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`IOP Publishing
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`Journal of Physics: Conference Series 326 (201 1) 012008
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`doi:10.1088/1742-6596/326/1/012008
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`characterize reliability of interconnects, dedicated EM structures (figure 8a) are tested in accelerated
`conditions (high temperature and current density) and monitored on resistance evolution with time.
`Some studies are currently performed to understand what drives EM (influence of copper
`microstructure?) and to find best process conditions to improve interconnect resistivity (surface
`treatment. impurities adding. . .).
`The first relevant information after an EM test is the localization of the void(s) that need to be
`performed on very small features: 45 nm wide (W) and 100 nm thick ('1) EM copper line geometry for
`the 28 nm node technology (figure 8a). In case of SEM imaging. interconnect is revealed by classical
`FIB cut whereas in case of TEM imaging. lamella preparation is required with thickness less than 45
`nm in this case to avoid any 3D effects as illustrated in Figure 8b.
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`a)
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`hg cunem
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`I I
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`Figure 8. a) Electromigration test structure sample b)TEM image of copper interconnect with small
`void localized under the via.
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`Some experiments are actually performed [21] to show if local microstructure inside a metal line can
`influence or not electromigration mechanism. For this. electron back-scattered diffraction (EBSD)
`technique in an SEM is used to obtain texture and grain size information.
`Figure 9 illustrates an example of global microstructure analysis for 140 nm wide copper lines where
`changing copper deposition process results in much higher (111) texture but also much smaller mean
`gra